Searched full:a6xx (Results 1 – 17 of 17) sorted by relevance
10 <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>24 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>25 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>26 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>79 <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>115 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>122 <!-- a6xx events -->126 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>128 <value name="LABEL" value="63" variants="A6XX-"/>130 <!-- note, some of these are the same as a6xx, just named differently -->[all …]
2222 <domain name="A6XX" width="32" prefix="variant" varset="chip">2237 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>2452 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>2454 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>2555 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>2556 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>2557 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>2558 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>2559 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>2560 <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>[all …]
12 <value name="A6XX" value="6"/>384 but a6xx.
8 <domain name="A6XX" width="32" prefix="variant" varset="chip">
2528 <doc>Guessing that this is the same as a3xx/a6xx.</doc>
11 #include "a6xx.xml.h"687 .a6xx = &(const struct a6xx_info) {719 .a6xx = &(const struct a6xx_info) {749 .a6xx = &(const struct a6xx_info) {774 .a6xx = &(const struct a6xx_info) {797 .a6xx = &(const struct a6xx_info) {821 .a6xx = &(const struct a6xx_info) {845 .a6xx = &(const struct a6xx_info) {871 .a6xx = &(const struct a6xx_info) {898 .a6xx = &(const struct a6xx_info) {[all …]
25 ADRENO_FW_SQE = 0, /* a6xx */27 ADRENO_FW_GMU = 1, /* a6xx */105 const struct a6xx_info *a6xx; member290 * for all a6xx devices, but probably best to limit this in adreno_patchid()635 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
9 #include "a6xx.xml.h"34 * struct a6xx_info - a6xx specific information from device table
502 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) in a6xx_set_hwcg()518 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a6xx_set_hwcg()524 if (!adreno_gpu->info->a6xx->hwcg) { in a6xx_set_hwcg()553 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) in a6xx_set_hwcg()566 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a6xx_set_cp_protect()715 reglist = adreno_gpu->info->a6xx->pwrup_reglist; in a7xx_patch_pwrup_reglist()1179 if (adreno_gpu->info->a6xx->prim_fifo_threshold) in hw_init()1181 adreno_gpu->info->a6xx->prim_fifo_threshold); in hw_init()1884 * There is a different programming path for A6xx targets with an in a6xx_llc_slices_init()
113 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_set_freq()828 const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx; in a6xx_gmu_fw_start()1114 * Warm boot path does not work on newer A6xx GPUs in a6xx_gmu_resume()1407 /* GMU on A6xx votes perfmode on all valid bandwidth */ in a6xx_gmu_rpmh_bw_votes_init()1548 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_rpmh_votes_init()1635 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_pwrlevels_probe()
10 #include "a6xx.xml.h"
710 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_hfi_send_bw_table()
109 For a5xx and a6xx devices this node contains a memory-region that227 then: # Starting with A6xx, the clocks are usually defined in the GMU node291 // Example a6xx (with GMU):
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
198 generated/a6xx.xml.h \
281 * switch-over happened early enough in mesa a6xx bringup that we282 * can disallow relocs for a6xx and newer.
39 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)