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/linux-6.14.4/drivers/iio/adc/
Dpalmas_gpadc.c3 * palmas-adc.c -- TI PALMAS GPADC.
131 static struct palmas_adc_event *palmas_gpadc_get_event(struct palmas_gpadc *adc, in palmas_gpadc_get_event() argument
135 if (adc_chan == adc->event0.channel && dir == adc->event0.direction) in palmas_gpadc_get_event()
136 return &adc->event0; in palmas_gpadc_get_event()
138 if (adc_chan == adc->event1.channel && dir == adc->event1.direction) in palmas_gpadc_get_event()
139 return &adc->event1; in palmas_gpadc_get_event()
144 static bool palmas_gpadc_channel_is_freerunning(struct palmas_gpadc *adc, in palmas_gpadc_channel_is_freerunning() argument
147 return palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_RISING) || in palmas_gpadc_channel_is_freerunning()
148 palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_FALLING); in palmas_gpadc_channel_is_freerunning()
175 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc) in palmas_disable_auto_conversion() argument
[all …]
Dimx93_adc.c3 * NXP i.MX93 ADC driver
22 #define IMX93_ADC_DRIVER_NAME "imx93-adc"
42 /* ADC bit shift */
61 /* ADC status */
102 static void imx93_adc_power_down(struct imx93_adc *adc) in imx93_adc_power_down() argument
107 mcr = readl(adc->regs + IMX93_ADC_MCR); in imx93_adc_power_down()
109 writel(mcr, adc->regs + IMX93_ADC_MCR); in imx93_adc_power_down()
111 ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr, in imx93_adc_power_down()
116 dev_warn(adc->dev, in imx93_adc_power_down()
117 "ADC do not in power down mode, current MSR is %x\n", in imx93_adc_power_down()
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Dimx8qxp-adc.c3 * NXP i.MX8QXP ADC driver
30 #define ADC_DRIVER_NAME "imx8qxp-adc"
46 /* ADC bit shift */
75 /* ADC PARAMETER*/
97 /* Serialise ADC channel reads */
123 static void imx8qxp_adc_reset(struct imx8qxp_adc *adc) in imx8qxp_adc_reset() argument
128 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
130 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
133 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
137 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); in imx8qxp_adc_reset()
[all …]
Dstm32-adc.c3 * This file is part of STM32 ADC driver
31 #include "stm32-adc-core.h"
36 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
94 * struct stm32_adc_ic - ADC internal channels
112 * struct stm32_adc_trig_info - ADC trigger info
122 * struct stm32_adc_calib - optional adc calibration data
132 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
144 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data
210 * @smp_cycles: programmable sampling time (ADC clock cycles)
232 * struct stm32_adc - private data of each ADC IIO instance
[all …]
Drzg2l_adc.c25 #define DRIVER_NAME "rzg2l-adc"
59 * struct rzg2l_adc_hw_params - ADC hardware specific parameters
60 * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
62 * @adsmp_mask: ADC sampling period mask (see ADM3 register)
64 * @default_adcmp: default ADC cmp (see ADM3 register)
95 * struct rzg2l_adc_channel - ADC channel descriptor
96 * @name: ADC channel name
97 * @type: ADC channel type
116 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg) in rzg2l_adc_readl() argument
118 return readl(adc->base + reg); in rzg2l_adc_readl()
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DKconfig3 # ADC drivers
25 tristate "Analog Devices AD4000 ADC Driver"
31 SPI analog to digital converters (ADC).
37 tristate "Analog Device AD4130 ADC Driver"
46 to digital converters (ADC).
52 tristate "Analog Device AD4695 ADC Driver"
59 analog to digital converters (ADC).
68 tristate "Analog Devices AD7091R5 ADC Driver"
73 Say yes here to build support for Analog Devices AD7091R-5 ADC.
76 tristate "Analog Devices AD7091R8 ADC Driver"
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Dti-adc12138.c3 * ADC12130/ADC12132/ADC12138 12-bit plus sign ADC driver
52 * Maximum size needed: 16x 2 bytes ADC data + 8 bytes timestamp.
128 static int adc12138_mode_programming(struct adc12138 *adc, u8 mode, in adc12138_mode_programming() argument
132 .tx_buf = adc->tx_buf, in adc12138_mode_programming()
133 .rx_buf = adc->rx_buf, in adc12138_mode_programming()
139 if (adc->id != adc12138) in adc12138_mode_programming()
142 adc->tx_buf[0] = mode; in adc12138_mode_programming()
144 ret = spi_sync_transfer(adc->spi, &xfer, 1); in adc12138_mode_programming()
148 memcpy(rx_buf, adc->rx_buf, len); in adc12138_mode_programming()
153 static int adc12138_read_status(struct adc12138 *adc) in adc12138_read_status() argument
[all …]
Dingenic-adc.c3 * ADC driver for the Ingenic JZ47xx SoCs
6 * based on drivers/mfd/jz4740-adc.c
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
102 int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
116 struct ingenic_adc *adc = iio_priv(iio_dev); in ingenic_adc_set_adcmd() local
118 mutex_lock(&adc->lock); in ingenic_adc_set_adcmd()
121 readl(adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
128 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
134 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
142 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
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Dstm32-dfsdm-adc.c3 * This file is the ADC part of the STM32 DFSDM driver
11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
79 /* ADC specific */
318 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); in stm32_dfsdm_compute_all_osrs() local
319 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; in stm32_dfsdm_compute_all_osrs()
339 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); in stm32_dfsdm_start_channel() local
340 struct regmap *regmap = adc->dfsdm->regmap; in stm32_dfsdm_start_channel()
345 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) { in stm32_dfsdm_start_channel()
359 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); in stm32_dfsdm_stop_channel() local
360 struct regmap *regmap = adc->dfsdm->regmap; in stm32_dfsdm_stop_channel()
[all …]
Dmcp3911.c106 int (*config)(struct mcp3911 *adc, bool external_vref);
107 int (*get_osr)(struct mcp3911 *adc, u32 *val);
108 int (*set_osr)(struct mcp3911 *adc, u32 val);
109 int (*enable_offset)(struct mcp3911 *adc, bool enable);
110 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
111 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
112 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
132 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) in mcp3911_read() argument
136 reg = MCP3911_REG_READ(reg, adc->dev_addr); in mcp3911_read()
137 ret = spi_write_then_read(adc->spi, &reg, 1, val, len); in mcp3911_read()
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Dqcom-spmi-adc5.c10 #include <linux/iio/adc/qcom-vadc-common.h>
104 * struct adc5_channel_prop - ADC channel property.
113 * @avg_samples: ability to provide single result from the ADC
133 * struct adc5_chip - ADC private structure.
136 * @base: base address for the ADC peripheral.
137 * @nchannels: number of ADC channels.
138 * @chan_props: array of ADC channel properties.
141 * @complete: ADC result notification after interrupt is received.
142 * @lock: ADC lock for access to the peripheral.
158 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len) in adc5_read() argument
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Dlpc18xx_adc.c3 * IIO ADC driver for NXP LPC18xx ADC
26 /* LPC18XX ADC registers and bits */
69 static int lpc18xx_adc_read_chan(struct lpc18xx_adc *adc, unsigned int ch) in lpc18xx_adc_read_chan() argument
74 reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; in lpc18xx_adc_read_chan()
75 writel(reg, adc->base + LPC18XX_ADC_CR); in lpc18xx_adc_read_chan()
77 ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, in lpc18xx_adc_read_chan()
80 dev_warn(adc->dev, "adc read timed out\n"); in lpc18xx_adc_read_chan()
91 struct lpc18xx_adc *adc = iio_priv(indio_dev); in lpc18xx_adc_read_raw() local
95 mutex_lock(&adc->lock); in lpc18xx_adc_read_raw()
96 *val = lpc18xx_adc_read_chan(adc, chan->channel); in lpc18xx_adc_read_raw()
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Dti-adc084s021.c5 * Driver for Texas Instruments' ADC084S021 ADC chip.
68 * adc084s021_adc_conversion() - Read an ADC channel and return its value.
70 * @adc: The ADC SPI data.
73 static int adc084s021_adc_conversion(struct adc084s021 *adc, __be16 *data) in adc084s021_adc_conversion() argument
75 int n_words = (adc->spi_trans.len >> 1) - 1; /* Discard first word */ in adc084s021_adc_conversion()
79 ret = spi_sync(adc->spi, &adc->message); in adc084s021_adc_conversion()
84 *(data + i) = adc->rx_buf[i + 1]; in adc084s021_adc_conversion()
93 struct adc084s021 *adc = iio_priv(indio_dev); in adc084s021_read_raw() local
103 ret = regulator_enable(adc->reg); in adc084s021_read_raw()
109 adc->tx_buf[0] = channel->channel << 3; in adc084s021_read_raw()
[all …]
Dmcp3564.c3 * IIO driver for MCP356X/MCP356XR and MCP346X/MCP346XR series ADC chip family
14 …MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180…
64 * ADC Output Data Format 32-bit (25-bit right justified data + Channel ID):
65 * CHID[3:0] + SGN extension (4 bits) + 24-bit ADC data.
70 * ADC Output Data Format 32-bit (25-bit right justified data):
71 * SGN extension (8-bit) + 24-bit ADC data.
76 * ADC Output Data Format 32-bit (24-bit left justified data):
77 * 24-bit ADC data + 0x00 (8-bit).
78 * It does not allow overrange (ADC code locked to 0xFFFFFF or 0x800000).
82 * ADC Output Data Format 24-bit (default ADC coding):
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Dti-adc0832.c3 * ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
33 * Max size needed: 16x 1 byte ADC data + 8 bytes timestamp
120 static int adc0831_adc_conversion(struct adc0832 *adc) in adc0831_adc_conversion() argument
122 struct spi_device *spi = adc->spi; in adc0831_adc_conversion()
125 ret = spi_read(spi, &adc->rx_buf, 2); in adc0831_adc_conversion()
132 return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6); in adc0831_adc_conversion()
135 static int adc0832_adc_conversion(struct adc0832 *adc, int channel, in adc0832_adc_conversion() argument
138 struct spi_device *spi = adc->spi; in adc0832_adc_conversion()
140 .tx_buf = adc->tx_buf, in adc0832_adc_conversion()
141 .rx_buf = adc->rx_buf, in adc0832_adc_conversion()
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Dad7944.c3 * Analog Devices AD7944/85/86 PulSAR ADC family driver.
137 static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc, in ad7944_3wire_cs_mode_init_msg() argument
140 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns in ad7944_3wire_cs_mode_init_msg()
141 : adc->timing_spec->conv_ns; in ad7944_3wire_cs_mode_init_msg()
142 struct spi_transfer *xfers = adc->xfers; in ad7944_3wire_cs_mode_init_msg()
166 xfers[2].rx_buf = &adc->sample.raw; in ad7944_3wire_cs_mode_init_msg()
170 spi_message_init_with_transfers(&adc->msg, xfers, 3); in ad7944_3wire_cs_mode_init_msg()
172 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); in ad7944_3wire_cs_mode_init_msg()
175 static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc, in ad7944_4wire_mode_init_msg() argument
178 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns in ad7944_4wire_mode_init_msg()
[all …]
Dmxs-lradc-adc.c3 * Freescale MXS LRADC ADC driver
134 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_read_single() local
135 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_read_single()
148 reinit_completion(&adc->completion); in mxs_lradc_adc_read_single()
157 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
158 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
161 if (test_bit(chan, &adc->is_divided)) in mxs_lradc_adc_read_single()
163 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
166 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
170 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
[all …]
Dmax1241.c3 * MAX1241 low-power, 12-bit serial ADC
41 static int max1241_read(struct max1241 *adc) in max1241_read() argument
57 .rx_buf = &adc->data, in max1241_read()
62 return spi_sync_transfer(adc->spi, xfers, ARRAY_SIZE(xfers)); in max1241_read()
70 struct max1241 *adc = iio_priv(indio_dev); in max1241_read_raw() local
74 mutex_lock(&adc->lock); in max1241_read_raw()
76 if (adc->shutdown) { in max1241_read_raw()
77 gpiod_set_value(adc->shutdown, 0); in max1241_read_raw()
79 ret = max1241_read(adc); in max1241_read_raw()
80 gpiod_set_value(adc->shutdown, 1); in max1241_read_raw()
[all …]
Dmcp320x.c8 * Driver for following ADC chips from Microchip Technology's:
72 * struct mcp320x - Microchip SPI ADC instance
74 * @msg: SPI message to select a channel and receive a value from the ADC
80 * @chip_info: ADC properties
120 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel, in mcp320x_adc_conversion() argument
125 if (adc->chip_info->conv_time) { in mcp320x_adc_conversion()
126 ret = spi_sync(adc->spi, &adc->start_conv_msg); in mcp320x_adc_conversion()
130 usleep_range(adc->chip_info->conv_time, in mcp320x_adc_conversion()
131 adc->chip_info->conv_time + 100); in mcp320x_adc_conversion()
134 memset(&adc->rx_buf, 0, sizeof(adc->rx_buf)); in mcp320x_adc_conversion()
[all …]
Drn5t618-adc.c3 * ADC driver for the RICOH RN5T618 power management chip family
83 struct rn5t618_adc_data *adc = data; in rn5t618_adc_irq() local
88 regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC1, 0); in rn5t618_adc_irq()
89 regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC2, 0); in rn5t618_adc_irq()
91 ret = regmap_read(adc->rn5t618->regmap, RN5T618_IR_ADC3, &r); in rn5t618_adc_irq()
93 dev_err(adc->dev, "failed to read IRQ status: %d\n", ret); in rn5t618_adc_irq()
95 regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC3, 0); in rn5t618_adc_irq()
98 complete(&adc->conv_completion); in rn5t618_adc_irq()
107 struct rn5t618_adc_data *adc = iio_priv(iio_dev); in rn5t618_adc_read() local
120 ret = regmap_update_bits(adc->rn5t618->regmap, RN5T618_ADCCNT3, in rn5t618_adc_read()
[all …]
/linux-6.14.4/drivers/mfd/
Dpcf50633-adc.c2 /* NXP PCF50633 ADC Driver
11 * NOTE: This driver does not yet support subtractive ADC mode, which means
23 #include <linux/mfd/pcf50633/adc.h>
62 /* start ADC conversion on selected channel */ in adc_setup()
69 struct pcf50633_adc *adc = __to_adc(pcf); in trigger_next_adc_job_if_any() local
72 head = adc->queue_head; in trigger_next_adc_job_if_any()
74 if (!adc->queue[head]) in trigger_next_adc_job_if_any()
77 adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg); in trigger_next_adc_job_if_any()
83 struct pcf50633_adc *adc = __to_adc(pcf); in adc_enqueue_request() local
86 mutex_lock(&adc->queue_mutex); in adc_enqueue_request()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iio/adc/
Dst,stm32-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
7 title: STMicroelectronics STM32 ADC
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
19 Each STM32 ADC block can have up to 3 ADC instances.
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
29 - st,stm32mp1-adc-core
30 - st,stm32mp13-adc-core
37 One or more interrupts for ADC block, depending on part used:
[all …]
Dsamsung,exynos-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
7 title: Samsung Exynos Analog to Digital Converter (ADC)
16 - samsung,exynos-adc-v1 # Exynos5250
17 - samsung,exynos-adc-v2
18 - samsung,exynos3250-adc
19 - samsung,exynos4212-adc # Exynos4212 and Exynos4412
20 - samsung,exynos7-adc
21 - samsung,s3c2410-adc
22 - samsung,s3c2416-adc
23 - samsung,s3c2440-adc
[all …]
Datmel,sama9260-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama9260-adc.yaml#
7 title: AT91 sama9260 and similar Analog to Digital Converter (ADC)
15 - atmel,at91sam9260-adc
16 - atmel,at91sam9rl-adc
17 - atmel,at91sam9g45-adc
18 - atmel,at91sam9x5-adc
19 - atmel,at91sama5d3-adc
36 atmel,adc-channels-used:
40 atmel,adc-startup-time:
43 Startup Time of the ADC in microseconds as defined in the datasheet
[all …]
Dqcom,pm8018-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
13 The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
14 oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
19 - qcom,pm8018-adc
20 - qcom,pm8038-adc
21 - qcom,pm8058-adc
22 - qcom,pm8921-adc
27 ADC base address in the PMIC, typically 0x197.
62 - adc-channel@c
63 - adc-channel@d
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