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/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/linux-6.14.4/arch/riscv/boot/dts/sophgo/
Dcv1800b.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
19 compatible = "sophgo,cv1800b-pinctrl";
22 reg-names = "sys", "rtc";
27 &plic {
28 compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
32 compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
36 compatible = "sophgo,cv1800-clk";
Dcv1812h.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
21 compatible = "sophgo,cv1812h-pinctrl";
24 reg-names = "sys", "rtc";
29 &plic {
30 compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
34 compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
38 compatible = "sophgo,cv1810-clk";
Dsg2002.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
21 compatible = "sophgo,sg2002-pinctrl";
24 reg-names = "sys", "rtc";
29 &plic {
30 compatible = "sophgo,sg2002-plic", "thead,c900-plic";
34 compatible = "sophgo,sg2002-clint", "thead,c900-clint";
38 compatible = "sophgo,sg2000-clk";
42 compatible = "sophgo,sg2002-dwcmshc";
Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
17 #address-cells = <2>;
18 #size-cells = <2>;
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/linux-6.14.4/arch/riscv/boot/dts/allwinner/
Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <[email protected]>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
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/linux-6.14.4/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux-6.14.4/drivers/irqchip/
Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "riscv-plic: " fmt
25 * This driver implements a version of the RISC-V PLIC with the actual layout
28 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
31 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
112 raw_spin_lock_irqsave(&handler->enable_lock, flags); in plic_toggle()
113 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
114 raw_spin_unlock_irqrestore(&handler->enable_lock, flags); in plic_toggle()
125 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
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