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/linux-6.14.4/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <[email protected]>
11 - Andrew Lunn <[email protected]>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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/linux-6.14.4/arch/arm/boot/dts/broadcom/
Dbcm11351.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012-2013 Broadcom Corporation
4 #include <dt-bindings/clock/bcm281xx.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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Dbcm2166x-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
11 #include <dt-bindings/clock/bcm21664.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 hub: hub-bus@34000000 {
21 compatible = "simple-bus";
23 #address-cells = <1>;
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/linux-6.14.4/drivers/media/i2c/
Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
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/linux-6.14.4/arch/arm64/boot/dts/amd/
Damd-seattle-clks.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
19 clock-output-names = "ccpclk_375mhz";
23 compatible = "fixed-clock";
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/linux-6.14.4/arch/arm/boot/dts/intel/axm/
Daxm5516-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
74 compatible = "arm,cortex-a15";
76 clock-frequency = <1400000000>;
77 cpu-release-addr = <0>; // Fixed by the boot loader
82 compatible = "arm,cortex-a15";
84 clock-frequency = <1400000000>;
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/linux-6.14.4/arch/arm64/boot/dts/arm/
Djuno-clocks.dtsi4 * Copyright (c) 2013-2014 ARM Ltd
11 soc_uartclk: clock-7372800 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <7372800>;
15 clock-output-names = "juno:uartclk";
18 soc_usb48mhz: clock-48000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <48000000>;
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/linux-6.14.4/arch/nios2/boot/dts/
D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
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/linux-6.14.4/arch/arc/boot/dts/
Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/linux-6.14.4/Documentation/netlink/specs/
Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
41 -
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <[email protected]>
11 - Stephen Boyd <[email protected]>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
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Dsilabs,si570.txt2 I2C clock generators.
5 This binding uses the common clock binding[1]. Details about the devices can be
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
15 - compatible: Shall be one of "silabs,si570", "silabs,si571",
17 - reg: I2C device address.
18 - #clock-cells: From common clock bindings: Shall be 0.
19 - factory-fout: Factory set default frequency. This frequency is part specific.
20 The correct frequency for the part used has to be provided in
23 - temperature-stability: Temperature stability of the device in PPM. Should be
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/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <[email protected]>
11 - Jagan Teki <[email protected]>
12 - Marek Szyprowski <[email protected]>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
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/linux-6.14.4/drivers/staging/sm750fb/
Dddk750_chip.c1 // SPDX-License-Identifier: GPL-2.0
52 * This function set up the main chip clock.
54 * Input: Frequency to be set.
56 static void set_chip_clock(unsigned int frequency) in set_chip_clock() argument
60 /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ in set_chip_clock()
64 if (frequency) { in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
74 * up the exact clock required by the User. in set_chip_clock()
76 * possible clock. in set_chip_clock()
78 sm750_calc_pll_value(frequency, &pll); in set_chip_clock()
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/linux-6.14.4/arch/arm/boot/dts/nvidia/
Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
10 clock@60006000 {
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
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Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
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Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
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/linux-6.14.4/drivers/clk/
Dclk-si570.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2011 - 2021 Xilinx Inc.
14 #include <linux/clk-provider.h>
54 * @max_freq: Maximum frequency for this device
64 * @hw: Clock hw struct
68 * @fxtal: Factory xtal frequency
69 * @n1: Clock divider N1
70 * @hs_div: Clock divider HSDIV
71 * @rfreq: Clock multiplier RFREQ
72 * @frequency: Current output frequency
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/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <[email protected]>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
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/linux-6.14.4/Documentation/devicetree/bindings/net/wireless/
Dti,wlcore.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <[email protected]>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
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/linux-6.14.4/drivers/clk/pxa/
Dclk-pxa2xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 #define CCCR (0x0000) /* Core Clock Configuration Register */
6 #define CCSR (0x000C) /* Core Clock Status Register */
7 #define CKEN (0x0004) /* Clock Enable Register */
10 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
11 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
12 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
25 #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
26 #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
27 #define CKEN_MEMC (22) /* Memory Controller Clock Enable */
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/linux-6.14.4/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_vt.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
11 compatible = "altr,socfpga-vt", "altr,socfpga";
27 clock-frequency = <10000000>;
33 broken-cd;
34 bus-width = <4>;
35 cap-mmc-highspeed;
36 cap-sd-highspeed;
40 phy-mode = "gmii";
45 clock-frequency = <7000000>;
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/linux-6.14.4/arch/riscv/boot/dts/starfive/
Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
25 stdout-path = "serial0:115200n8";
33 gpio-restart {
34 compatible = "gpio-restart";
39 pwmdac_codec: audio-codec {
40 compatible = "linux,spdif-dit";
41 #sound-dai-cells = <0>;
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/linux-6.14.4/Documentation/devicetree/bindings/media/i2c/
Daptina,mt9p031.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <[email protected]>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
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