Searched +full:cn10k +full:- +full:ddr +full:- +full:pmu (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Marvell CN10K DDR performance monitor10 - Bharat Bhushan <[email protected]>15 - enum:16 - marvell,cn10k-ddr-pmu22 - compatible23 - reg[all …]
1 # SPDX-License-Identifier: GPL-2.0-only10 tristate "ARM CCI PMU driver"14 Support for PMU events monitoring on the ARM CCI (Cache Coherent17 If compiled as a module, it will be called arm-cci.20 bool "support CCI-400"25 CCI-400 provides 4 independent event counters counting events related29 bool "support CCI-500/CCI-550"33 CCI-500/CCI-550 both provide 8 independent event counters, which can41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)45 tristate "Arm CMN-600 PMU support"[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver5 * Copyright (C) 2021-2024 Marvell.54 /* Two dedicated event counters for DDR reads and writes */61 * DO NOT change these event-id numbers, they are used to148 struct pmu pmu; member161 void (*enable_read_freerun_counter)(struct cn10k_ddr_pmu *pmu,163 void (*enable_write_freerun_counter)(struct cn10k_ddr_pmu *pmu,165 void (*clear_read_freerun_counter)(struct cn10k_ddr_pmu *pmu);166 void (*clear_write_freerun_counter)(struct cn10k_ddr_pmu *pmu);[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-[email protected]88 F: drivers/scsi/3w-*[all …]