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| /linux-6.14.4/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ |
| D | stall.json | 4 …"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no oper…
8 …"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no oper…
32 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when no instructions …
36 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there i…
40 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there i…
44 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there i…
48 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when the frontend is …
52 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the fro…
56 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the fro…
60 …"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when operati…
[all …]
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| D | l1d_cache.json | 75 …"BriefDescription": "This event counts access counted by L1D_CACHE that is due to a hardware prefe…
79 …"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a …
83 …"BriefDescription": "This event counts demand read counted by L1D_CACHE_RD that hits in the Level …
87 …"BriefDescription": "This event counts demand write counted by L1D_CACHE_WR that hits in the Level…
91 …"BriefDescription": "This event counts access counted by L1D_CACHE that hits in the Level 1 data c…
95 …"BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_RD that hits a cache…
99 …"BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_WR that hits a cache…
103 …"BriefDescription": "This event counts fetch counted by either Level 1 data hardware prefetch or L…
107 …"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a re…
111 …"BriefDescription": "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL…
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| D | l1i_cache.json | 26 …"BriefDescription": "This event counts access counted by L1I_CACHE that is due to a hardware prefe…
30 …"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a …
34 …"BriefDescription": "This event counts demand fetch counted by L1I_CACHE_DM_RD that hits in the Le…
38 …"BriefDescription": "This event counts access counted by L1I_CACHE that hits in the Level 1 instru…
42 …"BriefDescription": "This event counts demand access counted by L1I_CACHE_HIT_RD that hits a cache…
46 …"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a re…
50 …"BriefDescription": "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL…
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| D | l2_cache.json | 122 …"BriefDescription": "This event counts access counted by L2D_CACHE that is due to a hardware prefe…
126 …"BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a …
130 …"BriefDescription": "This event counts demand read counted by L2D_CACHE_RD that hits in the Level …
134 …"BriefDescription": "This event counts demand write counted by L2D_CACHE_WR that hits in the Level…
138 …"BriefDescription": "This event counts access counted by L2D_CACHE that hits in the Level 2 data c…
142 …"BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_RD that hits a recen…
146 …"BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_WR that hits a recen…
150 …"BriefDescription": "This event counts fetch counted by either Level 2 data hardware prefetch or L…
154 …"BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_PRF that causes a re…
158 …"BriefDescription": "The counter counts by the number of cache refills counted by L2D_CACHE_REFILL…
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| D | sve.json | 140 …"BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_S…
144 …"BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_S…
224 … counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPE…
228 …r operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
232 …t counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPE…
236 …r operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
240 …t counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPE…
244 …r operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
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| D | tlb.json | 332 …"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the resul…
336 …"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the resul…
340 …"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the resul…
344 …"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the resul…
348 …"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the resul…
352 …"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the resul…
356 …"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the resul…
360 …"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the resul…
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| D | ll_cache.json | 4 …"BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation…
8 …"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3…
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| /linux-6.14.4/tools/perf/pmu-events/arch/powerpc/power10/ |
| D | others.json | 20 …e L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, b…
45 …es not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time."
50 …es not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time."
55 …e instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time."
60 …e instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time."
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| /linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| D | mmu.json | 9 …f a Stage 1 translation table walk handled by the MMU. This event is not counted when it is access…
12 …f a Stage 1 translation table walk handled by the MMU. This event is not counted when it is access…
15 …f a Stage 2 translation table walk handled by the MMU. This event is not counted when it is access…
18 …f a Stage 2 translation table walk handled by the MMU. This event is not counted when it is access…
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| /linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | retired.json | 16 …EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers …
20 … also counted. Note that exception generating instructions, exception return instructions and cont…
24 …"PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a p…
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| D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
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| D | tlb.json | 28 …counted even if the translation ended up taking a translation fault for reasons different than EPD…
32 …counted even if the translation ended up taking a translation fault for reasons different than EPD…
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| D | l2_cache.json | 12 …ta outside the CPU and snoops which return data from an L1 cache are not counted. Data would not b…
28 …ption": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. …
32 …tion": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. …
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| /linux-6.14.4/tools/lib/perf/include/internal/ |
| D | rc_check.h | 24 * counted structs. It leverages address and leak sanitizers to make sure gets
36 /* Declare a reference counted struct variable. */
41 * reference counted struct.
70 /* Declare a reference counted struct variable. */
75 * reference counted struct.
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| /linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
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| D | retired.json | 16 …EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers …
20 …whether the branch is taken or not. Instructions that explicitly write to the PC are also counted."
24 …"PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a p…
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| D | l2_cache.json | 12 …ta outside the CPU and snoops which return data from an L1 cache are not counted. Data would not b…
28 …ption": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. …
32 …tion": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. …
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| D | l1i_cache.json | 4 …may include accessing multiple instructions, but the single cache line allocation is counted once."
8 …truction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
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| /linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
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| D | retired.json | 16 …EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers …
20 …whether the branch is taken or not. Instructions that explicitly write to the PC are also counted."
24 …"PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a p…
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| D | l2_cache.json | 12 …ta outside the CPU and snoops which return data from an L1 cache are not counted. Data would not b…
28 …ption": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. …
32 …tion": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. …
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| /linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| D | cache.json | 105 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
108 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
171 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
174 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
177 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
180 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
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| /linux-6.14.4/Documentation/userspace-api/media/dvb/ |
| D | frontend-stat-properties.rst | 116 - ``FE_SCALE_COUNTER`` - Number of error bits counted before the inner
144 - ``FE_SCALE_COUNTER`` - Number of bits counted while measuring
173 - ``FE_SCALE_COUNTER`` - Number of error bits counted after the inner
201 - ``FE_SCALE_COUNTER`` - Number of bits counted while measuring
222 - ``FE_SCALE_COUNTER`` - Number of error blocks counted after the outer
244 - ``FE_SCALE_COUNTER`` - Number of blocks counted while measuring
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| /linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| D | cache.json | 31 … the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.",
35 …data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted",
39 …ch do not write data outside of the core and snoops which return data from the L1 are not counted",
62 …data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' tr…
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| /linux-6.14.4/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | virtual-memory.json | 36 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
55 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
65 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
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