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/linux-6.14.4/drivers/clk/renesas/
DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dr9a07g054.dtsi9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
[all …]
Dr9a07g044.dtsi9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
[all …]
Dr9a07g043.dtsi8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
[all …]
Dr9a09g057.dtsi8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
218 clocks = <&cpg CPG_MOD 0x5>;
219 power-domains = <&cpg>;
220 resets = <&cpg 0x36>;
226 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
233 power-domains = <&cpg>;
[all …]
Dr9a08g045.dtsi9 #include <dt-bindings/clock/r9a08g045-cpg.h>
42 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
83 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
85 power-domains = <&cpg>;
86 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
101 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
103 power-domains = <&cpg>;
104 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
119 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
121 power-domains = <&cpg>;
[all …]
Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
Dhihope-rev4.dtsi96 clocks = <&cpg CPG_MOD 1005>,
97 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
98 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
99 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
100 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
101 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
102 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
103 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
104 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
105 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
95 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
165 clocks = <&cpg CPG_MOD 402>;
167 resets = <&cpg 402>;
181 clocks = <&cpg CPG_MOD 912>;
183 resets = <&cpg 912>;
196 clocks = <&cpg CPG_MOD 911>;
198 resets = <&cpg 911>;
211 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
98 clocks = <&cpg CPG_MOD 402>;
100 resets = <&cpg 402>;
114 clocks = <&cpg CPG_MOD 912>;
116 resets = <&cpg 912>;
129 clocks = <&cpg CPG_MOD 911>;
131 resets = <&cpg 911>;
144 clocks = <&cpg CPG_MOD 910>;
146 resets = <&cpg 910>;
159 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
82 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
93 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
150 clocks = <&cpg CPG_MOD 402>;
152 resets = <&cpg 402>;
166 clocks = <&cpg CPG_MOD 912>;
168 resets = <&cpg 912>;
181 clocks = <&cpg CPG_MOD 911>;
183 resets = <&cpg 911>;
196 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
179 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
193 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
209 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
222 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
235 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
248 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
359 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a774a1.dtsi10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
129 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
157 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
274 clocks = <&cpg CPG_MOD 402>;
276 resets = <&cpg 402>;
290 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a77961.dtsi8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
181 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
194 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
207 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
220 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
323 clocks = <&cpg CPG_MOD 402>;
325 resets = <&cpg 402>;
339 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a774b1.dtsi10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
94 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
158 clocks = <&cpg CPG_MOD 402>;
160 resets = <&cpg 402>;
174 clocks = <&cpg CPG_MOD 912>;
176 resets = <&cpg 912>;
189 clocks = <&cpg CPG_MOD 911>;
191 resets = <&cpg 911>;
204 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77960.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
181 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
194 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
207 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
220 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
323 clocks = <&cpg CPG_MOD 402>;
325 resets = <&cpg 402>;
339 clocks = <&cpg CPG_MOD 912>;
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
[all …]
/linux-6.14.4/arch/arm/boot/dts/renesas/
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
71 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
132 clocks = <&cpg CPG_MOD 402>;
134 resets = <&cpg 402>;
148 clocks = <&cpg CPG_MOD 912>;
150 resets = <&cpg 912>;
163 clocks = <&cpg CPG_MOD 911>;
165 resets = <&cpg 911>;
178 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
122 clocks = <&cpg CPG_MOD 402>;
124 resets = <&cpg 402>;
138 clocks = <&cpg CPG_MOD 912>;
140 resets = <&cpg 912>;
153 clocks = <&cpg CPG_MOD 911>;
155 resets = <&cpg 911>;
168 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
58 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
58 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
77 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
165 clocks = <&cpg CPG_MOD 402>;
167 resets = <&cpg 402>;
181 clocks = <&cpg CPG_MOD 912>;
183 resets = <&cpg 912>;
196 clocks = <&cpg CPG_MOD 911>;
198 resets = <&cpg 911>;
211 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
73 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
139 clocks = <&cpg CPG_MOD 912>;
141 resets = <&cpg 912>;
154 clocks = <&cpg CPG_MOD 911>;
156 resets = <&cpg 911>;
169 clocks = <&cpg CPG_MOD 910>;
171 resets = <&cpg 910>;
184 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
166 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
178 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
190 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
202 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
278 clocks = <&cpg CPG_MOD 402>;
[all …]

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