Searched +full:eyeq6h +full:- +full:acc +full:- +full:olb (Results 1 – 4 of 4) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/soc/mobileye/ |
| D | mobileye,eyeq5-olb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grégory Clement <[email protected]>
11 - Théo Lebrun <[email protected]>
12 - Vladimir Kondratiev <[email protected]>
15 OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks,
17 instance. EyeQ6H hosts seven instances.
22 - enum:
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| /linux-6.14.4/arch/mips/boot/dts/mobileye/ |
| D | eyeq6h.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
8 #include <dt-bindings/clock/mobileye,eyeq5-clk.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
28 cpu_intc: interrupt-controller {
29 compatible = "mti,cpu-interrupt-controller";
30 interrupt-controller;
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| /linux-6.14.4/drivers/clk/ |
| D | clk-eyeq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PLL clock driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
6 * - Read-only PLLs, all derived from the same main crystal clock.
7 * - It also exposes divider clocks, those are children to PLLs.
8 * - Fixed factor clocks, children to PLLs.
11 * shared region called OLB. Some PLLs and fixed-factors are initialised early
14 * We use eqc_ as prefix, as-in "EyeQ Clock", but way shorter.
23 #define pr_fmt(fmt) "clk-eyeq: " fmt
29 #include <linux/clk-provider.h>
34 #include <linux/io-64-nonatomic-hi-lo.h>
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| /linux-6.14.4/drivers/reset/ |
| D | reset-eyeq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
5 * Controllers live in a shared register region called OLB. EyeQ5 and EyeQ6L
6 * have a single OLB instance for a single reset controller. EyeQ6H has seven
7 * OLB instances; three host reset controllers.
13 * Domain types define expected behavior: one-register-per-reset,
14 * one-bit-per-reset, status detection method, busywait duration, etc.
16 * We use eqr_ as prefix, as-in "EyeQ Reset", but way shorter.
52 * Known resets in EyeQ6H west/east (type EQR_EYEQ6H_SARCR):
54 * 4. UART1 5. I2C0 6. I2C1 7. -hole-
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