| /linux-6.14.4/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <[email protected]>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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| D | lattice-machxo2-spi.txt | 1 Lattice MachXO2 Slave SPI FPGA Manager
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
24 fpga_mgr_spi: fpga-mgr@0 {
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| D | xlnx,pr-decoupler.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <[email protected]>
13 - $ref: fpga-bridge.yaml#
17 decouplers/fpga bridges. The controller can decouple/disable the bridges
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
28 Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
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| /linux-6.14.4/Documentation/driver-api/fpga/ |
| D | fpga-region.rst | 1 FPGA Region
5 --------
7 This document is meant to be a brief overview of the FPGA region API usage. A
11 For the purposes of this API document, let's just say that a region associates
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
14 program a region.
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
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| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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| D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
14 * lock the region's mutex
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
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| D | index.rst | 2 FPGA Subsystem
11 fpga-mgr
12 fpga-bridge
13 fpga-region
14 fpga-programming
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| /linux-6.14.4/drivers/fpga/ |
| D | of-fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
22 { .compatible = "fpga-region", },
28 * of_fpga_region_find - find FPGA region
29 * @np: device node of FPGA Region
31 * Caller will need to put_device(®ion->dev) when done.
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| D | fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to an fpga region
37 * @region: FPGA Region struct
39 * Caller should call fpga_region_put() when done with region.
43 * * -EBUSY if someone already has a reference to the region.
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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| D | dfl-fme-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-mgr.h>
18 #include <linux/fpga/fpga-region.h>
20 #include "dfl-fme-pr.h"
22 static int fme_region_get_bridges(struct fpga_region *region) in fme_region_get_bridges() argument
24 struct dfl_fme_region_pdata *pdata = region->priv; in fme_region_get_bridges()
25 struct device *dev = &pdata->br->dev; in fme_region_get_bridges()
27 return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list); in fme_region_get_bridges()
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| D | dfl-fme-pr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga-bridge.h>
25 #include <linux/fpga/fpga-region.h>
26 #include <linux/fpga-dfl.h>
29 #include "dfl-fme.h"
30 #include "dfl-fme-pr.h"
37 list_for_each_entry(fme_region, &fme->region_list, node) in dfl_fme_region_find_by_port_id()
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
12 obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
13 obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
14 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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| D | dfl-fme-pr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
24 * struct dfl_fme_region - FME fpga region data structure
26 * @region: platform device of the FPGA region.
28 * @port_id: indicate which port this region connected to.
31 struct platform_device *region; member
37 * struct dfl_fme_region_pdata - platform data for FME region platform device.
39 * @mgr: platform device of the FPGA manager.
40 * @br: platform device of the FPGA bridge.
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| /linux-6.14.4/include/linux/fpga/ |
| D | fpga-region.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
13 * struct fpga_region_info - collection of parameters an FPGA Region
14 * @mgr: fpga region manager
15 * @compat_id: FPGA region id for compatibility check.
16 * @priv: fpga region private data
28 int (*get_bridges)(struct fpga_region *region);
32 * struct fpga_region - FPGA Region structure
33 * @dev: FPGA Region device
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| D | fpga-mgr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FPGA Framework
5 * Copyright (C) 2013-2016 Altera Corporation
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
27 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
29 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
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| /linux-6.14.4/drivers/fpga/tests/ |
| D | fpga-region-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
32 struct fpga_region *region; member
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
61 * Fake FPGA manager that implements only the write op to count the number
64 * of the Region.
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for KUnit test suites for the FPGA subsystem
6 obj-$(CONFIG_FPGA_KUNIT_TESTS) += fpga-mgr-test.o fpga-bridge-test.o fpga-region-test.o
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| /linux-6.14.4/Documentation/fpga/ |
| D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <[email protected]>
8 - Xiao Guangrong <[email protected]>
9 - Wu Hao <[email protected]>
10 - Xu Yilun <[email protected]>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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| /linux-6.14.4/include/uapi/linux/ |
| D | fpga-dfl.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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| /linux-6.14.4/Documentation/ABI/testing/ |
| D | sysfs-class-fpga-region | 1 What: /sys/class/fpga_region/<region>/compat_id
5 Description: FPGA region id for compatibility check, e.g. compatibility
6 of the FPGA reconfiguration hardware and image. This value
8 FPGA region. This interface returns the compat_id value or
9 just error code -ENOENT in case compat_id is not used.
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| D | sysfs-platform-dfl-fme | 1 What: /sys/bus/platform/devices/dfl-fme.0/ports_num
5 Description: Read-only. One DFL FPGA device may have more than 1
7 number of ports on the FPGA device when read it.
9 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_id
13 Description: Read-only. It returns Bitstream (static FPGA region)
15 and other information of this static FPGA region.
17 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_metadata
21 Description: Read-only. It returns Bitstream (static FPGA region) meta
23 information of this static FPGA region.
25 What: /sys/bus/platform/devices/dfl-fme.0/cache_size
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| /linux-6.14.4/Documentation/devicetree/bindings/firmware/ |
| D | intel,stratix10-svc.txt | 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
7 configuration data from that location and perform the FPGA configuration.
17 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
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| /linux-6.14.4/Documentation/devicetree/bindings/gpio/ |
| D | gpio-ts4900.txt | 1 * Technologic Systems I2C-FPGA's GPIO controller bindings
3 This bindings describes the GPIO controller for Technologic's FPGA core.
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
12 of memory mapped region.
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
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| /linux-6.14.4/Documentation/devicetree/bindings/input/touchscreen/ |
| D | ts4800-ts.txt | 1 * TS-4800 Touchscreen bindings
4 - compatible: must be "technologic,ts4800-ts"
5 - reg: physical base address of the controller and length of memory mapped
6 region.
7 - syscon: phandle / integers array that points to the syscon node which
8 describes the FPGA's syscon registers.
9 - phandle to FPGA's syscon
10 - offset to the touchscreen register
11 - offset to the touchscreen enable bit
|