| /aosp_15_r20/external/mesa3d/src/intel/ci/ |
| H A D | gitlab-ci-inc.yml | 1 .intel-common-rules:
2 stage: intel
4 - changes: &intel_common_file_list
5 - src/intel/*
6 - src/intel/blorp/**/*
7 - src/intel/common/**/*
8 - src/intel/compiler/**/*
9 - src/intel/dev/**/*
10 - src/intel/ds/**/*
11 - src/intel/genxml/**/*
[all …]
|
| H A D | gitlab-ci.yml | 2 - local: 'src/intel/ci/gitlab-ci-inc.yml'
4 anv-jsl:
6 - .lava-acer-cb317-1h-c3z6-dedede:x86_64
7 - .anv-test
9 DEQP_SUITE: anv-jsl
10 VK_DRIVER: intel
14 # We don't enable a full run of anv-jsl nightly because it's about 8 hours of
16 .anv-jsl-full:
18 - anv-jsl
19 - .anv-manual-rules
[all …]
|
| /aosp_15_r20/external/angle/src/tests/ |
| H A D | angle_end2end_tests_expectations.txt | 2 // Use of this source code is governed by a BSD-style license that can be
20 42264678 VULKAN WIN INTEL : GLSLTest_ES31.StructAndArrayEqualOperator/* = SKIP
41 // Advanced blend ops currently fail on Windows/Intel.
42 376899587 WIN INTEL VULKAN : AdvancedBlendTest.*/* = SKIP
58 // Would need a pass to name in-out structs based on the contents and dedupe the structs.
103 42264632 WIN OPENGL INTEL : BlitFramebufferTest.OOBWrite/* = SKIP
105 42264699 WIN INTEL OPENGL : GLSLTest_ES31.BoolInInterfaceBlocks/* = SKIP
106 42264739 WIN INTEL OPENGL : GLSLTest_ES31.StorageBufferBoolVectorPassedToFunctions/* = SKIP
107 42265617 WIN INTEL OPENGL : GLSLTest.AliasingFunctionOutParamAndGlobal/* = SKIP
108 42266821 WIN INTEL OPENGL : TextureCubeTestES3.IncompatibleLayerABThenCompatibleLayerAB/* = SKIP
[all …]
|
| /aosp_15_r20/prebuilts/rust/linux-musl-x86/1.80.1/lib/rustlib/src/rust/library/stdarch/crates/core_arch/src/x86/ |
| H A D | sse2.rs | 3 #[cfg(test)]
12 /// Provides a hint to the processor that the code sequence is a spin-wait loop.
14 /// This can help improve the performance and power consumption of spin-wait
17 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))]
23 // the SSE2 target-feature - therefore it does not require any target features in _mm_pause()
30 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
33 #[cfg_attr(test, assert_instr(clflush))]
39 /// Performs a serializing operation on all load-from-memory instructions
46 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512f.rs | 8 // x86-32 wants to use a 32-bit address size, but asm! defaults to using the full
10 // use the 32-bit register name in that case.
39 #[cfg(test)]
42 /// Computes the absolute values of packed 32-bit integers in `a`.
44 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
48 #[cfg_attr(test, assert_instr(vpabsd))]
49 pub unsafe fn _mm512_abs_epi32(a: __m512i) -> __m512i { in _mm512_abs_epi32()
51 // all-0 is a properly initialized i32x16 in _mm512_abs_epi32()
58 /// Computes the absolute value of packed 32-bit integers in `a`, and store the
62 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx2.rs | 3 //! AVX2 expands most AVX commands to 256-bit wide vector registers and
4 //! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
8 //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
9 //! Instruction Set Reference, A-Z][intel64_ref].
10 //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
16 …http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software…
19 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
24 #[cfg(test)]
27 /// Computes the absolute values of packed 32-bit integers in `a`.
29 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512bw.rs | 8 #[cfg(test)]
13 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
15 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(test, assert_instr(vpabsw))]
20 pub unsafe fn _mm512_abs_epi16(a: __m512i) -> __m512i { in _mm512_abs_epi16()
22 // all-0 is a properly initialized i16x32 in _mm512_abs_epi16()
29 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
31 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
35 #[cfg_attr(test, assert_instr(vpabsw))]
36 pub unsafe fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { in _mm512_mask_abs_epi16()
[all …]
|
| /aosp_15_r20/prebuilts/rust/linux-x86/1.81.0.u1/lib/rustlib/src/rust/library/stdarch/crates/core_arch/src/x86/ |
| H A D | sse2.rs | 3 #[cfg(test)]
12 /// Provides a hint to the processor that the code sequence is a spin-wait loop.
14 /// This can help improve the performance and power consumption of spin-wait
17 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))]
23 // the SSE2 target-feature - therefore it does not require any target features in _mm_pause()
30 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
33 #[cfg_attr(test, assert_instr(clflush))]
39 /// Performs a serializing operation on all load-from-memory instructions
46 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512f.rs | 8 // x86-32 wants to use a 32-bit address size, but asm! defaults to using the full
10 // use the 32-bit register name in that case.
39 #[cfg(test)]
42 /// Computes the absolute values of packed 32-bit integers in `a`.
44 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
48 #[cfg_attr(test, assert_instr(vpabsd))]
49 pub unsafe fn _mm512_abs_epi32(a: __m512i) -> __m512i { in _mm512_abs_epi32()
51 // all-0 is a properly initialized i32x16 in _mm512_abs_epi32()
58 /// Computes the absolute value of packed 32-bit integers in `a`, and store the
62 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx2.rs | 3 //! AVX2 expands most AVX commands to 256-bit wide vector registers and
4 //! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
8 //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
9 //! Instruction Set Reference, A-Z][intel64_ref].
10 //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
16 …http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software…
19 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
24 #[cfg(test)]
27 /// Computes the absolute values of packed 32-bit integers in `a`.
29 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512bw.rs | 8 #[cfg(test)]
13 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
15 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(test, assert_instr(vpabsw))]
20 pub unsafe fn _mm512_abs_epi16(a: __m512i) -> __m512i { in _mm512_abs_epi16()
22 // all-0 is a properly initialized i16x32 in _mm512_abs_epi16()
29 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
31 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
35 #[cfg_attr(test, assert_instr(vpabsw))]
36 pub unsafe fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { in _mm512_mask_abs_epi16()
[all …]
|
| /aosp_15_r20/prebuilts/rust/linux-x86/1.81.0/lib/rustlib/src/rust/library/stdarch/crates/core_arch/src/x86/ |
| H A D | sse2.rs | 3 #[cfg(test)]
12 /// Provides a hint to the processor that the code sequence is a spin-wait loop.
14 /// This can help improve the performance and power consumption of spin-wait
17 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))]
23 // the SSE2 target-feature - therefore it does not require any target features in _mm_pause()
30 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
33 #[cfg_attr(test, assert_instr(clflush))]
39 /// Performs a serializing operation on all load-from-memory instructions
46 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512f.rs | 8 // x86-32 wants to use a 32-bit address size, but asm! defaults to using the full
10 // use the 32-bit register name in that case.
39 #[cfg(test)]
42 /// Computes the absolute values of packed 32-bit integers in `a`.
44 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
48 #[cfg_attr(test, assert_instr(vpabsd))]
49 pub unsafe fn _mm512_abs_epi32(a: __m512i) -> __m512i { in _mm512_abs_epi32()
51 // all-0 is a properly initialized i32x16 in _mm512_abs_epi32()
58 /// Computes the absolute value of packed 32-bit integers in `a`, and store the
62 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx2.rs | 3 //! AVX2 expands most AVX commands to 256-bit wide vector registers and
4 //! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
8 //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
9 //! Instruction Set Reference, A-Z][intel64_ref].
10 //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
16 …http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software…
19 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
24 #[cfg(test)]
27 /// Computes the absolute values of packed 32-bit integers in `a`.
29 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512bw.rs | 8 #[cfg(test)]
13 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
15 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(test, assert_instr(vpabsw))]
20 pub unsafe fn _mm512_abs_epi16(a: __m512i) -> __m512i { in _mm512_abs_epi16()
22 // all-0 is a properly initialized i16x32 in _mm512_abs_epi16()
29 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
31 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
35 #[cfg_attr(test, assert_instr(vpabsw))]
36 pub unsafe fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { in _mm512_mask_abs_epi16()
[all …]
|
| /aosp_15_r20/prebuilts/rust/linux-x86/1.80.1/lib/rustlib/src/rust/library/stdarch/crates/core_arch/src/x86/ |
| H A D | sse2.rs | 3 #[cfg(test)]
12 /// Provides a hint to the processor that the code sequence is a spin-wait loop.
14 /// This can help improve the performance and power consumption of spin-wait
17 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))]
23 // the SSE2 target-feature - therefore it does not require any target features in _mm_pause()
30 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
33 #[cfg_attr(test, assert_instr(clflush))]
39 /// Performs a serializing operation on all load-from-memory instructions
46 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512f.rs | 8 // x86-32 wants to use a 32-bit address size, but asm! defaults to using the full
10 // use the 32-bit register name in that case.
39 #[cfg(test)]
42 /// Computes the absolute values of packed 32-bit integers in `a`.
44 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
48 #[cfg_attr(test, assert_instr(vpabsd))]
49 pub unsafe fn _mm512_abs_epi32(a: __m512i) -> __m512i { in _mm512_abs_epi32()
51 // all-0 is a properly initialized i32x16 in _mm512_abs_epi32()
58 /// Computes the absolute value of packed 32-bit integers in `a`, and store the
62 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx2.rs | 3 //! AVX2 expands most AVX commands to 256-bit wide vector registers and
4 //! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
8 //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
9 //! Instruction Set Reference, A-Z][intel64_ref].
10 //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
16 …http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software…
19 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
24 #[cfg(test)]
27 /// Computes the absolute values of packed 32-bit integers in `a`.
29 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512bw.rs | 8 #[cfg(test)]
13 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
15 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(test, assert_instr(vpabsw))]
20 pub unsafe fn _mm512_abs_epi16(a: __m512i) -> __m512i { in _mm512_abs_epi16()
22 // all-0 is a properly initialized i16x32 in _mm512_abs_epi16()
29 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
31 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
35 #[cfg_attr(test, assert_instr(vpabsw))]
36 pub unsafe fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { in _mm512_mask_abs_epi16()
[all …]
|
| /aosp_15_r20/prebuilts/rust/linux-musl-x86/1.81.0/lib/rustlib/src/rust/library/stdarch/crates/core_arch/src/x86/ |
| H A D | sse2.rs | 3 #[cfg(test)]
12 /// Provides a hint to the processor that the code sequence is a spin-wait loop.
14 /// This can help improve the performance and power consumption of spin-wait
17 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))]
23 // the SSE2 target-feature - therefore it does not require any target features in _mm_pause()
30 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
33 #[cfg_attr(test, assert_instr(clflush))]
39 /// Performs a serializing operation on all load-from-memory instructions
46 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512f.rs | 8 // x86-32 wants to use a 32-bit address size, but asm! defaults to using the full
10 // use the 32-bit register name in that case.
39 #[cfg(test)]
42 /// Computes the absolute values of packed 32-bit integers in `a`.
44 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
48 #[cfg_attr(test, assert_instr(vpabsd))]
49 pub unsafe fn _mm512_abs_epi32(a: __m512i) -> __m512i { in _mm512_abs_epi32()
51 // all-0 is a properly initialized i32x16 in _mm512_abs_epi32()
58 /// Computes the absolute value of packed 32-bit integers in `a`, and store the
62 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx2.rs | 3 //! AVX2 expands most AVX commands to 256-bit wide vector registers and
4 //! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
8 //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
9 //! Instruction Set Reference, A-Z][intel64_ref].
10 //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
16 …http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software…
19 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
24 #[cfg(test)]
27 /// Computes the absolute values of packed 32-bit integers in `a`.
29 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
[all …]
|
| H A D | avx512bw.rs | 8 #[cfg(test)]
13 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
15 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
19 #[cfg_attr(test, assert_instr(vpabsw))]
20 pub unsafe fn _mm512_abs_epi16(a: __m512i) -> __m512i { in _mm512_abs_epi16()
22 // all-0 is a properly initialized i16x32 in _mm512_abs_epi16()
29 /// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned result…
31 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.htm…
35 #[cfg_attr(test, assert_instr(vpabsw))]
36 pub unsafe fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { in _mm512_mask_abs_epi16()
[all …]
|
| /aosp_15_r20/external/cronet/testing/unexpected_passes_common/ |
| H A D | expectations_unittest.py | 3 # Use of this source code is governed by a BSD-style license that can be
28 crbug.com/1234 [ win ] foo/test [ Failure ]
29 crbug.com/5678 crbug.com/6789 [ win ] foo/another/test [ RetryOnFailure ]
31 [ linux ] foo/test [ Failure ]
34 crbug.com/3456 [ linux ] some/bad/test [ Skip ]
35 crbug.com/4567 [ linux ] some/good/test [ Pass ]
42 crbug.com/4567 [ mac ] foo/test [ Failure ]
48 crbug.com/1234 [ wine ] foo/test [ Failure ]
50 [ linux ] foo/test [ Failure ]
53 crbug.com/3456 [ linux ] some/bad/test [ Skip ]
[all …]
|
| /aosp_15_r20/external/AFLplusplus/benchmark/ |
| H A D | benchmark-results.jsonl | 1 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
2 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
3 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
4 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
5 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
6 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
7 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
8 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
9 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
10 …-9900k, 16GB DDR4-3000, Arch Linux", "compiler": "clang version 16.0.6", "target_arch": "x86_64-pc…
[all …]
|