Searched full:interrupt (Results 1 – 25 of 6366) sorted by relevance
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| /linux-6.14.4/arch/arm64/boot/dts/exynos/ |
| D | exynos9810-pinctrl.dtsi | 16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 interrupt-parent = <&gic>;
34 #interrupt-cells = <2>;
41 interrupt-controller;
42 interrupt-parent = <&gic>;
51 #interrupt-cells = <2>;
58 interrupt-controller;
59 interrupt-parent = <&gic>;
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| /linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | renesas,rzv2h-icu.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
7 title: Renesas RZ/V2H(P) Interrupt Control Unit
14 - $ref: /schemas/interrupt-controller.yaml#
17 The Interrupt Control Unit (ICU) handles external interrupts (NMI, IRQ, and
25 '#interrupt-cells':
27 PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to
34 interrupt-controller: true
42 - description: NMI interrupt
43 - description: PORT_IRQ0 interrupt
44 - description: PORT_IRQ1 interrupt
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| D | renesas,rzg2l-irqc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
14 IA55 performs various interrupt controls including synchronization for the external
16 interrupts output by each IP. And it notifies the interrupt to the GIC
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
35 '#interrupt-cells':
37 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
44 interrupt-controller: true
52 - description: NMI interrupt
53 - description: IRQ0 interrupt
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| D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
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| D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
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| D | samsung,exynos4210-combiner.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
20 combined interrupt for its eight interrupt sources. The combined interrupt is
21 usually connected to a parent interrupt controller.
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| D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
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| D | brcm,bcm7120-l2-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
22 directly output an interrupt signal towards the interrupt controller parent,
23 or if they will output an interrupt signal at this 2nd level interrupt
30 - not all bits within the interrupt controller actually map to an interrupt
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
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| D | riscv,aplic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
19 interrupt sources connect to the root APLIC domain and a parent APLIC
20 domain can delegate interrupt sources to it's child APLIC domains. There
24 - $ref: /schemas/interrupt-controller.yaml#
36 interrupt-controller: true
38 "#interrupt-cells":
52 message signaled interrupt controller (IMSIC). If both "msi-parent" and
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| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
18 The interrupt sources map to the corresponding bits in the interrupt
27 /* dw_apb_ictl is used as secondary interrupt controller */
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| D | fsl,ls-extirq.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
7 title: Freescale Layerscape External Interrupt Controller
14 LX216xA) support inverting the polarity of certain external interrupt
34 '#interrupt-cells':
40 interrupt-controller: true
45 Specifies the Interrupt Polarity Control Register (INTPCR) in the
46 SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
48 interrupt-map:
51 interrupt-map-mask: true
55 - '#interrupt-cells'
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| /linux-6.14.4/drivers/net/ipa/ |
| D | ipa_interrupt.c | 9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
22 #include <linux/interrupt.h>
36 * struct ipa_interrupt - IPA interrupt information
40 * @suspend_enabled: Bitmap of endpoints with the SUSPEND interrupt enabled
49 /* Clear the suspend interrupt for all endpoints that signaled it */
50 static void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) in ipa_interrupt_suspend_clear_all() argument
52 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_suspend_clear_all()
64 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ in ipa_interrupt_suspend_clear_all()
73 /* Process a particular interrupt type that has been received */
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| D | ipa_interrupt.h | 20 * @interrupt: IPA interrupt structure
21 * @endpoint_id: Endpoint whose interrupt should be enabled
24 * A TX_SUSPEND interrupt arrives on an AP RX enpoint when packet data can't
28 void ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt,
33 * @interrupt: IPA interrupt structure
34 * @endpoint_id: Endpoint whose interrupt should be disabled
36 void ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt,
40 * ipa_interrupt_simulate_suspend() - Simulate TX_SUSPEND IPA interrupt
41 * @interrupt: IPA interrupt structure
43 * This calls the TX_SUSPEND interrupt handler, as if such an interrupt
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| /linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
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| /linux-6.14.4/Documentation/devicetree/bindings/net/wireless/ |
| D | qcom,ath11k.yaml | 32 interrupt-names:
104 - description: misc-pulse1 interrupt events
105 - description: misc-latch interrupt events
106 - description: sw exception interrupt events
107 - description: watchdog interrupt events
108 - description: interrupt event for ring CE0
109 - description: interrupt event for ring CE1
110 - description: interrupt event for ring CE2
111 - description: interrupt event for ring CE3
112 - description: interrupt event for ring CE4
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| /linux-6.14.4/drivers/gpu/drm/amd/include/ivsrcid/dcn/ |
| D | irqsrcs_dcn_1_0.h | 78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
96 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT…
102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU…
105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY…
108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY…
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| /linux-6.14.4/arch/powerpc/boot/dts/ |
| D | fsp2.dts | 64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
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| /linux-6.14.4/arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
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| D | bcm7360.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
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| D | bcm7346.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
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| D | bcm7362.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
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| /linux-6.14.4/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
25 interrupt-parent = <&pic>;
33 interrupt-parent = <&pic>;
43 interrupt-parent = <&pic>;
53 interrupt-parent = <&pic>;
63 interrupt-parent = <&pic>;
89 interrupt-parent = <&pic>;
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| /linux-6.14.4/arch/loongarch/boot/dts/ |
| D | loongson-2k2000.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
41 cpuintc: interrupt-controller {
42 compatible = "loongson,cpu-interrupt-controller";
43 #interrupt-cells = <1>;
44 interrupt-controller;
96 interrupt-parent = <&eiointc>;
119 interrupt-parent = <&liointc>;
124 liointc: interrupt-controller@1fe01400 {
128 interrupt-controller;
129 #interrupt-cells = <2>;
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| /linux-6.14.4/arch/arm/boot/dts/samsung/ |
| D | exynos5410-pinctrl.dtsi | 16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
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| /linux-6.14.4/drivers/irqchip/ |
| D | Kconfig | 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
94 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
134 tristate "Broadcom STB generic L2 interrupt controller driver"
176 Enable support for the LAN966x Outbound Interrupt Controller.
178 maps the internal interrupts sources to PCIe interrupt.
236 Enable support for the Renesas Interrupt Controller for external
237 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
244 Enable support for the Renesas Interrupt Controller for external
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