| /linux-6.14.4/tools/testing/selftests/drivers/net/mlxsw/ |
| D | ethtool_lanes.sh | 28 busywait $TIMEOUT sh -c "ethtool $swp1 | grep -q Lanes:"
30 log_test "SKIP: driver does not support lanes setting"
41 local lanes=$1; shift
45 chosen_lanes=$(ethtool $dev | grep 'Lanes:')
46 chosen_lanes=${chosen_lanes#*"Lanes: "}
48 ((chosen_lanes == lanes))
49 check_err $? "swp1 advertise $max_speed and $lanes, devs sync to $chosen_lanes"
66 ethtool -s $swp1 speed $max_speed lanes $unsupported_lanes $autoneg_str &> /dev/null
67 check_fail $? "Unsuccessful $unsupported_lanes lanes setting was expected"
94 local lanes=$1; shift
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/media/ |
| D | qcom,sm8250-camss.yaml | 124 clock-lanes:
127 data-lanes:
132 - clock-lanes
133 - data-lanes
147 clock-lanes:
150 data-lanes:
155 - clock-lanes
156 - data-lanes
170 clock-lanes:
173 data-lanes:
[all …]
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| D | qcom,sc8280xp-camss.yaml | 139 clock-lanes:
142 data-lanes:
147 - clock-lanes
148 - data-lanes
162 clock-lanes:
165 data-lanes:
170 - clock-lanes
171 - data-lanes
185 clock-lanes:
188 data-lanes:
[all …]
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| D | brcm,bcm2835-unicam.yaml | 55 brcm,num-data-lanes:
59 Number of CSI-2 data lanes supported by this Unicam instance. The number
60 of data lanes actively used is specified with the data-lanes endpoint
77 data-lanes: true
82 - data-lanes
96 - brcm,num-data-lanes
118 brcm,num-data-lanes = <2>;
123 data-lanes = <1 2>;
|
| D | ti,cal.yaml | 86 clock-lanes:
89 data-lanes:
104 clock-lanes:
107 data-lanes:
146 clock-lanes = <0>;
147 data-lanes = <1 2>;
170 clock-lanes = <0>;
171 data-lanes = <1 2>;
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| D | video-interfaces.yaml | 159 data-lanes:
170 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
176 clock-lanes:
183 a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which places the
206 An array of polarities of the lanes starting from the clock lane and
207 followed by the data lanes in the same order as in data-lanes. Valid
209 the combined length of data-lanes and clock-lanes properties. If the
226 An array of line orders of the CSI-2 C-PHY data lanes. The order of the
227 lanes are the same as in data-lanes property. Valid values are 0-5 as
230 data-lanes property. If the line-orders property is omitted, the value
|
| /linux-6.14.4/tools/testing/selftests/drivers/net/hw/ |
| D | devlink_port_split.py | 12 # Test port split configuration using devlink-port lanes attribute.
77 Get the $port's maximum number of lanes.
78 Return: number of lanes, e.g. 1, 2, 4 and 8.
86 if 'lanes' in values:
87 lanes = values['lanes']
89 lanes = 0
90 return lanes
150 def exists_and_lanes(ports, lanes, dev): argument
153 $lanes number of lanes after splitting.
162 if max_lanes != lanes:
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/renesas/ |
| D | r8a779a0-falcon-csi-dsi.dtsi | 21 clock-lanes = <0>;
22 data-lanes = <1 2 3 4>;
40 clock-lanes = <0>;
41 data-lanes = <1 2 3 4>;
59 clock-lanes = <0>;
60 data-lanes = <1 2 3 4>;
111 clock-lanes = <0>;
112 data-lanes = <1 2 3 4>;
132 clock-lanes = <0>;
133 data-lanes = <1 2 3 4>;
[all …]
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| D | hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 18 clock-lanes = <0>;
19 data-lanes = <1 2>;
32 clock-lanes = <0>;
33 data-lanes = <1 2>;
49 clock-lanes = <0>;
50 data-lanes = <1 2>;
63 clock-lanes = <0>;
64 data-lanes = <1 2>;
|
| D | white-hawk-csi-dsi.dtsi | 22 clock-lanes = <0>;
23 data-lanes = <1 2 3>;
43 clock-lanes = <0>;
44 data-lanes = <1 2 3>;
89 clock-lanes = <0>;
90 data-lanes = <1 2 3>;
110 clock-lanes = <0>;
111 data-lanes = <1 2 3>;
|
| D | r8a774c0-ek874-mipi-2.1.dts | 38 clock-lanes = <0>;
39 data-lanes = <1 2>;
52 clock-lanes = <0>;
53 data-lanes = <1 2>;
62 clock-lanes = <0>;
63 data-lanes = <1 2>;
|
| /linux-6.14.4/drivers/gpu/drm/hisilicon/hibmc/dp/ |
| D | dp_link.c | 19 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
21 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
28 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
31 drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
110 for (i = 0; i < dp->link.cap.lanes; i++) in hibmc_dp_link_training_cr_pre()
113 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
114 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_cr_pre()
128 for (lane = 0; lane < dp->link.cap.lanes; lane++) in hibmc_dp_link_get_adjust_train()
159 switch (dp->link.cap.lanes) { in hibmc_dp_link_reduce_lane()
161 dp->link.cap.lanes--; in hibmc_dp_link_reduce_lane()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/media/i2c/ |
| D | adv748x.yaml | 83 clock-lanes:
86 data-lanes:
91 - clock-lanes
92 - data-lanes
106 clock-lanes:
109 data-lanes:
113 - clock-lanes
114 - data-lanes
195 clock-lanes = <0>;
196 data-lanes = <1 2 3 4>;
[all …]
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| /linux-6.14.4/drivers/media/platform/ti/omap3isp/ |
| D | ispcsiphy.c | 167 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
179 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
182 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
189 /* Clock and data lanes verification */ in omap3isp_csiphy_config()
191 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
194 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
197 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
200 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
203 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) in omap3isp_csiphy_config()
215 /* CSI-2 is DDR and we only count used lanes. */ in omap3isp_csiphy_config()
[all …]
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| /linux-6.14.4/drivers/gpu/drm/tegra/ |
| D | dp.c | 51 link->lanes = 0; in drm_dp_link_reset()
233 link->lanes = link->max_lanes; in drm_dp_link_probe()
346 values[1] = link->lanes; in drm_dp_link_configure()
381 * with the lowest number of lanes and the lowest possible link rate that can
393 /* available number of lanes */ in drm_dp_link_choose()
394 static const unsigned int lanes[3] = { 1, 2, 4 }; in drm_dp_link_choose() local
402 for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) { in drm_dp_link_choose()
405 * Capacity for this combination of lanes and rate, in drm_dp_link_choose()
412 capacity = lanes[i] * (rates[j] * 10) * 8 / 10; in drm_dp_link_choose()
415 DRM_DEBUG_KMS("using %u lanes at %u kHz (%lu/%lu kbps)\n", in drm_dp_link_choose()
[all …]
|
| /linux-6.14.4/net/ethtool/ |
| D | linkmodes.c | 49 data->ksettings.lanes = 0; in linkmodes_prepare_data()
133 if (ksettings->lanes && in linkmodes_fill_reply()
134 nla_put_u32(skb, ETHTOOL_A_LINKMODES_LANES, ksettings->lanes)) in linkmodes_fill_reply()
168 * lanes and duplex values. Called when autonegotiation is on, speed, lanes or
190 (!req_lanes || info->lanes == ksettings->lanes) && in ethnl_auto_linkmodes()
229 "lanes value is invalid"); in ethnl_check_linkmodes()
264 /* If autoneg is off and lanes parameter is not supported by the in ethnl_update_linkmodes()
270 "lanes configuration not supported by device"); in ethnl_update_linkmodes()
273 } else if (!lsettings->autoneg && ksettings->lanes) { in ethnl_update_linkmodes()
274 /* If autoneg is off and lanes parameter is not passed from user but in ethnl_update_linkmodes()
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|
| /linux-6.14.4/Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 104 - If lanes 0 to 3 are used:
107 - If lanes 4 or 5 are used:
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
210 nvidia,num-lanes = <2>;
224 nvidia,num-lanes = <2>;
316 nvidia,num-lanes = <2>;
[all …]
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| /linux-6.14.4/Documentation/driver-api/media/drivers/ |
| D | ipu6.rst | 154 Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake,
155 there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
157 Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
158 maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
159 lanes so IPU6 support maximum 6 CSI-2 ports.
162 lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
163 maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
164 port 0 with 2 data lanes can work together with CSI-2 port 1 with 2
165 data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1
166 will not be available as the 4 data lanes are shared by CSI-2 port 0
|
| /linux-6.14.4/include/linux/phy/ |
| D | phy-dp.h | 31 * @lanes:
33 * Number of active, consecutive, data lanes, starting from
38 unsigned int lanes; member
44 * to be used by particular lanes. One value per lane.
55 * used by particular lanes. One value per lane.
91 * and pre-emphasis to requested values. Only lanes specified
92 * by "lanes" parameter will be affected.
|
| /linux-6.14.4/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 88 xlnx,en-active-lanes:
91 Present if the number of active lanes can be re-configured at
92 runtime in the Protocol Configuration Register. Otherwise all lanes,
115 data-lanes:
121 1 2 - For 2 lanes enabled in IP.
122 1 2 3 - For 3 lanes enabled in IP.
123 1 2 3 4 - For 4 lanes enabled in IP.
131 - data-lanes
180 xlnx,en-active-lanes;
195 data-lanes = <1 2 3 4>;
|
| /linux-6.14.4/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_common.c | 18 prop = of_find_property(ep, "lanes", &len); in hdmi_parse_lanes_of()
20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
23 dev_err(&pdev->dev, "bad number of lanes\n"); in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
|
| /linux-6.14.4/drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi_common.c | 18 prop = of_find_property(ep, "lanes", &len); in hdmi_parse_lanes_of()
20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
23 dev_err(&pdev->dev, "bad number of lanes\n"); in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
|
| /linux-6.14.4/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-sk-csi2-dual-imx219.dtso | 43 clock-lanes = <0>;
44 data-lanes = <1 2>;
65 clock-lanes = <0>;
66 data-lanes = <1 2>;
85 clock-lanes = <0>;
86 data-lanes = <1 2>;
132 clock-lanes = <0>;
133 data-lanes = <1 2>;
|
| /linux-6.14.4/drivers/phy/rockchip/ |
| D | phy-rockchip-snps-pcie3.c | 68 u32 lanes[4]; member
107 dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); in rockchip_p3phy_rk3568_init()
108 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3568_init()
165 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3588_init()
167 if (priv->lanes[i] == 3) in rockchip_p3phy_rk3588_init()
169 if (priv->lanes[i] == 4) in rockchip_p3phy_rk3588_init()
284 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", in rockchip_p3phy_probe()
285 priv->lanes, 2, in rockchip_p3phy_probe()
286 ARRAY_SIZE(priv->lanes)); in rockchip_p3phy_probe()
288 /* if no data-lanes assume aggregation */ in rockchip_p3phy_probe()
[all …]
|
| /linux-6.14.4/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra124-xusb-padctl.yaml | 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
25 ports (e.g. PCIe) and the lanes.
88 order to use the pad and any of its lanes, this property must be set
105 lanes:
149 lanes:
177 lanes:
[all …]
|