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/aosp_15_r20/external/coreboot/src/southbridge/intel/bd82x6x/
H A Dme.c183 u8 me_state = get_uint_option("me_state", 0); in intel_me_init() local
186 printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev); in intel_me_init()
213 if (me_state == CMOS_ME_STATE_DISABLED in intel_me_init()
236 && me_state == CMOS_ME_STATE_NORMAL in intel_me_init()
265 if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { in intel_me_init()
266 u8 new_state = me_state | CMOS_ME_STATE_CHANGED; in intel_me_init()
H A Dme_8.x.c182 u8 me_state = get_uint_option("me_state", 0); in intel_me_init() local
185 printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev); in intel_me_init()
213 if (me_state == CMOS_ME_STATE_DISABLED in intel_me_init()
236 && me_state == CMOS_ME_STATE_NORMAL in intel_me_init()
265 if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { in intel_me_init()
266 u8 new_state = me_state | CMOS_ME_STATE_CHANGED; in intel_me_init()
/aosp_15_r20/external/coreboot/src/soc/intel/common/block/cse/
H A Dcse.c1221 * of `me_state`. A value of `0` will result in a (CS)ME state of `0` (working)
1234 * 432 1 e 5 me_state
1319 * Check if the CMOS value "me_state" exists, if it doesn't, then in cse_set_state()
1322 const unsigned int cmos_me_state = get_uint_option("me_state", UINT_MAX); in cse_set_state()
1327 printk(BIOS_DEBUG, "CMOS: me_state = %u\n", cmos_me_state); in cse_set_state()
1330 * We only take action if the me_state doesn't match the CS(ME) working state in cse_set_state()
1336 /* me_state should be disabled, but it's enabled */ in cse_set_state()
1342 /* me_state should be enabled, but it's disabled */ in cse_set_state()
/aosp_15_r20/external/coreboot/Documentation/releases/
H A Dcoreboot-4.16-relnotes.md132 set based on a CMOS value of `me_state`. A value of `0` will result in a
146 the new CMOS option me_state, with values of 0 and 1. The method is very
/aosp_15_r20/external/coreboot/src/mainboard/protectli/vault_cml/
H A Dcmos.default5 me_state=Enable
/aosp_15_r20/external/coreboot/src/mainboard/system76/oryp6/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/addw1/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/tgl-u/
H A Dcmos.default5 me_state=Enable
/aosp_15_r20/external/coreboot/src/mainboard/system76/adl/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/rpl/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/whl-u/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/oryp5/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/bonw14/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/cml-u/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/gaze15/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/system76/tgl-h/
H A Dcmos.default5 me_state=Disable
/aosp_15_r20/external/coreboot/src/mainboard/dell/snb_ivb_latitude/
H A Dcmos.default9 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/x220/
H A Dcmos.default18 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/t420s/
H A Dcmos.default19 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/l520/
H A Dcmos.default19 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/t420/
H A Dcmos.default19 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/t520/
H A Dcmos.default20 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/t530/
H A Dcmos.default20 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/t430/
H A Dcmos.default20 me_state=Normal
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/t430s/
H A Dcmos.default21 me_state=Normal

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