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Searched +full:phy +full:- +full:dll +full:- +full:delay +full:- +full:strobe (Results 1 – 13 of 13) sorted by relevance

/linux-6.14.4/drivers/mmc/host/
Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY support for Xenon SDHC
8 * Date: 2016-8-24
12 #include <linux/delay.h>
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
20 /* Register base for eMMC PHY 5.0 Version */
22 /* Register base for eMMC PHY 5.1 Version */
116 * List offset of PHY registers and some special register values
117 * in eMMC PHY 5.0 or eMMC PHY 5.1
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Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
24 #include "sdhci-pltfm.h"
41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
113 /* PHY register area pointer */
116 /* PHY general configuration */
118 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
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Dsdhci-sprd.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
22 #include "sdhci-pltfm.h"
105 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
106 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
107 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
108 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
109 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
110 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
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Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
19 /* HRS - Host Register Set (specific to Cadence) */
20 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
39 /* SRS - Slot Register Set (SDHCI-compatible) */
42 /* PHY */
57 * The tuned val register is 6 bit-wide, but not the whole of the range is
58 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
90 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
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Dsdhci_am654.c1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
29 /* PHY Registers */
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
109 "ti,itap-del-sel-legacy",
111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
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Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <[email protected]>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
23 #include <linux/phy/phy.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
94 * On some SoCs the syscon area has a feature where the upper 16-bits of
95 * each 32-bit register act as a write mask for the lower 16-bits. This allows
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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <[email protected]>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - socionext,uniphier-sd4hc
20 - const: cdns,sd4hc
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Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <[email protected]>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <[email protected]>
11 - Baolin Wang <[email protected]>
12 - Chunyan Zhang <[email protected]>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
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/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip emmc PHY driver
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
10 #include <linux/delay.h>
15 #include <linux/phy/phy.h>
20 * The higher 16-bit of this register is used for write protection
93 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off) in rockchip_emmc_phy_power() argument
95 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); in rockchip_emmc_phy_power()
106 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
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/linux-6.14.4/drivers/gpu/drm/amd/include/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/linux-6.14.4/drivers/gpu/drm/radeon/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
695 // =0: PHY linkA if bfLane<3
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/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
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