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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <[email protected]>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - socionext,uniphier-sd4hc
20 - const: cdns,sd4hc
[all …]
Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <[email protected]>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Thierry Reding <[email protected]>
17 - items:
18 - enum:
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/linux-6.14.4/arch/arm64/boot/dts/amd/
Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
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/linux-6.14.4/drivers/mmc/host/
Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
19 /* HRS - Host Register Set (specific to Cadence) */
20 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
39 /* SRS - Slot Register Set (SDHCI-compatible) */
42 /* PHY */
57 * The tuned val register is 6 bit-wide, but not the whole of the range is
58 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
90 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
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Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <[email protected]>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
23 #include <linux/phy/phy.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
94 * On some SoCs the syscon area has a feature where the upper 16-bits of
95 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
Dsdhci_am654.c1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
29 /* PHY Registers */
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
109 "ti,itap-del-sel-legacy",
111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
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/linux-6.14.4/drivers/net/ethernet/intel/e1000e/
Dparam.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
15 #define OPTION_UNSET -1
36 /* Transmit Interrupt Delay in units of 1.024 microseconds
37 * Tx interrupt delay needs to typically be set to something non-zero
39 * Valid Range: 0-65535
41 E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
46 /* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
48 * Valid Range: 0-65535
50 E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
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Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
104 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
198 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
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/linux-6.14.4/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
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Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
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Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
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/linux-6.14.4/Documentation/networking/
Dphy.rst2 PHY Abstraction Layer
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
47 mii_id is the address on the bus for the PHY, and regnum is the register
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
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/linux-6.14.4/drivers/net/ethernet/intel/ixgbe/
Dixgbe_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
64 "Copyright (c) 1999-2016 Intel Corporation.";
80 /* ixgbe_pci_tbl - PCI Device ID Table
160 …"Maximum number of virtual functions to allocate per physical function - default is zero and maxim…
166 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
169 static int debug = -1;
190 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); in netif_is_ixgbe()
199 parent_bus = adapter->pdev->bus->parent; in ixgbe_read_pci_cfg_word_parent()
201 return -1; in ixgbe_read_pci_cfg_word_parent()
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/linux-6.14.4/drivers/net/wireless/ath/ath5k/
Dreg.h2 * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]>
3 * Copyright (c) 2004-2008 Reyk Floeter <[email protected]>
4 * Copyright (c) 2007-2008 Michael Taylor <[email protected]>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
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/linux-6.14.4/drivers/gpu/drm/amd/display/dmub/inc/
Ddmub_cmd.h32 #include <linux/delay.h>
123 * PSR control version legacy
133 * ABM control version legacy
143 * Physical framebuffer address location, 64-bit.
255 * @knee_threshold: Current x-position of ACE knee (u0.16).
275 * union dmub_addr - DMUB physical/virtual 64-bit address.
340 * Back to back flip, therefore cannot power down PHY
381 * @force_phy_power_on: Force phy power on
405 * @disable_delay_alpm_on: Force disable delay alpm on
457 * 0x1 (bit 0) - Desync Error flag.
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/linux-6.14.4/drivers/net/ethernet/intel/igb/
Digb_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
9 #include <linux/delay.h>
104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
130 "legacy-rx",
139 struct e1000_hw *hw = &adapter->hw; in igb_get_link_ksettings()
140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_get_link_ksettings()
141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; in igb_get_link_ksettings()
146 status = pm_runtime_suspended(&adapter->pdev->dev) ? in igb_get_link_ksettings()
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/linux-6.14.4/drivers/net/ethernet/intel/e1000/
De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
89 * e1000_set_phy_type - Set the phy type member in the hw struct.
94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
97 switch (hw->phy_id) { in e1000_set_phy_type()
103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
106 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
107 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
108 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
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De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
104 /* PHY status info structure and supporting enums */
280 /* PHY */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
529 /* Receive Descriptor - Packet Split */
553 __le16 length[3]; /* length of buffers 1-3 */
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/linux-6.14.4/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
13 #include "phy.h"
27 *((u32 *) (val)) = rtlpci->receive_config; in rtl92se_get_hw_reg()
31 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92se_get_hw_reg()
35 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92se_get_hw_reg()
51 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; in rtl92se_get_hw_reg()
81 if (rtlhal->version == VERSION_8192S_ACUT) in rtl92se_set_hw_reg()
120 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
129 reg_tmp = (mac->cur_40_prime_sc) << 5; in rtl92se_set_hw_reg()
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/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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/linux-6.14.4/drivers/gpu/drm/amd/include/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
496 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
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/linux-6.14.4/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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/linux-6.14.4/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dd11.h32 #define TX_AC_BE_FIFO 1 /* Best-Effort TX FIFO */
44 /* Legacy TX FIFO numbers */
60 /* 2byte-wide pio register set per channel(xmt or rcv) */
74 /* 4byte-wide pio register set per channel(xmt or rcv) */
86 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
87 * write: only low 16b-it half can be written
108 /* Device Control ("semi-standard host registers") */
109 u32 PAD[3]; /* 0x0 - 0x8 */
119 u32 PAD[40]; /* 0x60 - 0xFC */
121 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
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/linux-6.14.4/drivers/ata/
Dlibata-sff.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libata-sff.c - helper library for PCI IDE BMDMA
5 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2006 Jeff Garzik
9 * as Documentation/driver-api/libata.rst
12 * http://www.sata-io.org/
53 * ata_sff_check_status - Read device status reg & clear interrupt
56 * Reads ATA taskfile status register for currently-selected device
65 return ioread8(ap->ioaddr.status_addr); in ata_sff_check_status()
70 * ata_sff_altstatus - Read device alternate status reg
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