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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
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Dqcom,qca8k-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
10 - Bjorn Andersson <[email protected]>
11 - Luo Jie <[email protected]>
18 include/dt-bindings/clock/qcom,qca8k-nsscc.h
19 include/dt-bindings/reset/qcom,qca8k-nsscc.h
24 - const: qcom,qca8084-nsscc
[all …]
Dqcom,qdu1000-ecpricc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
10 - Taniya Das <[email protected]>
11 - Imran Shaik <[email protected]>
17 See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
22 - qcom,qdu1000-ecpricc
29 - description: Board XO source
[all …]
Dqcom,ipq5018-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <[email protected]>
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
26 - description: Board XO source
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Dqcom,ipq9574-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <[email protected]>
11 - Anusha Rao <[email protected]>
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
23 const: qcom,ipq9574-gcc
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Dqcom,sm4450-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM4450
10 - Ajit Pandey <[email protected]>
11 - Taniya Das <[email protected]>
17 See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
21 const: qcom,sm4450-dispcc
28 - description: Board XO source
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Dqcom,sdx75-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SDX75
10 - Imran Shaik <[email protected]>
11 - Taniya Das <[email protected]>
17 See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
21 const: qcom,sdx75-gcc
25 - description: Board XO source
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Dqcom,sm8650-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8650
10 - Bjorn Andersson <[email protected]>
16 See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
20 const: qcom,sm8650-gcc
24 - description: Board XO source
25 - description: Board Always On XO source
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Dqcom,sm8550-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8550
10 - Bjorn Andersson <[email protected]>
16 See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
20 const: qcom,sm8550-gcc
24 - description: Board XO source
25 - description: Sleep clock source
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Dqcom,qcs8300-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300
10 - Taniya Das <[email protected]>
11 - Imran Shaik <[email protected]>
17 See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h
21 const: qcom,qcs8300-gcc
25 - description: Board XO source
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Dqcom,sm8750-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8750
10 - Taniya Das <[email protected]>
16 See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
20 const: qcom,sm8750-gcc
24 - description: Board XO source
25 - description: Board Always On XO source
[all …]
Dqcom,sm8450-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
10 - Konrad Dybcio <[email protected]>
17 include/dt-bindings/clock/qcom,sar2130p-gpucc.h
18 include/dt-bindings/clock/qcom,sm4450-gpucc.h
19 include/dt-bindings/clock/qcom,sm8450-gpucc.h
20 include/dt-bindings/clock/qcom,sm8550-gpucc.h
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Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8350
10 - Vinod Koul <[email protected]>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
20 const: qcom,gcc-sm8350
24 - description: Board XO source
25 - description: Sleep clock source
[all …]
Dqcom,gcc-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8450
10 - Vinod Koul <[email protected]>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
21 - qcom,gcc-sm8450
22 - qcom,sm8475-gcc
26 - description: Board XO source
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/linux-6.14.4/drivers/reset/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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/linux-6.14.4/drivers/video/fbdev/via/
Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
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/linux-6.14.4/arch/arm/mach-omap1/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
30 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/linux-6.14.4/sound/soc/codecs/
Dcs35l56.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <sound/cs-amp-lib.h>
31 #include <sound/soc-dapm.h>
43 flush_work(&cs35l56->dsp_work); in cs35l56_wait_dsp_ready()
66 static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0);
162 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs35l56_play_event()
167 dev_dbg(cs35l56->base.dev, "play: %d\n", event); in cs35l56_play_event()
172 return regmap_write(cs35l56->base.regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, in cs35l56_play_event()
176 ret = regmap_read_poll_timeout(cs35l56->base.regmap, in cs35l56_play_event()
182 dev_err(cs35l56->base.dev, "PS0 wait failed: %d\n", ret); in cs35l56_play_event()
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/linux-6.14.4/Documentation/devicetree/bindings/power/reset/
Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <[email protected]>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
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/linux-6.14.4/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
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/linux-6.14.4/Documentation/devicetree/bindings/display/panel/
Dsamsung,ams639rq08.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung AMS639RQ08 EA8076-based 6.39" 1080x2340 MIPI-DSI Panel
10 - Danila Tikhonov <[email protected]>
11 - Jens Reidel <[email protected]>
14 The Samsung AMS639RQ08 is a 6.39 inch 1080x2340 MIPI-DSI CMD mode AMOLED panel.
17 - $ref: panel-common.yaml#
26 vdd3p3-supply:
27 description: 3.3V source voltage rail
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Dsamsung,ams581vf01.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung AMS581VF01 SOFEF01-based 5.81" 1080x2340 MIPI-DSI Panel
10 - Danila Tikhonov <[email protected]>
13 The Samsung AMS581VF01 is a 5.81 inch 1080x2340 MIPI-DSI CMD mode OLED panel.
16 - $ref: panel-common.yaml#
25 vdd3p3-supply:
26 description: 3.3V source voltage rail
28 vddio-supply:
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/linux-6.14.4/tools/testing/selftests/drivers/net/mlxsw/
Dpci_reset.sh2 # SPDX-License-Identifier: GPL-2.0
4 # Test that PCI reset works correctly by verifying that only the expected reset
5 # methods are supported and that after issuing the reset the ifindex of the
14 source $lib_dir/lib.sh
15 source $lib_dir/devlink_lib.sh
21 local bus=$(echo $DEVLINK_DEV | cut -d '/' -f 1)
22 local bdf=$(echo $DEVLINK_DEV | cut -d '/' -f 2)
26 log_test "pci reset"
30 if [ ! -f /sys/bus/pci/devices/$bdf/reset_method ]; then
31 check_err 1 "reset is not supported"
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/linux-6.14.4/Documentation/devicetree/bindings/input/
Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
[all …]
/linux-6.14.4/arch/sparc/include/asm/
Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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