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/aosp_15_r20/external/coreboot/src/ec/starlabs/merlin/variants/cezanne-desktop/
H A Demem.asl138 // Below are the Thunderbolt Offsets from the shared EC code. There aren't
142 // TBTC, 8, // Thunderbolt Command
143 // TBTP, 8, // Thunderbolt Data Port
144 // TBTD, 8, // Thunderbolt Data
145 // TBTA, 8, // Thunderbolt Acknowledge
146 // TBTG, 16, // Thunderbolt DBG Data
/aosp_15_r20/external/coreboot/src/ec/starlabs/merlin/variants/cezanne/
H A Demem.asl144 TBTC, 8, // Thunderbolt Command
145 TBTP, 8, // Thunderbolt Data Port
146 TBTD, 8, // Thunderbolt Data
147 TBTA, 8, // Thunderbolt Acknowledge
148 TBTG, 16, // Thunderbolt DBG Data
/aosp_15_r20/external/coreboot/src/soc/intel/common/block/usb4/
H A DKconfig9 of Intel Thunderbolt/USB4 ports.
16 USB4/Thunderbolt root ports.
23 Intel USB4/Thunderbolt North XHCI ports.
/aosp_15_r20/external/coreboot/util/coreboot-configurator/src/application/qrc/
H A Dcategories.yaml78 thunderbolt:
79 displayName: Thunderbolt
81 help: Enable or disable Thunderbolt functionality
/aosp_15_r20/external/coreboot/src/mainboard/starlabs/starbook/variants/tgl/
H A Dromstage.c33 /* Enable/Disable Thunderbolt based on CMOS settings */ in mainboard_memory_init_params()
34 if (get_uint_option("thunderbolt", 1) == 0) { in mainboard_memory_init_params()
H A Ddevtree.c59 /* Enable/Disable Thunderbolt based on CMOS settings */ in devtree_update()
60 if (get_uint_option("thunderbolt", 1) == 0) { in devtree_update()
H A Dcmos.default17 thunderbolt=Disable
/aosp_15_r20/external/coreboot/src/mainboard/starlabs/starbook/variants/rpl/
H A Dromstage.c37 /* Enable/Disable Thunderbolt based on CMOS settings */ in mainboard_memory_init_params()
38 if (get_uint_option("thunderbolt", 1) == 0) { in mainboard_memory_init_params()
H A Ddevtree.c61 /* Enable/Disable Thunderbolt based on CMOS settings */ in devtree_update()
62 if (get_uint_option("thunderbolt", 1) == 0) { in devtree_update()
H A Dgpio.c278 /* E18: Thunderbolt LSX TXD */
280 /* E19: Thunderbolt LSX RXD */
H A Dramstage.c9 if (get_uint_option("thunderbolt", 1) == 0) in mainboard_silicon_init_params()
/aosp_15_r20/external/coreboot/src/mainboard/lenovo/t430s/variants/t430s/
H A Doverridetree.cb21 # Enable hotplug on Port 5 for Thunderbolt controller
23 device ref pcie_rp5 on end # Thunderbolt controller
/aosp_15_r20/external/coreboot/src/mainboard/system76/rpl/variants/bonw15/
H A Doverridetree.cb18 [8] = USB2_PORT_MID(OC_SKIP), /* Type-C Thunderbolt (Right, Front) */
19 [9] = USB2_PORT_MID(OC_SKIP), /* Type-C Thunderbolt with PD (Right, Rear) */
/aosp_15_r20/external/pciutils/
H A Dpci.ids417 002f MegaRAID SAS 2208 IOV [Thunderbolt]
475 005b MegaRAID SAS 2208 [Thunderbolt]
715 15d9 0690 Onboard MegaRAID SAS2208 [Thunderbolt]
5132 14cd Family 19h USB4/Thunderbolt PCIe tunnel
5134 14ef Family 19h USB4/Thunderbolt PCIe tunnel
5219 15c4 Phoenix USB4/Thunderbolt NHI controller #1
5220 15c5 Phoenix USB4/Thunderbolt NHI controller #2
5329 162e Rembrandt USB4/Thunderbolt NHI controller #1
5330 162f Rembrandt USB4/Thunderbolt NHI controller #2
5370 1668 Pink Sardine USB4/Thunderbolt NHI controller #1
[all …]
/aosp_15_r20/external/kotlinpoet/kotlinpoet/src/commonTest/kotlin/com/squareup/kotlinpoet/
H A DFileSpecTest.kt43 .addStatement("result.add(%T.createNimbus(%T.THUNDERBOLT))", hoverboard, namedBoards) in importStaticReadmeExample()
53 .addImport(namedBoards, "THUNDERBOLT") in importStaticReadmeExample()
61 |import com.mattel.Hoverboard.Boards.THUNDERBOLT in importStaticReadmeExample()
73 | result.add(createNimbus(THUNDERBOLT)) in importStaticReadmeExample()
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/twinlake/
H A DFspmUpd.h2101 /** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable
2102 Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
2107 /** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable
2108 Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
2113 /** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable
2114 Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
2119 /** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable
2120 Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/
H A DFspmUpd.h2078 /** Offset 0x0B5A - TCSS Thunderbolt PCIE Root Port 0 Enable
2079 Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
2084 /** Offset 0x0B5B - TCSS Thunderbolt PCIE Root Port 1 Enable
2085 Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
2090 /** Offset 0x0B5C - TCSS Thunderbolt PCIE Root Port 2 Enable
2091 Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
2096 /** Offset 0x0B5D - TCSS Thunderbolt PCIE Root Port 3 Enable
2097 Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake/
H A DFspmUpd.h2101 /** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable
2102 Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
2107 /** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable
2108 Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
2113 /** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable
2114 Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
2119 /** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable
2120 Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/
H A DFspmUpd.h2101 /** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable
2102 Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
2107 /** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable
2108 Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
2113 /** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable
2114 Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
2119 /** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable
2120 Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/
H A DFspmUpd.h2078 /** Offset 0x0BBA - TCSS Thunderbolt PCIE Root Port 0 Enable
2079 Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
2084 /** Offset 0x0BBB - TCSS Thunderbolt PCIE Root Port 1 Enable
2085 Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
2090 /** Offset 0x0BBC - TCSS Thunderbolt PCIE Root Port 2 Enable
2091 Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
2096 /** Offset 0x0BBD - TCSS Thunderbolt PCIE Root Port 3 Enable
2097 Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
/aosp_15_r20/external/coreboot/src/soc/intel/common/block/acpi/
H A Dpep.c255 /* Handle Thunderbolt displays */ in lpi_s0ix_entry()
282 /* Handle Thunderbolt displays */ in lpi_s0ix_exit()
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/raptorlake/
H A DFspmUpd.h2525 /** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable
2526 Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
2531 /** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable
2532 Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
2537 /** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable
2538 Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
2543 /** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable
2544 Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
/aosp_15_r20/external/coreboot/src/soc/intel/tigerlake/include/soc/
H A Dtcss.h6 /* Thunderbolt firmware IMR status */
/aosp_15_r20/external/coreboot/src/soc/intel/alderlake/include/soc/
H A Dtcss.h6 /* Thunderbolt firmware IMR status */
/aosp_15_r20/external/coreboot/src/soc/intel/meteorlake/include/soc/
H A Dtcss.h6 /* Thunderbolt firmware IMR status */

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