1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <timer.h>
5 #include <soc/usb/qmp_usb_phy.h>
6 #include <soc/addressmap.h>
7
8
9 /* Only for QMP V4 PHY - QSERDES COM registers */
10 struct usb3_phy_qserdes_com_reg_layout {
11 u8 _reserved1[16];
12 u32 com_ssc_en_center;
13 u32 com_ssc_adj_per1;
14 u32 com_ssc_adj_per2;
15 u32 com_ssc_per1;
16 u32 com_ssc_per2;
17 u32 com_ssc_step_size1_mode0;
18 u32 com_ssc_step_size2_mode0;
19 u32 com_ssc_step_size3_mode0;
20 u32 com_ssc_step_size1_mode1;
21 u32 com_ssc_step_size2_mode1;
22 u32 com_ssc_step_size3_mode1;
23 u8 _reserved2[8];
24 u32 com_bias_en_clkbuflr_en;
25 u32 com_sys_clk_enable1;
26 u32 com_sys_clk_ctrl;
27 u32 com_sysclk_buf_enable;
28 u32 com_pll_en;
29 u32 com_pll_ivco;
30 u8 _reserved3[4];
31 u32 com_cmn_iptrim;
32 u8 _reserved4[16];
33 u32 com_cp_ctrl_mode0;
34 u32 com_cp_ctrl_mode1;
35 u32 com_pll_rctrl_mode0;
36 u32 com_pll_rctrl_mode1;
37 u32 com_pll_cctrl_mode0;
38 u32 com_pll_cctrl_mode1;
39 u8 _reserved6[8];
40 u32 com_sysclk_en_sel;
41 u8 _reserved7[8];
42 u32 com_resetsm_ctrl2;
43 u32 com_lock_cmp_en;
44 u32 com_lock_cmp_cfg;
45 u32 com_lock_cmp1_mode0;
46 u32 com_lock_cmp2_mode0;
47 u32 com_lock_cmp1_mode1;
48 u32 com_lock_cmp2_mode1;
49 u32 com_dec_start_mode0;
50 u8 _reserved8[4];
51 u32 com_dec_start_mode1;
52 u8 _reserved9[4];
53 u32 com_div_frac_start1_mode0;
54 u32 com_div_frac_start2_mode0;
55 u32 com_div_frac_start3_mode0;
56 u32 com_div_frac_start1_mode1;
57 u32 com_div_frac_start2_mode1;
58 u32 com_div_frac_start3_mode1;
59 u8 _reserved10[8];
60 u32 com_integloop_gain0_mode0;
61 u32 com_integloop_gain1_mode0;
62 u8 _reserved11[24];
63 u32 com_vco_tune_map;
64 u32 com_vco_tune1_mode0;
65 u32 com_vco_tune2_mode0;
66 u32 com_vco_tune1_mode1;
67 u32 com_vco_tune2_mode1;
68 u8 _reserved12[52];
69 u32 com_clk_select;
70 u32 com_hsclk_sel;
71 u8 _reserved13[12];
72 u32 com_coreclk_div_mode0;
73 u32 com_coreclk_div_mode1;
74 u8 _reserved14[4];
75 u32 com_core_clk_en;
76 u32 com_c_ready_status;
77 u32 com_cmn_config;
78 u32 com_cmn_rate_override;
79 u32 com_svs_mode_clk_sel;
80 u8 _reserved15[36];
81 u32 com_bin_vcocal_cmp_code1_mode0;
82 u32 com_bin_vcocal_cmp_code2_mode0;
83 u32 com_bin_vcocal_cmp_code1_mode1;
84 u32 com_bin_vcocal_cmp_code2_mode1;
85 u32 com_bin_vcocal_hsclk_sel;
86 };
87
88 check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010);
89 check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014);
90 check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018);
91 check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c);
92 check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020);
93 check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x044);
94 check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x058);
95 check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x074);
96 check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x094);
97 check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x0a0);
98 check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0bc);
99 check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0cc);
100 check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0ec);
101 check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x010c);
102 check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x154);
103 check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x168);
104 check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x174);
105 check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x184);
106 check_member(usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_hsclk_sel, 0x1bc);
107
108 /* Only for QMP V4 PHY - TX registers */
109 struct usb3_phy_qserdes_tx_reg_layout {
110 u8 _reserved1[52];
111 u32 tx_res_code_lane_tx;
112 u32 tx_res_code_lane_rx;
113 u32 tx_res_code_lane_offset_tx;
114 u32 tx_res_code_lane_offset_rx;
115 u8 _reserved2[64];
116 u32 tx_lane_mode_1;
117 u8 _reserved3[20];
118 u32 tx_rcv_detect_lvl_2;
119 u8 _reserved4[100];
120 u32 tx_pi_qec_ctrl;
121 };
122 check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x03c);
123 check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x040);
124 check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x084);
125 check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x09c);
126 check_member(usb3_phy_qserdes_tx_reg_layout, tx_pi_qec_ctrl, 0x104);
127
128 /* Only for QMP V4 PHY - RX registers */
129 struct usb3_phy_qserdes_rx_reg_layout {
130 u8 _reserved1[20];
131 u32 rx_ucdr_so_gain;
132 u8 _reserved2[24];
133 u32 rx_ucdr_fastlock_fo_gain;
134 u32 rx_ucdr_so_saturation_and_enable;
135 u8 _reserved3[4];
136 u32 rx_ucdr_fastlock_count_low;
137 u32 rx_ucdr_fastlock_count_high;
138 u32 rx_ucdr_pi_controls;
139 u8 _reserved4[4];
140 u32 rx_ucdr_sb2_thresh1;
141 u32 rx_ucdr_sb2_thresh2;
142 u32 rx_ucdr_sb2_gain1;
143 u32 rx_ucdr_sb2_gain2;
144 u8 _reserved12[4];
145 u32 rx_aux_data_tcoarse_tfine;
146 u8 _reserved5[112];
147 u32 rx_vga_cal_cntrl1;
148 u32 rx_vga_cal_cntrl2;
149 u32 rx_gm_cal;
150 u8 _reserved6[12];
151 u32 rx_rx_equ_adaptor_cntrl2;
152 u32 rx_rx_equ_adaptor_cntrl3;
153 u32 rx_rx_equ_adaptor_cntrl4;
154 u32 rx_rx_idac_tsettle_low;
155 u32 rx_rx_idac_tsettle_high;
156 u8 _reserved7[16];
157 u32 rx_rx_eq_offset_adaptor_cntrl1;
158 u8 _reserved8[8];
159 u32 rx_sigdet_cntrl;
160 u8 _reserved9[4];
161 u32 rx_sigdet_deglitch_cntrl;
162 u8 _reserved10[72];
163 u32 rx_rx_mode_00_low;
164 u32 rx_rx_mode_00_high;
165 u32 rx_rx_mode_00_high2;
166 u32 rx_rx_mode_00_high3;
167 u32 rx_rx_mode_00_high4;
168 u32 rx_rx_mode_01_low;
169 u32 rx_rx_mode_01_high;
170 u32 rx_rx_mode_01_high2;
171 u32 rx_rx_mode_01_high3;
172 u32 rx_rx_mode_01_high4;
173 u8 _reserved11[28];
174 u32 rx_dfe_en_timer;
175 u32 rx_dfe_ctle_post_cal_offset;
176 u32 rx_dcc_ctrl1;
177 u8 _reserved13[4];
178 u32 rx_vth_code;
179 };
180
181 check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain, 0x014);
182 check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030);
183 check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1, 0x0d4);
184 check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl2, 0x0ec);
185 check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl3, 0x0f0);
186 check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl4, 0x0f4);
187 check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl, 0x11c);
188 check_member(usb3_phy_qserdes_rx_reg_layout, rx_dcc_ctrl1, 0x1bc);
189 check_member(usb3_phy_qserdes_rx_reg_layout, rx_vth_code, 0x1c4);
190
191 /* Only for QMP V4 PHY - PCS registers */
192 struct usb3_phy_pcs_reg_layout {
193 u32 pcs_sw_reset;
194 u8 _reserved0[16];
195 u32 pcs_ready_status;
196 u8 _reserved1[40];
197 u32 pcs_power_down_control;
198 u32 pcs_start_control;
199 u8 _reserved2[124];
200 u32 pcs_lock_detect_config1;
201 u32 pcs_lock_detect_config2;
202 u32 pcs_lock_detect_config3;
203 u8 _reserved3[8];
204 u32 pcs_lock_detect_config6;
205 u32 pcs_refgen_req_config1;
206 u8 _reserved4[168];
207 u32 pcs_rx_sigdet_lvl;
208 u8 _reserved5[36];
209 u32 pcs_cdr_reset_time;
210 u8 _reserved6[12];
211 u32 pcs_align_detect_config1;
212 u32 pcs_align_detect_config2;
213 u8 _reserved7[8];
214 u32 pcs_pcs_tx_rx_config;
215 u8 _reserved8[8];
216 u32 pcs_eq_config1;
217 u8 _reserved9[12];
218 u32 pcs_eq_config5;
219 u8 _reserved10[296];
220 u32 pcs_usb3_lfps_det_high_count_val;
221 u8 _reserved11[28];
222 u32 pcs_usb3_rxeqtraining_dfe_time_s2;
223 };
224
225 check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x0c4);
226 check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x0c8);
227 check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config6, 0x0d8);
228 check_member(usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config, 0x1d0);
229 check_member(usb3_phy_pcs_reg_layout, pcs_eq_config5, 0x1ec);
230 check_member(usb3_phy_pcs_reg_layout, pcs_usb3_lfps_det_high_count_val, 0x318);
231 check_member(usb3_phy_pcs_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2, 0x338);
232
233 static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout =
234 (void *)QMP_PHY_QSERDES_COM_REG_BASE;
235 static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout =
236 (void *)QMP_PHY_QSERDES_TX_REG_BASE;
237 static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout =
238 (void *)QMP_PHY_QSERDES_RX_REG_BASE;
239 static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout =
240 (void *)QMP_PHY_PCS_REG_BASE;
241 static const struct qmp_phy_init_tbl qmp_v4_usb3_serdes_tbl[] = {
242 {&qserdes_com_reg_layout->com_ssc_en_center, 0x01},
243 {&qserdes_com_reg_layout->com_ssc_per1, 0x31},
244 {&qserdes_com_reg_layout->com_ssc_per2, 0x01},
245 {&qserdes_com_reg_layout->com_ssc_step_size1_mode0, 0xde},
246 {&qserdes_com_reg_layout->com_ssc_step_size2_mode0, 0x07},
247 {&qserdes_com_reg_layout->com_ssc_step_size1_mode1, 0xde},
248 {&qserdes_com_reg_layout->com_ssc_step_size2_mode1, 0x07},
249 {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a},
250 {&qserdes_com_reg_layout->com_cmn_iptrim, 0x20},
251 {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06},
252 {&qserdes_com_reg_layout->com_cp_ctrl_mode1, 0x06},
253 {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16},
254 {&qserdes_com_reg_layout->com_pll_rctrl_mode1, 0x16},
255 {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36},
256 {&qserdes_com_reg_layout->com_pll_cctrl_mode1, 0x36},
257 {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x1a},
258 {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04},
259 {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x14},
260 {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34},
261 {&qserdes_com_reg_layout->com_lock_cmp1_mode1, 0x34},
262 {&qserdes_com_reg_layout->com_lock_cmp2_mode1, 0x82},
263 {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82},
264 {&qserdes_com_reg_layout->com_dec_start_mode1, 0x82},
265 {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab},
266 {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea},
267 {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02},
268 {&qserdes_com_reg_layout->com_div_frac_start1_mode1, 0xab},
269 {&qserdes_com_reg_layout->com_div_frac_start2_mode1, 0xea},
270 {&qserdes_com_reg_layout->com_div_frac_start3_mode1, 0x02},
271 {&qserdes_com_reg_layout->com_vco_tune_map, 0x02},
272 {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0x24},
273 {&qserdes_com_reg_layout->com_vco_tune1_mode1, 0x24},
274 {&qserdes_com_reg_layout->com_vco_tune2_mode1, 0x02},
275 {&qserdes_com_reg_layout->com_hsclk_sel, 0x01},
276 {&qserdes_com_reg_layout->com_coreclk_div_mode1, 0x08},
277 {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode0, 0xca},
278 {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode0, 0x1e},
279 {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode1, 0xca},
280 {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode1, 0x1e},
281 {&qserdes_com_reg_layout->com_bin_vcocal_hsclk_sel, 0x11},
282 };
283
284 static const struct qmp_phy_init_tbl qmp_v4_usb3_tx_tbl[] = {
285 {&qserdes_tx_reg_layout->tx_res_code_lane_tx, 0x60},
286 {&qserdes_tx_reg_layout->tx_res_code_lane_rx, 0x60},
287 {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x11},
288 {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x02},
289 {&qserdes_tx_reg_layout->tx_lane_mode_1, 0xd5},
290 {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12},
291 {&qserdes_tx_reg_layout->tx_pi_qec_ctrl, 0x40},
292 };
293
294 static const struct qmp_phy_init_tbl qmp_v4_usb3_rx_tbl[] = {
295 {&qserdes_rx_reg_layout->rx_ucdr_so_gain, 0x06},
296 {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x2f},
297 {&qserdes_rx_reg_layout->rx_ucdr_so_saturation_and_enable, 0x7f},
298 {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_low, 0xff},
299 {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_high, 0x0f},
300 {&qserdes_rx_reg_layout->rx_ucdr_pi_controls, 0x99},
301 {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh1, 0x04},
302 {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh2, 0x08},
303 {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain1, 0x05},
304 {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain2, 0x05},
305 {&qserdes_rx_reg_layout->rx_vga_cal_cntrl1, 0x54},
306 {&qserdes_rx_reg_layout->rx_vga_cal_cntrl2, 0x0c},
307 {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl2, 0x0f},
308 {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl3, 0x4a},
309 {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl4, 0x0a},
310 {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_low, 0xc0},
311 {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_high, 0x00},
312 {&qserdes_rx_reg_layout->rx_rx_eq_offset_adaptor_cntrl1, 0x77},
313 {&qserdes_rx_reg_layout->rx_sigdet_cntrl, 0x04},
314 {&qserdes_rx_reg_layout->rx_sigdet_deglitch_cntrl, 0x0e},
315 {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0xff},
316 {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0x7f},
317 {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0x7f},
318 {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0xff},
319 {&qserdes_rx_reg_layout->rx_rx_mode_00_high2, 0x7f},
320 {&qserdes_rx_reg_layout->rx_rx_mode_00_high3, 0x7f},
321 {&qserdes_rx_reg_layout->rx_rx_mode_00_high4, 0x97},
322 {&qserdes_rx_reg_layout->rx_rx_mode_01_low, 0xdc},
323 {&qserdes_rx_reg_layout->rx_rx_mode_01_high, 0xdc},
324 {&qserdes_rx_reg_layout->rx_rx_mode_01_high2, 0x5c},
325 {&qserdes_rx_reg_layout->rx_rx_mode_01_high3, 0x7b},
326 {&qserdes_rx_reg_layout->rx_rx_mode_01_high4, 0xb4},
327 {&qserdes_rx_reg_layout->rx_dfe_en_timer, 0x04},
328 {&qserdes_rx_reg_layout->rx_dfe_ctle_post_cal_offset, 0x38},
329 {&qserdes_rx_reg_layout->rx_aux_data_tcoarse_tfine, 0xa0},
330 {&qserdes_rx_reg_layout->rx_dcc_ctrl1, 0x0c},
331 {&qserdes_rx_reg_layout->rx_gm_cal, 0x1f},
332 {&qserdes_rx_reg_layout->rx_vth_code, 0x10},
333 };
334
335 static const struct qmp_phy_init_tbl qmp_v4_usb3_pcs_tbl[] = {
336 {&pcs_reg_layout->pcs_lock_detect_config1, 0xd0},
337 {&pcs_reg_layout->pcs_lock_detect_config2, 0x07},
338 {&pcs_reg_layout->pcs_lock_detect_config3, 0x20},
339 {&pcs_reg_layout->pcs_lock_detect_config6, 0x13},
340 {&pcs_reg_layout->pcs_refgen_req_config1, 0x21},
341 {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xa9},
342 {&pcs_reg_layout->pcs_cdr_reset_time, 0x0a},
343 {&pcs_reg_layout->pcs_align_detect_config1, 0x88},
344 {&pcs_reg_layout->pcs_align_detect_config2, 0x13},
345 {&pcs_reg_layout->pcs_pcs_tx_rx_config, 0x0c},
346 {&pcs_reg_layout->pcs_eq_config1, 0x4b},
347 {&pcs_reg_layout->pcs_eq_config5, 0x10},
348 {&pcs_reg_layout->pcs_usb3_lfps_det_high_count_val, 0xf8},
349 {&pcs_reg_layout->pcs_usb3_rxeqtraining_dfe_time_s2, 0x07},
350 };
351
352 struct ss_usb_phy_reg qmp_v4_usb_phy = {
353 .serdes_tbl = qmp_v4_usb3_serdes_tbl,
354 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_serdes_tbl),
355 .tx_tbl = qmp_v4_usb3_tx_tbl,
356 .tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_tx_tbl),
357 .rx_tbl = qmp_v4_usb3_rx_tbl,
358 .rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_rx_tbl),
359 .pcs_tbl = qmp_v4_usb3_pcs_tbl,
360 .pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_tbl),
361 .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE,
362 };
363
qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[],int num)364 static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[],
365 int num)
366 {
367 int i;
368 const struct qmp_phy_init_tbl *t = tbl;
369
370 if (!t)
371 return;
372
373 for (i = 0; i < num; i++, t++)
374 write32(t->address, t->val);
375 }
376
ss_qmp_phy_init(void)377 void ss_qmp_phy_init(void)
378 {
379 struct ss_usb_phy_reg *ss_phy_reg;
380
381 ss_phy_reg = &qmp_v4_usb_phy;
382
383 /* power up USB3 PHY */
384 write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01);
385
386 /* Serdes configuration */
387 qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl,
388 ss_phy_reg->serdes_tbl_num);
389 /* Tx, Rx, and PCS configurations */
390 qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num);
391 qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num);
392 qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num);
393
394 /* perform software reset of PCS/Serdes */
395 write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00);
396 /* start PCS/Serdes to operation mode */
397 write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03);
398
399 /*
400 * Wait for PHY initialization to be done
401 * PCS_STATUS: wait for 1ms for PHY STATUS;
402 * SW can continuously check for PHYSTATUS = 1.b0.
403 */
404 long lock_us = wait_us(10000,
405 !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) &
406 USB3_PCS_PHYSTATUS));
407 if (!lock_us)
408 printk(BIOS_ERR, "QMP PHY PLL LOCK fails:\n");
409 else
410 printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n",
411 lock_us);
412 }
413