1 /*============================================================================== 2 Copyright(c) 2017 Intel Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files(the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and / or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included 12 in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 OTHER DEALINGS IN THE SOFTWARE. 21 ============================================================================*/ 22 /* 23 File Name: sku_wa.h 24 25 Description: 26 Common hardware sku and workaround information structures. 27 28 This file is commented in a manner allowing automated parsing of WA information. 29 Each entry inside WA table should include comments in form of: 30 @WorkaroundName <name-mandatory> //this field is mandatory 31 @Description <short description (can be multiline) 32 @PerfImpact <performance impact> 33 @BugType <hang,crash etc.> 34 @Component <Gmm> 35 36 \*****************************************************************************/ 37 #ifndef __SKU_WA_H__ 38 #define __SKU_WA_H__ 39 40 // Prevent the following... 41 // warning: ISO C++ prohibits anonymous structs [-pedantic] 42 // warning: ISO C90 doesn't support unnamed structs/unions [-pedantic] 43 #if defined(__clang__) 44 #pragma clang diagnostic push 45 #pragma clang diagnostic ignored "-Wpedantic" // clang only recognizes -Wpedantic 46 #elif defined(__GNUC__) 47 #pragma GCC diagnostic push 48 #if __GNUC__ >= 6 49 #pragma GCC diagnostic ignored "-Wpedantic" 50 #else 51 #pragma GCC diagnostic ignored "-pedantic" // gcc <= 4.7.4 only recognizes -pedantic 52 #endif 53 #endif 54 55 //********************************** SKU **************************************** 56 57 // Sku Table structure to abstract sku based hw feature availability 58 // For any Sku based feature, add a field in this structure 59 60 typedef struct _SKU_FEATURE_TABLE 61 { 62 // flags 1 = available, 0 = not available 63 struct //_sku_Core 64 { 65 unsigned int FtrULT : 1; // Indicates ULT SKU 66 unsigned int FtrVERing : 1; // Separate Ring for VideoEnhancement commands 67 unsigned int FtrVcs2 : 1; // Second VCS engine supported on Gen8 to Gen10 (in some configurations); 68 unsigned int FtrLCIA : 1; // Indicates Atom (Low Cost Intel Architecture) 69 unsigned int FtrCCSRing : 1; // To indicate if CCS hardware ring support is present. 70 unsigned int FtrCCSNode : 1; // To indicate if CCS Node support is present. 71 unsigned int FtrTileY : 1; // Identifies Legacy tiles TileY/Yf/Ys on the platform 72 unsigned int FtrCCSMultiInstance : 1; // To indicate if driver supports MultiContext mode on RCS and more than 1 CCS. 73 unsigned int FtrL3TransientDataFlush : 1; // Transient data flush from L3 cache 74 }; 75 76 77 struct //_sku_KMD_render 78 { // MI commends are capable to set 79 80 unsigned int FtrPPGTT : 1; // Per-Process GTT 81 unsigned int FtrIA32eGfxPTEs : 1; // GTT/PPGTT's use 64-bit IA-32e PTE format. 82 unsigned int FtrMemTypeMocsDeferPAT : 1; // Pre-Gen12 MOCS can defers to PAT, e.g. eLLC Target Cache for MOCS 83 unsigned int FtrPml4Support : 1; // PML4-based gfx page tables are supported (in addition to PD-based tables). 84 unsigned int FtrSVM : 1; // Shared Virtual Memory (i.e. support for SVM buffers which can be accessed by both the CPU and GPU at numerically equivalent addresses.) 85 unsigned int FtrTileMappedResource : 1; // Tiled Resource support aka Sparse Textures. 86 unsigned int FtrTranslationTable : 1; // Translation Table support for Tiled Resources. 87 unsigned int FtrUserModeTranslationTable : 1; // User mode managed Translation Table support for Tiled Resources. 88 unsigned int FtrNullPages : 1; // Support for PTE-based Null pages for Sparse/Tiled Resources). 89 unsigned int FtrEDram : 1; // embedded DRAM enable 90 unsigned int FtrLLCBypass : 1; // Partial tunneling of UC memory traffic via CCF (LLC Bypass) 91 unsigned int FtrCrystalwell : 1; // Crystalwell Sku 92 unsigned int FtrCentralCachePolicy : 1; // Centralized Cache Policy 93 unsigned int FtrWddm2GpuMmu : 1; // WDDMv2 GpuMmu Model (Set in platform SKU files, but disabled by GMM as appropriate for given system.) 94 unsigned int FtrWddm2Svm : 1; // WDDMv2 SVM Model (Set in platform SKU files, but disabled by GMM as appropriate for given system.) 95 unsigned int FtrStandardMipTailFormat : 1; // Dx Standard MipTail Format for TileYf/Ys 96 unsigned int FtrWddm2_1_64kbPages : 1; // WDDMv2.1 64KB page support 97 unsigned int FtrE2ECompression : 1; // E2E Compression ie Aux Table support 98 unsigned int FtrLinearCCS : 1; // Linear Aux surface is supported 99 unsigned int FtrFrameBufferLLC : 1; // Displayable Frame buffers cached in LLC 100 unsigned int FtrDriverFLR : 1; // Enable Function Level Reset (Gen11+) 101 unsigned int FtrLocalMemory : 1; 102 unsigned int FtrCameraCaptureCaching : 1; 103 unsigned int FtrLocalMemoryAllows4KB : 1; 104 unsigned int FtrPpgtt64KBWalkOptimization : 1; // XeHP 64KB Page table walk optimization on PPGTT. 105 unsigned int FtrFlatPhysCCS : 1; // XeHP compression ie flat physical CCS 106 unsigned int FtrDisplayXTiling : 1; // Fallback to Legacy TileX Display, used for Pre-SI platforms. 107 unsigned int FtrMultiTileArch : 1; 108 unsigned int FtrDisplayPageTables : 1; // Display Page Tables: 2-Level Page walk for Displayable Frame buffers in GGTT. 109 unsigned int Ftr57bGPUAddressing : 1; // 57b GPUVA support eg: PVC 110 unsigned int FtrUnified3DMediaCompressionFormats : 1; // DG2 has unified Render/media compression(versus TGLLP/XeHP_SDV 's multiple instances) and requires changes to RC format h/w encodings. 111 unsigned int FtrForceTile4 : 1; // Flag to force Tile4 usage as default in Tile64 supported platforms. 112 unsigned int FtrTile64Optimization : 1; 113 unsigned int FtrDiscrete : 1; // Discrete-gfx 114 unsigned int FtrXe2Compression : 1; // Xe2 Stateless Compression 115 unsigned int FtrXe2PlusTiling : 1; // Tile64 MSAA Layout 116 unsigned int FtrL4Cache : 1; // L4 cache support 117 unsigned int FtrPml5Support : 1; // xe2 page tables 118 119 }; 120 121 122 struct //_sku_3d 123 { 124 unsigned int FtrAstcLdr2D : 1; // ASTC 2D LDR Mode Support (mutually exclusive from other ASTC Ftr's) 125 unsigned int FtrAstcHdr2D : 1; // ASTC 2D HDR Mode Support (mutually exclusive from other ASTC Ftr's) 126 unsigned int FtrAstc3D : 1; // ASTC 3D LDR/HDR Mode Support (mutually exclusive from other ASTC Ftr's) 127 }; 128 129 struct //_sku_PwrCons 130 { 131 //FBC 132 unsigned int FtrFbc : 1; // Frame Buffer Compression 133 134 }; 135 136 struct //_sku_Display 137 { 138 unsigned int FtrRendComp : 1; // For Render Compression Feature on Gen9+ 139 unsigned int FtrDisplayYTiling : 1; // For Y Tile Feature on Gen9+ 140 unsigned int FtrDisplayDisabled : 1; // Server skus with Display 141 142 }; 143 144 struct 145 { 146 unsigned int FtrS3D : 1; // Stereoscopic 3D 147 unsigned int FtrDisplayEngineS3d : 1; // Display Engine Stereoscopic 3D 148 }; 149 150 struct // Virtualization features 151 { 152 unsigned int FtrVgt : 1; 153 }; 154 struct // For MultiTileArch, KMD reports default tile assignment to UMD-GmmLib - via __KmQueryDriverPrivateInfo 155 { 156 unsigned int FtrAssignedGpuTile : 3; // Indicates Gpu Tile number assigned to a process for Naive apps. 157 }; 158 159 } SKU_FEATURE_TABLE, *PSKU_FEATURE_TABLE; 160 161 #if defined(__clang__) 162 #pragma clang diagnostic pop 163 #elif defined(__GNUC__) 164 #pragma GCC diagnostic pop 165 #endif 166 167 //********************************** WA **************************************** 168 169 #define WA_DECLARE( wa, wa_comment, wa_bugType, wa_impact, wa_component) unsigned int wa : 1; 170 171 enum WA_BUG_TYPE 172 { 173 WA_BUG_TYPE_UNKNOWN = 0, 174 WA_BUG_TYPE_CORRUPTION = 1, 175 WA_BUG_TYPE_HANG = 2, 176 WA_BUG_TYPE_PERF = 4, 177 WA_BUG_TYPE_FUNCTIONAL = 8, 178 WA_BUG_TYPE_SPEC = 16, 179 WA_BUG_TYPE_FAIL = 32 180 }; 181 182 #define WA_BUG_PERF_IMPACT(f) f 183 #define WA_BUG_PERF_IMPACT_UNKNOWN -1 184 185 enum WA_COMPONENT 186 { 187 WA_COMPONENT_UNKNOWN = 0, 188 WA_COMPONENT_GMM = 0x1, 189 WA_COMPONENT_MEDIA = 0x2, 190 WA_COMPONENT_OCL = 0x3, 191 }; 192 193 // Workaround Table structure to abstract WA based on hw and rev id 194 typedef struct _WA_TABLE 195 { 196 // struct wa_3d 197 unsigned int : 0; 198 199 WA_DECLARE( 200 WaAlignIndexBuffer, 201 "Force the end of the index buffer to be cacheline-aligned to work around a hardware bug that performs no bounds checking on accesses past the end of the index buffer when it only partially fills a cacheline.", 202 WA_BUG_TYPE_CORRUPTION, 203 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 204 205 // struct _wa_Gmm 206 unsigned int : 0; 207 208 WA_DECLARE( 209 WaValign2ForR8G8B8UINTFormat, 210 "sampler format decoding error in HW for this particular format double fetching is happening, WA is to use VALIGN_2 instead of VALIGN_4", 211 WA_BUG_TYPE_CORRUPTION, 212 WA_BUG_PERF_IMPACT(0), WA_COMPONENT_UNKNOWN) 213 214 WA_DECLARE( 215 WaValign2For96bppFormats, 216 "VALIGN_2 only for 96bpp formats.", 217 WA_BUG_TYPE_UNKNOWN, 218 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 219 220 WA_DECLARE( 221 WaCursor16K, 222 "Cursor memory need to be mapped in GTT", 223 WA_BUG_TYPE_UNKNOWN, 224 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 225 226 WA_DECLARE( 227 Wa8kAlignforAsyncFlip, 228 "Enable 8k pitch alignment for Asynchronous Flips in rotated mode. (!) Unconventional use! When used, set each XP mode-change (not in platform WA file)!", 229 WA_BUG_TYPE_UNKNOWN, 230 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 231 232 WA_DECLARE( 233 Wa29BitDisplayAddrLimit, 234 "Sprite/Overlay/Display addresses limited to 29 bits (512MB)", 235 WA_BUG_TYPE_UNKNOWN, 236 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 237 238 WA_DECLARE( 239 WaAlignContextImage, 240 "WA for context alignment", 241 WA_BUG_TYPE_UNKNOWN, 242 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 243 244 WA_DECLARE( 245 WaForceGlobalGTT, 246 "WA for cmds requiring memory address to come from global GTT, not PPGTT.", 247 WA_BUG_TYPE_UNKNOWN, 248 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 249 250 WA_DECLARE( 251 WaReportPerfCountForceGlobalGTT, 252 "WA for MI_REPORT_PERF_COUNT cmd requiring memory address to come from global GTT, not PPGTT.", 253 WA_BUG_TYPE_UNKNOWN, 254 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 255 256 WA_DECLARE( 257 WaOaAddressTranslation, 258 "WA for STDW and PIPE_CONTROL cmd requiring memory address to come from global GTT, not PPGTT.", 259 WA_BUG_TYPE_UNKNOWN, 260 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 261 262 WA_DECLARE( 263 Wa2RowVerticalAlignment, 264 "WA to set VALIGN of sample and rt buffers.", 265 WA_BUG_TYPE_UNKNOWN, 266 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 267 268 WA_DECLARE( 269 WaPpgttAliasGlobalGttSpace, 270 "Disallow independent PPGTT space--i.e. the PPGTT must simply alias global GTT space. (N/A without FtrPageDirectory set.)", 271 WA_BUG_TYPE_UNKNOWN, 272 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 273 274 WA_DECLARE( 275 WaClearFenceRegistersAtDriverInit, 276 "WA to clear all fence registers at driver init time.", 277 WA_BUG_TYPE_UNKNOWN, 278 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 279 280 WA_DECLARE( 281 WaRestrictPitch128KB, 282 "Restrict max surface pitch to 128KB.", 283 WA_BUG_TYPE_UNKNOWN, 284 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 285 286 WA_DECLARE( 287 WaAvoidLLC, 288 "Avoid LLC use. (Intended for debug purposes only.)", 289 WA_BUG_TYPE_UNKNOWN, 290 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 291 292 WA_DECLARE( 293 WaAvoidL3, 294 "Avoid L3 use (but don't reconfigure; and naturally URB/etc. still need L3). (Intended for debug purposes only.)", 295 WA_BUG_TYPE_UNKNOWN, 296 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 297 298 WA_DECLARE( 299 Wa16TileFencesOnly, 300 "Limit to 16 tiling fences --Set at run-time by GMM.", 301 WA_BUG_TYPE_UNKNOWN, 302 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 303 304 WA_DECLARE( 305 Wa16MBOABufferAlignment, 306 "WA align the base address of the OA buffer to 16mb", 307 WA_BUG_TYPE_UNKNOWN, 308 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 309 310 WA_DECLARE( 311 WaTranslationTableUnavailable, 312 "WA for BXT and SKL skus without Tiled-Resource Translation-Table (TR-TT)", 313 WA_BUG_TYPE_SPEC, 314 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 315 316 WA_DECLARE( 317 WaNoMinimizedTrivialSurfacePadding, 318 "(Not actual HW WA.) On BDW:B0+ trivial surfaces (single-LOD, non-arrayed, non-MSAA, 1D/2D/Buffers) are exempt from the samplers large padding requirements. This WA identifies platforms that dont yet support that.", 319 WA_BUG_TYPE_UNKNOWN, 320 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 321 322 WA_DECLARE( 323 WaNoBufferSamplerPadding, 324 "Client agreeing to take responsibility for flushing L3 after sampling/etc.", 325 WA_BUG_TYPE_UNKNOWN, 326 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 327 328 WA_DECLARE( 329 WaSurfaceStatePlanarYOffsetAlignBy2, 330 "WA to align SURFACE_STATE Y Offset for UV Plane by 2", 331 WA_BUG_TYPE_UNKNOWN, 332 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 333 334 WA_DECLARE( 335 WaGttCachingOffByDefault, 336 "WA to enable the caching if off by defaultboth at driver init and Resume", 337 WA_BUG_TYPE_UNKNOWN, 338 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 339 340 WA_DECLARE( 341 WaTouchAllSvmMemory, 342 "When in WDDM2 / SVM mode, all VA memory buffers/surfaces/etc need to be touched to ensure proper PTE mapping", 343 WA_BUG_TYPE_UNKNOWN, 344 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 345 346 WA_DECLARE( 347 WaIOBAddressMustBeValidInHwContext, 348 "IndirectObjectBase address (of SBA cmd) in HW Context needs to be valid because it gets used every Context load", 349 WA_BUG_TYPE_HANG, 350 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 351 352 WA_DECLARE( 353 WaFlushTlbAfterCpuGgttWrites, 354 "WA to flush TLB after CPU GTT writes because TLB entry invalidations on GTT writes use wrong address for look-up", 355 WA_BUG_TYPE_FUNCTIONAL, 356 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 357 358 WA_DECLARE( 359 WaMsaa8xTileYDepthPitchAlignment, 360 "WA to use 256B pitch alignment for MSAA 8x + TileY depth surfaces.", 361 WA_BUG_TYPE_UNKNOWN, 362 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 363 364 WA_DECLARE( 365 WaDisableNullPageAsDummy, 366 "WA to disable use of NULL bit in dummy PTE", 367 WA_BUG_TYPE_HANG | WA_BUG_TYPE_CORRUPTION, 368 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 369 370 WA_DECLARE( 371 WaUseVAlign16OnTileXYBpp816, 372 "WA to make VAlign = 16, when bpp == 8 or 16 for both TileX and TileY on BDW", 373 WA_BUG_TYPE_CORRUPTION, 374 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 375 376 WA_DECLARE( 377 WaNoMocsEllcOnly, 378 "WA to get eLLC Target Cache for MOCS surfaces, when MOCS defers to PAT", 379 WA_BUG_TYPE_FUNCTIONAL, 380 WA_BUG_PERF_IMPACT, WA_COMPONENT_GMM) 381 382 WA_DECLARE( 383 WaGttPat0, 384 "GTT accesses hardwired to PAT0", 385 WA_BUG_TYPE_FUNCTIONAL, 386 WA_BUG_PERF_IMPACT, WA_COMPONENT_GMM) 387 388 WA_DECLARE( 389 WaGttPat0WB, 390 "WA to set WB cache for GTT accessess on PAT0", 391 WA_BUG_TYPE_FUNCTIONAL, 392 WA_BUG_PERF_IMPACT, WA_COMPONENT_GMM) 393 394 WA_DECLARE( 395 WaMemTypeIsMaxOfPatAndMocs, 396 "WA to set PAT.MT = UC. Since TGLLP uses MAX function to resolve PAT vs MOCS MemType So unless PTE.PAT says UC, MOCS won't be able to set UC!", 397 WA_BUG_TYPE_FUNCTIONAL, 398 WA_BUG_PERF_IMPACT, WA_COMPONENT_GMM) 399 400 WA_DECLARE( 401 WaGttPat0GttWbOverOsIommuEllcOnly, 402 "WA to set PAT0 to full cacheable (LLC+eLLC) for GTT access over eLLC only usage for OS based SVM", 403 WA_BUG_TYPE_FUNCTIONAL, 404 WA_BUG_PERF_IMPACT, WA_COMPONENT_GMM) 405 406 WA_DECLARE( 407 WaAddDummyPageForDisplayPrefetch, 408 "WA to add dummy page row after display surfaces to avoid issues with display pre-fetch", 409 WA_BUG_TYPE_CORRUPTION, 410 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 411 412 WA_DECLARE( 413 WaLLCCachingUnsupported, 414 "There is no H/w support for LLC in VLV or VLV Plus", 415 WA_BUG_TYPE_UNKNOWN, 416 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 417 418 WA_DECLARE( 419 WaEncryptedEdramOnlyPartials, 420 "Disable Edram only caching for encrypted usage", 421 WA_BUG_TYPE_CORRUPTION, 422 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 423 424 WA_DECLARE( 425 WaDisableEdramForDisplayRT, 426 "WA to disable EDRAM cacheability of Displayable Render Targets on SKL Steppings until I0", 427 WA_BUG_TYPE_PERF, 428 WA_BUG_PERF_IMPACT, WA_COMPONENT_GMM) 429 430 WA_DECLARE( 431 WaAstcCorruptionForOddCompressedBlockSizeX, 432 "Enable CHV D0+ WA for ASTC HW bug: sampling from mip levels 2+ returns wrong texels. WA adds XOffset to mip2+, requires D0 HW ECO fix.", 433 WA_BUG_TYPE_CORRUPTION, 434 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 435 436 WA_DECLARE( 437 WaLosslessCompressionSurfaceStride, 438 "WA to align surface stride for unified aux surfaces", 439 WA_BUG_TYPE_UNKNOWN, 440 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 441 442 WA_DECLARE( 443 Wa4kAlignUVOffsetNV12LinearSurface, 444 "WA to align UV plane offset at 4k page for NV12 Linear FlipChain surfaces", 445 WA_BUG_TYPE_CORRUPTION, 446 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 447 448 WA_DECLARE( 449 WaFbcLinearSurfaceStride, 450 "WA to align surface stride for linear primary surfaces", 451 WA_BUG_TYPE_UNKNOWN, 452 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 453 454 WA_DECLARE( 455 WaDoubleFastClearWidthAlignment, 456 "For all HSW GT3 skus and for all HSW GT E0+ skus, must double the width alignment when performing fast clears.", 457 WA_BUG_TYPE_CORRUPTION, 458 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 459 460 WA_DECLARE( 461 WaCompressedResourceRequiresConstVA21, 462 "3D and Media compressed resources should not have addresses that change within bit range [20:0]", 463 WA_BUG_TYPE_UNKNOWN, 464 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 465 466 WA_DECLARE( 467 WaDisregardPlatformChecks, 468 "Disable plarform checks to surface allocation.", 469 WA_BUG_TYPE_UNKNOWN, 470 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 471 472 WA_DECLARE( 473 WaAlignYUVResourceToLCU, 474 "source and recon surfaces need to be aligned to the LCU size", 475 WA_BUG_TYPE_CORRUPTION, 476 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 477 478 WA_DECLARE( 479 Wa32bppTileY2DColorNoHAlign4, 480 "Wa to defeature HALIGN_4 for 2D 32bpp RT surfaces, due to bug introduced from daprsc changes to help RCPB generate correct offsets to deal with cam match", 481 WA_BUG_TYPE_CORRUPTION, 482 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 483 484 WA_DECLARE( 485 WaAuxTable16KGranular, 486 "AuxTable map granularity changed to 16K ", 487 WA_BUG_TYPE_PERF, 488 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 489 490 WA_DECLARE( 491 WaAuxTable64KGranular, 492 "AuxTable map granularity changed to 64K ..Remove once Neo switches reference to WaAuxTable16KGranular", 493 WA_BUG_TYPE_PERF, 494 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 495 496 WA_DECLARE( 497 WaLimit128BMediaCompr, 498 "WA to limit media decompression on Render pipe to 128B (2CLs) 4:n.", 499 WA_BUG_TYPE_FUNCTIONAL, 500 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 501 502 WA_DECLARE( 503 WaUntypedBufferCompression, 504 "WA to allow untyped raw buffer AuxTable mapping", 505 WA_BUG_TYPE_FUNCTIONAL, 506 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 507 508 WA_DECLARE( 509 Wa64kbMappingAt2mbGranularity, 510 "WA to force 2MB alignment for 64KB-LMEM pages", 511 WA_BUG_TYPE_FUNCTIONAL, 512 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 513 514 WA_DECLARE( 515 WaDefaultTile4, 516 "[XeHP] Keep Tile4 as default on XeHP till B stepping", 517 WA_BUG_TYPE_UNKNOWN, 518 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 519 520 WA_DECLARE( 521 Wa_1606955757, 522 "[GPSSCLT] [XeHP] Multicontext (LB) : out-of-order write-read access to scratch space from hdctlbunit", 523 WA_BUG_TYPE_UNKNOWN, 524 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_OGL) 525 526 WA_DECLARE( 527 WaTile64Optimization, 528 "Tile64 wastge a lot of memory so WA provides optimization to fall back to Tile4 when waste is relatively higher", 529 WA_BUG_TYPE_UNKNOWN, 530 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 531 532 WA_DECLARE( 533 Wa_15010089951, 534 "[DG2][Silicon][Perf]DG2 VESFC performance when Compression feature is enabled.", 535 WA_BUG_TYPE_PERF, 536 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 537 538 WA_DECLARE( 539 Wa_22016140776, 540 "[PVC] operation unexpectedly results in NAN", 541 WA_BUG_TYPE_UNKNOWN, 542 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 543 544 WA_DECLARE( 545 Wa_14018443005, 546 "[Xe2] - Incorrect handling of compression when changing cached PA usage from compression OFF and another client does partial sector compression ON on W with UC", 547 WA_BUG_TYPE_UNKNOWN, 548 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 549 550 WA_DECLARE( 551 Wa_14018976079, 552 "[LNL] CPU-GPU False sharing broken for 1-way coherent pages", 553 WA_BUG_TYPE_UNKNOWN, 554 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 555 556 WA_DECLARE( 557 Wa_14018984349, 558 "[LNL] CPU-GPU False sharing broken for non-coherent pages", 559 WA_BUG_TYPE_UNKNOWN, 560 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 561 562 WA_DECLARE( 563 Wa_14020040029, 564 "Misalignment on Depth buffer for Zplanes", 565 WA_BUG_TYPE_UNKNOWN, 566 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_GMM) 567 568 WA_DECLARE( 569 Wa_EmuMufasaSupportOnBmg, 570 "WA for supporting failure seen in BMG with Mufasa", 571 WA_BUG_TYPE_FUNCTIONAL, 572 WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN) 573 574 } WA_TABLE, *PWA_TABLE; 575 576 //********************************** SKU/WA Macros ************************************* 577 578 #if (defined(__MINIPORT) || defined(__KCH) || defined(__SOFTBIOS) || defined(__GRM) || defined(__PWRCONS)) 579 #if LHDM || LINUX 580 #define GFX_IS_SKU(s, f) ((s)->SkuTable.f) 581 #define GFX_IS_WA(s, w) ((s)->WaTable.w) 582 #define GFX_WRITE_WA(x, y, z) ((x)->WaTable.y = z) 583 //No checking is done in the GFX_WRITE_SKU macro that z actually fits into y. 584 // It is up to the user to know the size of y and to pass in z accordingly. 585 #define GFX_WRITE_SKU(x, y, z) ((x)->SkuTable.y = z) 586 #else 587 #define GFX_IS_SKU(h, f) (((PHW_DEVICE_EXTENSION)(h))->pHWStatusPage->pSkuTable->f) 588 #define GFX_IS_WA(h, w) (((PHW_DEVICE_EXTENSION)(h))->pHWStatusPage->pWaTable->w) 589 #define GFX_WRITE_WA(x, y, z) (((HW_DEVICE_EXTENSION *)(x))->pHWStatusPage->pWaTable->y = z) 590 //No checking is done in the GFX_WRITE_SKU macro that z actually fits into y. 591 // It is up to the user to know the size of y and to pass in z accordingly. 592 #define GFX_WRITE_SKU(x, y, z) (((HW_DEVICE_EXTENSION *)(x))->pHWStatusPage->pSkuTable->y = z) 593 #endif // end LHDM 594 #else 595 #define GFX_IS_SKU(s, f) ((s)->SkuTable.f) 596 #define GFX_IS_WA(s, w) ((s)->WaTable.w) 597 #endif 598 #define GRAPHICS_IS_SKU(s, f) ((s)->f) 599 #define GRAPHICS_IS_WA(s, w) ((s)->w) 600 601 #endif //__SKU_WA_H__ 602