1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 /* $NoKeywords:$ */ 4 /** 5 * @file 6 * 7 * AMD CPU Execution Cache Allocation functions. 8 * 9 * Contains code for doing Execution Cache Allocation for ROM space 10 * 11 * @xrefitem bom "File Content Label" "Release Content" 12 * @e project: AGESA 13 * @e sub-project: CPU 14 * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $ 15 * 16 */ 17 /***************************************************************************** 18 * 19 * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc. 20 * All rights reserved. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions are met: 24 * * Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * * Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of 30 * its contributors may be used to endorse or promote products derived 31 * from this software without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY 37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 * 44 ***************************************************************************/ 45 46 #ifndef _CPU_CACHE_INIT_H_ 47 #define _CPU_CACHE_INIT_H_ 48 49 /*---------------------------------------------------------------------------- 50 * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) 51 * 52 *---------------------------------------------------------------------------- 53 */ 54 55 /*----------------------------------------------------------------------------- 56 * DEFINITIONS AND MACROS 57 * 58 *----------------------------------------------------------------------------- 59 */ 60 #define BSP_STACK_SIZE_64K 65536 61 #define BSP_STACK_SIZE_32K 32768 62 63 #define CORE0_STACK_SIZE 16384 64 #define CORE1_STACK_SIZE 4096 65 66 #define AMD_MTRR_FIX4K_BASE 0x268 67 #define AMD_MTRR_VARIABLE_BASE6 0x20C 68 #define AMD_MTRR_VARIABLE_BASE7 0x20E 69 70 #define WP_IO 0x0505050505050505ull 71 72 #define AGESA_CACHE_SIZE_REDUCED 1 73 #define AGESA_CACHE_REGIONS_ACROSS_1MB 2 74 #define AGESA_CACHE_REGIONS_ACROSS_4GB 3 75 #define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4 76 #define AGESA_CACHE_START_ADDRESS_LESS_D0000 5 77 #define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6 78 #define AGESA_DEALLOCATE_CACHE_REGIONS 7 79 80 /*---------------------------------------------------------------------------- 81 * TYPEDEFS, STRUCTURES, ENUMS 82 * 83 *---------------------------------------------------------------------------- 84 */ 85 /// Cache-As-Ram Executable region allocation modes 86 typedef enum { 87 LimitedByL2Size, ///< Execution space must be allocated from L2 88 InfiniteExe, ///< Family can support unlimited Execution space 89 MaxCarExeMode ///< Used as limit or bounds check 90 } CAR_EXE_MODE; 91 92 /// Cache Information 93 typedef struct { 94 IN UINT32 BspStackSize; ///< Stack size of BSP 95 IN UINT32 Core0StackSize; ///< Stack size of primary cores 96 IN UINT32 Core1StackSize; ///< Stack size of all non primary cores 97 IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size 98 IN UINT32 SharedMemSize; ///< Shared memory size 99 IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes 100 IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init. 101 IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings 102 IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space 103 } CACHE_INFO; 104 105 /// Merged memory region overlap type 106 typedef enum { 107 EmptySet, ///< One of the regions is zero length 108 Disjoint, ///< The two regions do not touch 109 Adjacent, ///< one region is next to the other, no gap 110 CommonEnd, ///< regions overlap with a common end point 111 Extending, ///< the 2nd region is extending the size of the 1st 112 Contained, ///< the 2nd region is wholely contained inside the 1st 113 CommonStartContained, ///< the 2nd region is contained in the 1st with a common start 114 Identity, ///< the two regions are the same 115 CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size 116 NotCombinable ///< the combined regions do not follow the cache block rules 117 } OVERLAP_TYPE; 118 119 /// Result of merging two memory regions for cache coverage 120 typedef struct { 121 IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions 122 IN OUT UINT32 MergedSize; ///< Size of the merged regions 123 OUT UINT32 OverlapAmount; ///< the size of the overlapping section 124 OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap 125 } MERGED_CACHE_REGION; 126 127 /*---------------------------------------------------------------------------- 128 * FUNCTIONS PROTOTYPE 129 * 130 *---------------------------------------------------------------------------- 131 */ 132 AGESA_STATUS 133 AllocateExecutionCache ( 134 IN AMD_CONFIG_PARAMS *StdHeader, 135 IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr 136 ); 137 138 #endif // _CPU_CACHE_INIT_H_ 139 140