1 /**
2 ******************************************************************************
3 * @file stm32l0xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 *** How to configure Interrupts using CORTEX HAL driver ***
17 ===========================================================
18 [..]
19 This section provides functions allowing to configure the NVIC interrupts (IRQ).
20 The Cortex M0+ exceptions are managed by CMSIS functions.
21 (#) Enable and Configure the priority of the selected IRQ Channels.
22 The priority can be 0..3.
23
24 -@- Lower priority values gives higher priority.
25 -@- Priority Order:
26 (#@) Lowest priority.
27 (#@) Lowest hardware priority (IRQn position).
28
29 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
30
31 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
32
33 [..]
34 *** How to configure Systick using CORTEX HAL driver ***
35 ========================================================
36 [..]
37 Setup SysTick Timer for time base.
38
39 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
40 is a CMSIS function that:
41 (++) Configures the SysTick Reload register with value passed as function parameter.
42 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
43 (++) Resets the SysTick Counter register.
44 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
45 (++) Enables the SysTick Interrupt.
46 (++) Starts the SysTick Counter.
47
48 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
49 HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
50 HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined
51 inside the stm32l0xx_hal_cortex.c file.
52
53 (+) You can change the SysTick IRQ priority by calling the
54 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
55 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
56
57 (+) To adjust the SysTick time base, use the following formula:
58
59 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
60 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
61 (++) Reload Value should not exceed 0xFFFFFF
62
63 @endverbatim
64 ******************************************************************************
65 * @attention
66 *
67 * <h2><center>© Copyright(c) 2016 STMicroelectronics.
68 * All rights reserved.</center></h2>
69 *
70 * This software component is licensed by ST under BSD 3-Clause license,
71 * the "License"; You may not use this file except in compliance with the
72 * License. You may obtain a copy of the License at:
73 * opensource.org/licenses/BSD-3-Clause
74 *
75 ******************************************************************************
76 */
77
78 /* Includes ------------------------------------------------------------------*/
79 #include "stm32l0xx_hal.h"
80
81 /** @addtogroup STM32L0xx_HAL_Driver
82 * @{
83 */
84
85 #ifdef HAL_CORTEX_MODULE_ENABLED
86
87 /** @addtogroup CORTEX
88 * @brief CORTEX HAL module driver
89 * @{
90 */
91
92 /* Private types -------------------------------------------------------------*/
93 /* Private variables ---------------------------------------------------------*/
94 /* Private constants ---------------------------------------------------------*/
95 /* Private macros ------------------------------------------------------------*/
96 /* Private functions ---------------------------------------------------------*/
97 /* Exported functions --------------------------------------------------------*/
98
99 /** @addtogroup CORTEX_Exported_Functions
100 * @{
101 */
102
103
104 /** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
105 * @brief Initialization and Configuration functions
106 *
107 @verbatim
108 ==============================================================================
109 ##### Initialization and Configuration functions #####
110 ==============================================================================
111 [..]
112 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
113 Systick functionalities
114
115 @endverbatim
116 * @{
117 */
118
119 /**
120 * @brief Sets the priority of an interrupt.
121 * @param IRQn External interrupt number .
122 * This parameter can be an enumerator of IRQn_Type enumeration
123 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
124 * @param PreemptPriority The pre-emption priority for the IRQn channel.
125 * This parameter can be a value between 0 and 3.
126 * A lower priority value indicates a higher priority
127 * @param SubPriority the subpriority level for the IRQ channel.
128 * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
129 * no subpriority supported in Cortex M0+ based products.
130 * @retval None
131 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)132 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
133 {
134 /* Check the parameters */
135 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
136 NVIC_SetPriority(IRQn,PreemptPriority);
137 }
138
139 /**
140 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
141 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
142 * function should be called before.
143 * @param IRQn External interrupt number .
144 * This parameter can be an enumerator of IRQn_Type enumeration
145 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
146 * @retval None
147 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)148 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
149 {
150 /* Check the parameters */
151 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
152
153 /* Enable interrupt */
154 NVIC_EnableIRQ(IRQn);
155 }
156
157 /**
158 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
159 * @param IRQn External interrupt number .
160 * This parameter can be an enumerator of IRQn_Type enumeration
161 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
162 * @retval None
163 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)164 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
165 {
166 /* Check the parameters */
167 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
168
169 /* Disable interrupt */
170 NVIC_DisableIRQ(IRQn);
171 }
172
173 /**
174 * @brief Initiate a system reset request to reset the MCU.
175 * @retval None
176 */
HAL_NVIC_SystemReset(void)177 void HAL_NVIC_SystemReset(void)
178 {
179 /* System Reset */
180 NVIC_SystemReset();
181 }
182
183 /**
184 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick)
185 * Counter is in free running mode to generate periodic interrupts.
186 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
187 * @retval status: - 0 Function succeeded.
188 * - 1 Function failed.
189 */
HAL_SYSTICK_Config(uint32_t TicksNumb)190 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
191 {
192 return SysTick_Config(TicksNumb);
193 }
194 /**
195 * @}
196 */
197
198 /** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
199 * @brief Cortex control functions
200 *
201 @verbatim
202 ==============================================================================
203 ##### Peripheral Control functions #####
204 ==============================================================================
205 [..]
206 This subsection provides a set of functions allowing to control the CORTEX
207 (NVIC, SYSTICK) functionalities.
208
209
210 @endverbatim
211 * @{
212 */
213
214
215 /**
216 * @brief Gets the priority of an interrupt.
217 * @param IRQn External interrupt number.
218 * This parameter can be an enumerator of IRQn_Type enumeration
219 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l0xxxx.h))
220 * @retval None
221 */
HAL_NVIC_GetPriority(IRQn_Type IRQn)222 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
223 {
224 /* Get priority for Cortex-M system or device specific interrupts */
225 return NVIC_GetPriority(IRQn);
226 }
227
228 /**
229 * @brief Sets Pending bit of an external interrupt.
230 * @param IRQn External interrupt number
231 * This parameter can be an enumerator of IRQn_Type enumeration
232 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
233 * @retval None
234 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)235 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
236 {
237 /* Set interrupt pending */
238 NVIC_SetPendingIRQ(IRQn);
239 }
240
241 /**
242 * @brief Get Pending Interrupt (read the pending register in the NVIC
243 * and return the pending bit for the specified interrupt).
244 * @param IRQn External interrupt number .
245 * This parameter can be an enumerator of IRQn_Type enumeration
246 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
247 * @retval status: - 0 Interrupt status is not pending.
248 * - 1 Interrupt status is pending.
249 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)250 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
251 {
252 /* Return 1 if pending else 0 */
253 return NVIC_GetPendingIRQ(IRQn);
254 }
255
256 /**
257 * @brief Clear the pending bit of an external interrupt.
258 * @param IRQn External interrupt number .
259 * This parameter can be an enumerator of IRQn_Type enumeration
260 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
261 * @retval None
262 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)263 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
264 {
265 /* Clear pending interrupt */
266 NVIC_ClearPendingIRQ(IRQn);
267 }
268
269
270 /**
271 * @brief Configure the SysTick clock source.
272 * @param CLKSource specifies the SysTick clock source.
273 * This parameter can be one of the following values:
274 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
275 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
276 * @retval None
277 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)278 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
279 {
280 /* Check the parameters */
281 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
282 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
283 {
284 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
285 }
286 else
287 {
288 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
289 }
290 }
291
292 /**
293 * @brief Handle SYSTICK interrupt request.
294 * @retval None
295 */
HAL_SYSTICK_IRQHandler(void)296 void HAL_SYSTICK_IRQHandler(void)
297 {
298 HAL_SYSTICK_Callback();
299 }
300
301 /**
302 * @brief SYSTICK callback.
303 * @retval None
304 */
HAL_SYSTICK_Callback(void)305 __weak void HAL_SYSTICK_Callback(void)
306 {
307 /* NOTE : This function should not be modified, when the callback is needed,
308 the HAL_SYSTICK_Callback could be implemented in the user file
309 */
310 }
311
312 #if (__MPU_PRESENT == 1U)
313 /**
314 * @brief Disable the MPU.
315 * @retval None
316 */
HAL_MPU_Disable(void)317 void HAL_MPU_Disable(void)
318 {
319
320 /*Data Memory Barrier setup */
321 __DMB();
322 /* Disable the MPU */
323 MPU->CTRL = 0;
324 }
325
326 /**
327 * @brief Enable the MPU.
328 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
329 * NMI, FAULTMASK and privileged access to the default memory
330 * This parameter can be one of the following values:
331 * @arg MPU_HFNMI_PRIVDEF_NONE
332 * @arg MPU_HARDFAULT_NMI
333 * @arg MPU_PRIVILEGED_DEFAULT
334 * @arg MPU_HFNMI_PRIVDEF
335 * @retval None
336 */
337
HAL_MPU_Enable(uint32_t MPU_Control)338 void HAL_MPU_Enable(uint32_t MPU_Control)
339 {
340 /* Enable the MPU */
341 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
342 /* Data Synchronization Barrier setup */
343 __DSB();
344 /* Instruction Synchronization Barrier setup */
345 __ISB();
346
347 }
348
349 /**
350 * @brief Initialize and configure the Region and the memory to be protected.
351 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
352 * the initialization and configuration information.
353 * @retval None
354 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)355 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
356 {
357 /* Check the parameters */
358 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
359 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
360
361 /* Set the Region number */
362 MPU->RNR = MPU_Init->Number;
363
364 if ((MPU_Init->Enable) == MPU_REGION_ENABLE)
365 {
366 /* Check the parameters */
367 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
368 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
369 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
370 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
371 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
372 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
373 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
374
375 /* Set the base adsress and set the 4 LSB to 0 */
376 MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U;
377
378 /* Fill the field RASR */
379 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
380 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
381 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
382 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
383 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
384 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
385 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
386 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
387 }
388 else
389 {
390 MPU->RBAR = 0x00U;
391 MPU->RASR = 0x00U;
392 }
393 }
394 #endif /* __MPU_PRESENT */
395
396
397 /**
398 * @}
399 */
400
401 /**
402 * @}
403 */
404
405 /**
406 * @}
407 */
408
409 #endif /* HAL_CORTEX_MODULE_ENABLED */
410 /**
411 * @}
412 */
413
414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
415
416