1 /*============================================================================== 2 Copyright(c) 2019 Intel Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files(the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and / or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included 12 in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 OTHER DEALINGS IN THE SOFTWARE. 21 ============================================================================*/ 22 23 24 #pragma once 25 #include "gfxmacro.h" 26 27 28 29 ////////////////////// Auxiliary Translation Table definitions////////////////////////////////////////// 30 //=========================================================================== 31 // typedef: 32 // GMM_AUXTTL3e 33 // 34 // Description: 35 // Struct for Auxiliary Translation-Table L3 entry 36 //-------------------------------------------------------------------------- 37 typedef union GMM_AUXTTL3e_REC 38 { 39 struct { 40 uint64_t Valid : 1; 41 uint64_t Reserved0 : 14; 42 uint64_t L2GfxAddr : 33; 43 uint64_t Reserved1 : 16; 44 }; 45 uint64_t Value; 46 } GMM_AUXTTL3e; 47 C_ASSERT(sizeof(GMM_AUXTTL3e) == 8); 48 49 // Get the L2GfxAddr bit field as a full L2 graphics address 50 #define GMM_FULL_GFXADDR_FROM_AUX_L3e_L2GFXADDR(L2GfxAddr) ((L2GfxAddr) << 16) 51 52 // Set the L2GfxAddr bit field given a full L2 graphics address 53 #define GMM_TO_AUX_L3e_L2GFXADDR(L2GfxAddress) ((L2GfxAddress) >> 16) 54 55 //=========================================================================== 56 // typedef: 57 // GMM_AUXTTL2e 58 // 59 // Description: 60 // Struct for Auxiliary Translation-Table L2 entry 61 //-------------------------------------------------------------------------- 62 typedef union GMM_AUXTTL2e_REC 63 { 64 struct 65 { 66 uint64_t Valid : 1; 67 uint64_t Reserved0 : 10; 68 uint64_t Reserved2 : 2; // used for MTL and above 69 uint64_t L1GfxAddr : 35; 70 uint64_t Reserved1 : 16; 71 }; 72 uint64_t Value; 73 } GMM_AUXTTL2e; 74 C_ASSERT(sizeof(GMM_AUXTTL2e) == 8); 75 76 // Get the L1GfxAddr bit field as a full L1 graphics address 77 #define GMM_FULL_GFXADDR_FROM_AUX_L2e_L1GFXADDR(L1GfxAddr) ((L1GfxAddr) << 16) 78 #define GMM_L1TABLE_ADDR_FROM_AUX_L2e_L1GFXADDR(L2e, Is1MBaligned) (Is1MBaligned ? (L2e.L1GfxAddr << 13 | L2e.Reserved2 << 11) : (L2e.L1GfxAddr << 13)) 79 80 // Set the L1GfxAddr bit field given a full L1 graphics address 81 #define GMM_TO_AUX_L2e_L1GFXADDR(L1GfxAddress) ((L1GfxAddress) >> 16) 82 #define GMM_TO_AUX_L2e_L1GFXADDR_2(GfxAddr, L2e, Is1MBaligned) { \ 83 L2e.L1GfxAddr = (GfxAddr >> 13); \ 84 L2e.Reserved2 = Is1MBaligned ? (GfxAddr >> 11) : 0;\ 85 } 86 #define GMM_GET_AUX_CCS_SIZE(Is1MBaligned) (Is1MBaligned? GMM_KBYTE(4): GMM_BYTES(256)) 87 88 typedef union GMM_AUXTTL1e_REC 89 { 90 struct 91 { 92 uint64_t Valid : 1; 93 uint64_t Mode : 2; //Compression ratio (128B compr ie 2:1 for RC, 256B compr ie 4:n compr for MC) 94 uint64_t Lossy : 1; //Lossy Compression 95 uint64_t Reserved0 : 2; 96 uint64_t Reserved2 : 2; //LSbs of 64B-aligned CCS chunk/cacheline address 97 uint64_t Reserved4 : 4; //LSbs of 256B-aligned CCS chunk/cacheline address 98 uint64_t GfxAddress : 36; //4K-aligned CCS chunk address 99 uint64_t Reserved1 : 4; 100 uint64_t TileMode : 2; //Ys = 0, Y=1, Reserved=(2-3) 101 uint64_t Depth : 3; //Packed/Planar bit-depth for MC; Bpp for RC 102 uint64_t LumaChroma : 1; //Planar Y=0 or Cr=1 103 uint64_t Format : 6; //Format encoding shared with Vivante/Internal CC/DEC units to recognize surafce formats 104 }; 105 uint64_t Value; 106 } GMM_AUXTTL1e; 107 C_ASSERT(sizeof(GMM_AUXTTL1e) == 8); 108 109 #define GMM_NO_TABLE ((GMM_GFX_ADDRESS)(-1L)) //common 110 111 #define GMM_INVALID_AUX_ENTRY ~__BIT(0) 112 113 #define GMM_AUX_L1e_SIZE (sizeof(GMM_AUXTTL1e)) 114 #define GMM_AUX_L2e_SIZE (sizeof(GMM_AUXTTL2e)) 115 #define GMM_AUX_L3e_SIZE (sizeof(GMM_AUXTTL3e)) 116 117 #define GMM_AUX_L1_LOW_BIT (14) 118 #define GMM_AUX_L1_HIGH_BIT (23) 119 #define GMM_AUX_L2_LOW_BIT (24) 120 #define GMM_AUX_L2_HIGH_BIT (35) 121 #define GMM_AUX_L3_LOW_BIT (36) 122 #define GMM_AUX_L3_HIGH_BIT (47) 123 124 //For perf, AuxTable granularity changed to 64K 125 #define WA16K(pGmmLibContext) (pGmmLibContext->GetWaTable().WaAuxTable16KGranular) 126 #define WA64K(pGmmLibContext) (pGmmLibContext->GetWaTable().WaAuxTable64KGranular) 127 128 // #L1 entries, i.e. 1024; 16K-granular ie 4 consequtive pages share Aux-cacheline; 129 // HW only tracks the distinct entries; 130 // Handle WA where HW chicken bit forces 64K-granularity 131 #define GMM_AUX_L1_SIZE(pGmmLibContext) ((1 << (GMM_AUX_L1_HIGH_BIT - GMM_AUX_L1_LOW_BIT + 1)) / (WA16K(pGmmLibContext) ? 1 : 4)) // MTL : L1 size is 256 entries, but only first 16 entries are used in HW (0-15) 132 #define GMM_AUX_L1_USABLESIZE(pGmmLibContext) ((1 << (GMM_AUX_L1_HIGH_BIT - GMM_AUX_L1_LOW_BIT + 1)) / (WA16K(pGmmLibContext) ? 1 : WA64K(pGmmLibContext) ? 4 : 64)) // MTL : L1 size is 256 entries, but only first 16 entries are used in HW (0-15) 133 #define GMM_AUX_L1_SIZE_DWORD(pGmmLibContext) (GFX_CEIL_DIV(GMM_AUX_L1_SIZE(pGmmLibContext), 32)) // MTL : 256/32 = 8 134 135 // #L2 entries, i.e. 4096 136 #define GMM_AUX_L2_SIZE (1 << (GMM_AUX_L2_HIGH_BIT - GMM_AUX_L2_LOW_BIT + 1)) 137 #define GMM_AUX_L2_SIZE_DWORD (GFX_CEIL_DIV(GMM_AUX_L2_SIZE, 32)) 138 139 // #L3 entries, i.e. 4096 140 #define GMM_AUX_L3_SIZE (1 << (GMM_AUX_L3_HIGH_BIT - GMM_AUX_L3_LOW_BIT + 1)) 141 142 #define GMM_AUX_L1_ENTRY_IDX(GfxAddress, pGmmLibContext) \ 143 ((((GfxAddress)&GFX_MASK_LARGE(GMM_AUX_L1_LOW_BIT, GMM_AUX_L1_HIGH_BIT)) >> \ 144 (uint64_t)GMM_AUX_L1_LOW_BIT) / \ 145 (WA16K(pGmmLibContext) ? 1 : WA64K(pGmmLibContext) ? 4 : 64)) // MTL and above: L1 size is 256 entries, but only first 16 entries are used in HW 146 147 #define GMM_AUX_L1_ENTRY_IDX_EXPORTED(GfxAddress,WA64KEx) \ 148 ((((GfxAddress) & GFX_MASK_LARGE(GMM_AUX_L1_LOW_BIT, GMM_AUX_L1_HIGH_BIT)) >> \ 149 (uint64_t)GMM_AUX_L1_LOW_BIT) / ((WA64KEx) ? 4 : 1)) 150 151 #define GMM_AUX_L1_ENTRY_IDX_EXPORTED_2(GfxAddress, WA64KEx, WA16KEx) \ 152 ((((GfxAddress)&GFX_MASK_LARGE(GMM_AUX_L1_LOW_BIT, GMM_AUX_L1_HIGH_BIT)) >> (uint64_t)GMM_AUX_L1_LOW_BIT) / (WA16KEx ? 1 : WA64KEx ? 4 : 64) ) 153 154 #define GMM_AUX_L2_ENTRY_IDX(GfxAddress) \ 155 (((GfxAddress) & GFX_MASK_LARGE(GMM_AUX_L2_LOW_BIT, GMM_AUX_L2_HIGH_BIT)) >> \ 156 (uint64_t)GMM_AUX_L2_LOW_BIT) 157 158 #define GMM_AUX_L3_ENTRY_IDX(GfxAddress) \ 159 (((GfxAddress) & GFX_MASK_LARGE(GMM_AUX_L3_LOW_BIT, GMM_AUX_L3_HIGH_BIT)) >> \ 160 (uint64_t)GMM_AUX_L3_LOW_BIT) 161 162 ////////////////////// Auxiliary Translation Table definitions end////////////////////////////////////////// 163