1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _PixelGen_SysBlock_defs_h 8 #define _PixelGen_SysBlock_defs_h 9 10 /* Parematers and User_Parameters for HSS */ 11 #define _PXG_PPC Ppc 12 #define _PXG_PIXEL_BITS PixelWidth 13 #define _PXG_MAX_NOF_SID MaxNofSids 14 #define _PXG_DATA_BITS DataWidth 15 #define _PXG_CNT_BITS CntWidth 16 #define _PXG_FIFODEPTH FifoDepth 17 #define _PXG_DBG Dbg_device_not_included 18 19 /* ID's and Address */ 20 #define _PXG_ADRRESS_ALIGN_REG 4 21 22 #define _PXG_COM_ENABLE_REG_IDX 0 23 #define _PXG_PRBS_RSTVAL_REG0_IDX 1 24 #define _PXG_PRBS_RSTVAL_REG1_IDX 2 25 #define _PXG_SYNG_SID_REG_IDX 3 26 #define _PXG_SYNG_FREE_RUN_REG_IDX 4 27 #define _PXG_SYNG_PAUSE_REG_IDX 5 28 #define _PXG_SYNG_NOF_FRAME_REG_IDX 6 29 #define _PXG_SYNG_NOF_PIXEL_REG_IDX 7 30 #define _PXG_SYNG_NOF_LINE_REG_IDX 8 31 #define _PXG_SYNG_HBLANK_CYC_REG_IDX 9 32 #define _PXG_SYNG_VBLANK_CYC_REG_IDX 10 33 #define _PXG_SYNG_STAT_HCNT_REG_IDX 11 34 #define _PXG_SYNG_STAT_VCNT_REG_IDX 12 35 #define _PXG_SYNG_STAT_FCNT_REG_IDX 13 36 #define _PXG_SYNG_STAT_DONE_REG_IDX 14 37 #define _PXG_TPG_MODE_REG_IDX 15 38 #define _PXG_TPG_HCNT_MASK_REG_IDX 16 39 #define _PXG_TPG_VCNT_MASK_REG_IDX 17 40 #define _PXG_TPG_XYCNT_MASK_REG_IDX 18 41 #define _PXG_TPG_HCNT_DELTA_REG_IDX 19 42 #define _PXG_TPG_VCNT_DELTA_REG_IDX 20 43 #define _PXG_TPG_R1_REG_IDX 21 44 #define _PXG_TPG_G1_REG_IDX 22 45 #define _PXG_TPG_B1_REG_IDX 23 46 #define _PXG_TPG_R2_REG_IDX 24 47 #define _PXG_TPG_G2_REG_IDX 25 48 #define _PXG_TPG_B2_REG_IDX 26 49 /* */ 50 #define _PXG_SYNG_PAUSE_CYCLES 0 51 /* Subblock ID's */ 52 #define _PXG_DISABLE_IDX 0 53 #define _PXG_PRBS_IDX 0 54 #define _PXG_TPG_IDX 1 55 #define _PXG_SYNG_IDX 2 56 #define _PXG_SMUX_IDX 3 57 /* Register Widths */ 58 #define _PXG_COM_ENABLE_REG_WIDTH 2 59 #define _PXG_COM_SRST_REG_WIDTH 4 60 #define _PXG_PRBS_RSTVAL_REG0_WIDTH 31 61 #define _PXG_PRBS_RSTVAL_REG1_WIDTH 31 62 63 #define _PXG_SYNG_SID_REG_WIDTH 3 64 65 #define _PXG_SYNG_FREE_RUN_REG_WIDTH 1 66 #define _PXG_SYNG_PAUSE_REG_WIDTH 1 67 /* 68 #define _PXG_SYNG_NOF_FRAME_REG_WIDTH <sync_gen_cnt_width> 69 #define _PXG_SYNG_NOF_PIXEL_REG_WIDTH <sync_gen_cnt_width> 70 #define _PXG_SYNG_NOF_LINE_REG_WIDTH <sync_gen_cnt_width> 71 #define _PXG_SYNG_HBLANK_CYC_REG_WIDTH <sync_gen_cnt_width> 72 #define _PXG_SYNG_VBLANK_CYC_REG_WIDTH <sync_gen_cnt_width> 73 #define _PXG_SYNG_STAT_HCNT_REG_WIDTH <sync_gen_cnt_width> 74 #define _PXG_SYNG_STAT_VCNT_REG_WIDTH <sync_gen_cnt_width> 75 #define _PXG_SYNG_STAT_FCNT_REG_WIDTH <sync_gen_cnt_width> 76 */ 77 #define _PXG_SYNG_STAT_DONE_REG_WIDTH 1 78 #define _PXG_TPG_MODE_REG_WIDTH 2 79 /* 80 #define _PXG_TPG_HCNT_MASK_REG_WIDTH <sync_gen_cnt_width> 81 #define _PXG_TPG_VCNT_MASK_REG_WIDTH <sync_gen_cnt_width> 82 #define _PXG_TPG_XYCNT_MASK_REG_WIDTH <pixle_width> 83 */ 84 #define _PXG_TPG_HCNT_DELTA_REG_WIDTH 4 85 #define _PXG_TPG_VCNT_DELTA_REG_WIDTH 4 86 /* 87 #define _PXG_TPG_R1_REG_WIDTH <pixle_width> 88 #define _PXG_TPG_G1_REG_WIDTH <pixle_width> 89 #define _PXG_TPG_B1_REG_WIDTH <pixle_width> 90 #define _PXG_TPG_R2_REG_WIDTH <pixle_width> 91 #define _PXG_TPG_G2_REG_WIDTH <pixle_width> 92 #define _PXG_TPG_B2_REG_WIDTH <pixle_width> 93 */ 94 #define _PXG_FIFO_DEPTH 2 95 /* MISC */ 96 #define _PXG_ENABLE_REG_VAL 1 97 #define _PXG_PRBS_ENABLE_REG_VAL 1 98 #define _PXG_TPG_ENABLE_REG_VAL 2 99 #define _PXG_SYNG_ENABLE_REG_VAL 4 100 #define _PXG_FIFO_ENABLE_REG_VAL 8 101 #define _PXG_PXL_BITS 14 102 #define _PXG_INVALID_FLAG 0xDEADBEEF 103 #define _PXG_CAFE_FLAG 0xCAFEBABE 104 105 #endif /* _PixelGen_SysBlock_defs_h */ 106