xref: /aosp_15_r20/external/mesa3d/src/amd/common/ac_descriptors.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  * Copyright 2024 Valve Corporation
4  *
5  * SPDX-License-Identifier: MIT
6  */
7 
8 #ifndef AC_DESCRIPTORS_H
9 #define AC_DESCRIPTORS_H
10 
11 #include "ac_gpu_info.h"
12 #include "ac_surface.h"
13 
14 #include "util/format/u_format.h"
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 unsigned
21 ac_map_swizzle(unsigned swizzle);
22 
23 struct ac_sampler_state {
24    unsigned address_mode_u : 3;
25    unsigned address_mode_v : 3;
26    unsigned address_mode_w : 3;
27    unsigned max_aniso_ratio : 3;
28    unsigned depth_compare_func : 3;
29    unsigned unnormalized_coords : 1;
30    unsigned cube_wrap : 1;
31    unsigned trunc_coord : 1;
32    unsigned filter_mode : 2;
33    unsigned mag_filter : 2;
34    unsigned min_filter : 2;
35    unsigned mip_filter : 2;
36    unsigned aniso_single_level : 1;
37    unsigned border_color_type : 2;
38    unsigned border_color_ptr : 12;
39    float min_lod;
40    float max_lod;
41    float lod_bias;
42 };
43 
44 void
45 ac_build_sampler_descriptor(const enum amd_gfx_level gfx_level,
46                             const struct ac_sampler_state *state,
47                             uint32_t desc[4]);
48 
49 struct ac_fmask_state {
50    const struct radeon_surf *surf;
51    uint64_t va;
52    uint32_t width : 16;
53    uint32_t height : 16;
54    uint32_t depth : 14;
55    uint32_t type : 4;
56    uint32_t first_layer : 14;
57    uint32_t last_layer : 13;
58 
59    uint32_t num_samples : 5;
60    uint32_t num_storage_samples : 4;
61    uint32_t tc_compat_cmask : 1;
62 };
63 
64 void
65 ac_build_fmask_descriptor(const enum amd_gfx_level gfx_level,
66                           const struct ac_fmask_state *state,
67                           uint32_t desc[8]);
68 
69 struct ac_texture_state {
70    struct radeon_surf *surf;
71    enum pipe_format format;
72    enum pipe_format img_format;
73    uint32_t width : 17;
74    uint32_t height : 17;
75    uint32_t depth : 15;
76    uint32_t type : 4;
77    enum pipe_swizzle swizzle[4];
78    uint32_t num_samples : 5;
79    uint32_t num_storage_samples : 5;
80    uint32_t first_level : 4;
81    uint32_t last_level : 5;
82    uint32_t num_levels : 6;
83    uint32_t first_layer : 14;
84    uint32_t last_layer : 13;
85    float min_lod;
86 
87    struct {
88       uint32_t uav3d : 1;
89       uint32_t upgraded_depth : 1;
90    } gfx10;
91 
92    struct {
93       const struct ac_surf_nbc_view *nbc_view;
94    } gfx9;
95 
96    uint32_t dcc_enabled : 1;
97    uint32_t tc_compat_htile_enabled : 1;
98    uint32_t aniso_single_level : 1;
99 };
100 
101 void
102 ac_build_texture_descriptor(const struct radeon_info *info,
103                             const struct ac_texture_state *state,
104                             uint32_t desc[8]);
105 
106 uint32_t
107 ac_tile_mode_index(const struct radeon_surf *surf,
108                    unsigned level,
109                    bool stencil);
110 
111 struct ac_mutable_tex_state {
112    const struct radeon_surf *surf;
113    uint64_t va;
114 
115    struct {
116       uint32_t write_compress_enable : 1;
117       uint32_t iterate_256 : 1;
118    } gfx10;
119 
120    struct {
121       const struct ac_surf_nbc_view *nbc_view;
122    } gfx9;
123 
124    struct {
125       const struct legacy_surf_level *base_level_info;
126       uint32_t base_level;
127       uint32_t block_width;
128    } gfx6;
129 
130    uint32_t is_stencil : 1;
131    uint32_t dcc_enabled : 1;
132    uint32_t tc_compat_htile_enabled : 1;
133 };
134 
135 void
136 ac_set_mutable_tex_desc_fields(const struct radeon_info *info,
137                                const struct ac_mutable_tex_state *state,
138                                uint32_t desc[8]);
139 
140 struct ac_buffer_state {
141    uint64_t va;
142    uint32_t size;
143    enum pipe_format format;
144    enum pipe_swizzle swizzle[4];
145    uint32_t stride;
146    uint32_t swizzle_enable : 2;
147    uint32_t element_size : 2;
148    uint32_t index_stride : 2;
149    uint32_t add_tid : 1;
150    uint32_t gfx10_oob_select : 2;
151 };
152 
153 void
154 ac_set_buf_desc_word3(const enum amd_gfx_level gfx_level,
155                       const struct ac_buffer_state *state,
156                       uint32_t *rsrc_word3);
157 
158 void
159 ac_build_buffer_descriptor(const enum amd_gfx_level gfx_level,
160                            const struct ac_buffer_state *state,
161                            uint32_t desc[4]);
162 
163 void
164 ac_build_raw_buffer_descriptor(const enum amd_gfx_level gfx_level,
165                                uint64_t va,
166                                uint32_t size,
167                                uint32_t desc[4]);
168 
169 void
170 ac_build_attr_ring_descriptor(const enum amd_gfx_level gfx_level,
171                               uint64_t va,
172                               uint32_t size,
173                               uint32_t stride,
174                               uint32_t desc[4]);
175 
176 struct ac_ds_state {
177    const struct radeon_surf *surf;
178    uint64_t va;
179    enum pipe_format format;
180    uint32_t width : 17;
181    uint32_t height : 17;
182    uint32_t level : 5;
183    uint32_t num_levels : 6;
184    uint32_t num_samples : 5;
185    uint32_t first_layer : 14;
186    uint32_t last_layer : 14;
187 
188    uint32_t allow_expclear : 1;
189    uint32_t stencil_only : 1;
190    uint32_t z_read_only : 1;
191    uint32_t stencil_read_only : 1;
192 
193    uint32_t htile_enabled : 1;
194    uint32_t htile_stencil_disabled : 1;
195    uint32_t vrs_enabled : 1;
196 };
197 
198 struct ac_ds_surface {
199    uint64_t db_depth_base;
200    uint64_t db_stencil_base;
201    uint32_t db_depth_view;
202    uint32_t db_depth_size;
203    uint32_t db_z_info;
204    uint32_t db_stencil_info;
205 
206    union {
207       struct {
208          uint64_t hiz_base;
209          uint32_t hiz_info;
210          uint32_t hiz_size_xy;
211          uint64_t his_base;
212          uint32_t his_info;
213          uint32_t his_size_xy;
214          uint32_t db_depth_view1;
215       } gfx12;
216 
217       struct {
218          uint64_t db_htile_data_base;
219          uint32_t db_depth_info;
220          uint32_t db_depth_slice;
221          uint32_t db_htile_surface;
222          uint32_t db_z_info2;
223          uint32_t db_stencil_info2;
224       } gfx6;
225    } u;
226 };
227 
228 void
229 ac_init_ds_surface(const struct radeon_info *info, const struct ac_ds_state *state, struct ac_ds_surface *ds);
230 
231 struct ac_mutable_ds_state {
232    const struct ac_ds_surface *ds; /* original DS surface */
233    enum pipe_format format;
234    uint32_t tc_compat_htile_enabled : 1;
235    uint32_t zrange_precision : 1;
236    uint32_t no_d16_compression : 1;
237 };
238 
239 void
240 ac_set_mutable_ds_surface_fields(const struct radeon_info *info, const struct ac_mutable_ds_state *state,
241                                  struct ac_ds_surface *ds);
242 
243 struct ac_cb_state {
244    const struct radeon_surf *surf;
245    enum pipe_format format;
246    uint32_t width : 17;
247    uint32_t height : 17;
248    uint32_t first_layer : 14;
249    uint32_t last_layer : 14;
250    uint32_t num_layers : 14;
251    uint32_t num_samples : 5;
252    uint32_t num_storage_samples : 5;
253    uint32_t base_level : 5;
254    uint32_t num_levels : 6;
255 
256    struct {
257       struct ac_surf_nbc_view *nbc_view;
258    } gfx10;
259 };
260 
261 struct ac_cb_surface {
262    uint32_t cb_color_info;
263    uint32_t cb_color_view;
264    uint32_t cb_color_view2;
265    uint32_t cb_color_attrib;
266    uint32_t cb_color_attrib2; /* GFX9+ */
267    uint32_t cb_color_attrib3; /* GFX10+ */
268    uint32_t cb_dcc_control;
269    uint64_t cb_color_base;
270    uint64_t cb_color_cmask;
271    uint64_t cb_color_fmask;
272    uint64_t cb_dcc_base;
273    uint32_t cb_color_slice;
274    uint32_t cb_color_cmask_slice;
275    uint32_t cb_color_fmask_slice;
276    union {
277       uint32_t cb_color_pitch; /* GFX6-GFX8 */
278       uint32_t cb_mrt_epitch;  /* GFX9+ */
279    };
280 };
281 
282 void
283 ac_init_cb_surface(const struct radeon_info *info, const struct ac_cb_state *state, struct ac_cb_surface *cb);
284 
285 struct ac_mutable_cb_state {
286    const struct radeon_surf *surf;
287    const struct ac_cb_surface *cb; /* original CB surface */
288    uint64_t va;
289 
290    uint32_t base_level : 5;
291    uint32_t num_samples : 5;
292 
293    uint32_t fmask_enabled : 1;
294    uint32_t cmask_enabled : 1;
295    uint32_t fast_clear_enabled : 1;
296    uint32_t tc_compat_cmask_enabled : 1;
297    uint32_t dcc_enabled : 1;
298 
299    struct {
300       struct ac_surf_nbc_view *nbc_view;
301    } gfx10;
302 };
303 
304 void
305 ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac_mutable_cb_state *state,
306                                  struct ac_cb_surface *cb);
307 
308 #ifdef __cplusplus
309 }
310 #endif
311 
312 #endif
313