1 /*
2 * Copyright © 2018 Valve Corporation
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #ifndef ACO_INSTRUCTION_SELECTION_H
8 #define ACO_INSTRUCTION_SELECTION_H
9
10 #include "aco_ir.h"
11
12 #include "nir.h"
13
14 #include <array>
15 #include <unordered_map>
16 #include <vector>
17
18 namespace aco {
19
20 enum aco_color_output_type {
21 ACO_TYPE_ANY32,
22 ACO_TYPE_FLOAT16,
23 ACO_TYPE_INT16,
24 ACO_TYPE_UINT16,
25 };
26
27 struct shader_io_state {
28 uint8_t mask[VARYING_SLOT_MAX];
29 Temp temps[VARYING_SLOT_MAX * 4u];
30
shader_io_stateshader_io_state31 shader_io_state()
32 {
33 memset(mask, 0, sizeof(mask));
34 std::fill_n(temps, VARYING_SLOT_MAX * 4u, Temp(0, RegClass::v1));
35 }
36 };
37
38 struct exec_info {
39 /* Set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
40 bool potentially_empty_discard = false;
41 uint16_t potentially_empty_break_depth = UINT16_MAX;
42 /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth,
43 * parent_if.is_divergent==false and parent_loop.has_divergent_continue==false. Also set to
44 * false if loop_nest_depth<exec_potentially_empty_break_depth. */
45 bool potentially_empty_break = false;
46 uint16_t potentially_empty_continue_depth = UINT16_MAX;
47 /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
48 * and parent_if.is_divergent==false. */
49 bool potentially_empty_continue = false;
50
combineexec_info51 void combine(struct exec_info& other)
52 {
53 potentially_empty_discard |= other.potentially_empty_discard;
54 potentially_empty_break_depth =
55 std::min(potentially_empty_break_depth, other.potentially_empty_break_depth);
56 potentially_empty_break |= other.potentially_empty_break;
57 potentially_empty_continue_depth =
58 std::min(potentially_empty_continue_depth, other.potentially_empty_continue_depth);
59 potentially_empty_continue |= other.potentially_empty_continue;
60 }
61 };
62
63 struct isel_context {
64 const struct aco_compiler_options* options;
65 const struct ac_shader_args* args;
66 Program* program;
67 nir_shader* shader;
68 uint32_t constant_data_offset;
69 Block* block;
70 uint32_t first_temp_id;
71 std::unordered_map<unsigned, std::array<Temp, NIR_MAX_VEC_COMPONENTS>> allocated_vec;
72 std::vector<Temp> unended_linear_vgprs;
73 Stage stage;
74 struct {
75 bool has_branch;
76 struct {
77 unsigned header_idx;
78 Block* exit;
79 bool has_divergent_continue = false;
80 bool has_divergent_branch = false;
81 } parent_loop;
82 struct {
83 bool is_divergent = false;
84 } parent_if;
85 bool had_divergent_discard = false;
86
87 struct exec_info exec;
88 } cf_info;
89
90 /* NIR range analysis. */
91 struct hash_table* range_ht;
92 nir_unsigned_upper_bound_config ub_config;
93
94 Temp arg_temps[AC_MAX_ARGS];
95 Operand workgroup_id[3];
96 Temp ttmp8;
97
98 /* tessellation information */
99 uint64_t tcs_temp_only_inputs;
100 bool tcs_in_out_eq = false;
101
102 /* Fragment color output information */
103 uint16_t output_color_types;
104
105 /* I/O information */
106 shader_io_state inputs;
107 shader_io_state outputs;
108
109 /* WQM information */
110 uint32_t wqm_block_idx;
111 uint32_t wqm_instruction_idx;
112
113 BITSET_DECLARE(output_args, AC_MAX_ARGS);
114 };
115
116 inline Temp
get_arg(isel_context * ctx,struct ac_arg arg)117 get_arg(isel_context* ctx, struct ac_arg arg)
118 {
119 assert(arg.used);
120 return ctx->arg_temps[arg.arg_index];
121 }
122
123 void init_context(isel_context* ctx, nir_shader* shader);
124 void cleanup_context(isel_context* ctx);
125
126 isel_context setup_isel_context(Program* program, unsigned shader_count,
127 struct nir_shader* const* shaders, ac_shader_config* config,
128 const struct aco_compiler_options* options,
129 const struct aco_shader_info* info,
130 const struct ac_shader_args* args,
131 SWStage sw_stage = SWStage::None);
132
133 } // namespace aco
134
135 #endif /* ACO_INSTRUCTION_SELECTION_H */
136