1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 **************************************************************************************************** 11 * @file addrinterface.h 12 * @brief Contains the addrlib interfaces declaration and parameter defines 13 **************************************************************************************************** 14 */ 15 #ifndef __ADDR_INTERFACE_H__ 16 #define __ADDR_INTERFACE_H__ 17 18 // Includes should be before extern "C" 19 #include "addrtypes.h" 20 21 #if defined(__cplusplus) 22 extern "C" 23 { 24 #endif 25 26 #define ADDRLIB_VERSION_MAJOR 9 27 #define ADDRLIB_VERSION_MINOR 11 28 #define ADDRLIB_MAKE_VERSION(major, minor) ((major << 16) | minor) 29 #define ADDRLIB_VERSION ADDRLIB_MAKE_VERSION(ADDRLIB_VERSION_MAJOR, ADDRLIB_VERSION_MINOR) 30 31 /// Virtually all interface functions need ADDR_HANDLE as first parameter 32 typedef VOID* ADDR_HANDLE; 33 34 /// Client handle used in callbacks 35 typedef VOID* ADDR_CLIENT_HANDLE; 36 37 typedef struct _ADDR_EXTENT3D 38 { 39 UINT_32 width; 40 UINT_32 height; 41 UINT_32 depth; // also slices for 2D images 42 } ADDR_EXTENT3D; 43 44 /** 45 * ///////////////////////////////////////////////////////////////////////////////////////////////// 46 * // Callback functions 47 * ///////////////////////////////////////////////////////////////////////////////////////////////// 48 * typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 49 * const ADDR_ALLOCSYSMEM_INPUT* pInput); 50 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 51 * VOID* pVirtAddr); 52 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 53 * const ADDR_DEBUGPRINT_INPUT* pInput); 54 * 55 **/ 56 /** 57 * ///////////////////////////////////////////////////////////////////////////////////////////////// 58 * // Create/Destroy/Config functions 59 * ///////////////////////////////////////////////////////////////////////////////////////////////// 60 * AddrCreate() 61 * AddrDestroy() 62 * 63 * ///////////////////////////////////////////////////////////////////////////////////////////////// 64 * // Surface functions 65 * ///////////////////////////////////////////////////////////////////////////////////////////////// 66 * AddrComputeSurfaceInfo() 67 * AddrComputeSurfaceAddrFromCoord() 68 * AddrComputeSurfaceCoordFromAddr() 69 * 70 * ///////////////////////////////////////////////////////////////////////////////////////////////// 71 * // HTile functions 72 * ///////////////////////////////////////////////////////////////////////////////////////////////// 73 * AddrComputeHtileInfo() 74 * AddrComputeHtileAddrFromCoord() 75 * AddrComputeHtileCoordFromAddr() 76 * 77 * ///////////////////////////////////////////////////////////////////////////////////////////////// 78 * // C-mask functions 79 * ///////////////////////////////////////////////////////////////////////////////////////////////// 80 * AddrComputeCmaskInfo() 81 * AddrComputeCmaskAddrFromCoord() 82 * AddrComputeCmaskCoordFromAddr() 83 * 84 * ///////////////////////////////////////////////////////////////////////////////////////////////// 85 * // F-mask functions 86 * ///////////////////////////////////////////////////////////////////////////////////////////////// 87 * AddrComputeFmaskInfo() 88 * AddrComputeFmaskAddrFromCoord() 89 * AddrComputeFmaskCoordFromAddr() 90 * 91 **/ 92 /** 93 * ///////////////////////////////////////////////////////////////////////////////////////////////// 94 * // Element/Utility functions 95 * ///////////////////////////////////////////////////////////////////////////////////////////////// 96 * ElemFlt32ToDepthPixel() 97 * ElemFlt32ToColorPixel() 98 **/ 99 /** 100 * AddrExtractBankPipeSwizzle() 101 * AddrCombineBankPipeSwizzle() 102 * AddrComputeSliceSwizzle() 103 * AddrConvertTileInfoToHW() 104 * AddrConvertTileIndex() 105 * AddrConvertTileIndex1() 106 * AddrGetTileIndex() 107 * AddrComputeBaseSwizzle() 108 * AddrUseTileIndex() 109 * AddrUseCombinedSwizzle() 110 * 111 **/ 112 113 //////////////////////////////////////////////////////////////////////////////////////////////////// 114 // Callback functions 115 //////////////////////////////////////////////////////////////////////////////////////////////////// 116 117 /** 118 **************************************************************************************************** 119 * @brief channel setting structure 120 **************************************************************************************************** 121 */ 122 typedef union _ADDR_CHANNEL_SETTING 123 { 124 struct 125 { 126 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid 127 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel, 3 for MSAA sample index 128 UINT_8 index : 5; ///< Channel index 129 }; 130 UINT_8 value; ///< Value 131 } ADDR_CHANNEL_SETTING; 132 133 /** 134 **************************************************************************************************** 135 * @brief address equation key structure 136 **************************************************************************************************** 137 */ 138 typedef union _ADDR_EQUATION_KEY 139 { 140 struct 141 { 142 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel 143 UINT_32 tileMode : 5; ///< Tile mode 144 UINT_32 microTileType : 3; ///< Micro tile type 145 UINT_32 pipeConfig : 5; ///< pipe config 146 UINT_32 numBanksLog2 : 3; ///< Number of banks log2 147 UINT_32 bankWidth : 4; ///< Bank width 148 UINT_32 bankHeight : 4; ///< Bank height 149 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio 150 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt 151 UINT_32 reserved : 1; ///< Reserved bit 152 } fields; 153 UINT_32 value; 154 } ADDR_EQUATION_KEY; 155 156 /** 157 **************************************************************************************************** 158 * @brief address equation structure 159 **************************************************************************************************** 160 */ 161 #define ADDR_MAX_LEGACY_EQUATION_COMP 3u 162 #define ADDR_MAX_EQUATION_COMP 5u 163 #define ADDR_MAX_EQUATION_BIT 20u 164 165 // Invalid equation index 166 #define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF 167 168 typedef struct _ADDR_EQUATION 169 { 170 union 171 { 172 struct { 173 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting 174 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting 175 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting 176 ADDR_CHANNEL_SETTING xor3[ADDR_MAX_EQUATION_BIT]; ///< xor3 setting 177 ADDR_CHANNEL_SETTING xor4[ADDR_MAX_EQUATION_BIT]; ///< xor4 setting 178 }; 179 ///< Components showing the sources of each bit; each bit is result of addr ^ xor ^ xor2... 180 ADDR_CHANNEL_SETTING comps[ADDR_MAX_EQUATION_COMP][ADDR_MAX_EQUATION_BIT]; 181 }; 182 UINT_32 numBits; ///< The number of bits in equation 183 UINT_32 numBitComponents; ///< The max number of channels contributing to a bit 184 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being 185 ///< stacked vertically prior to swizzling 186 } ADDR_EQUATION; 187 188 189 /** 190 **************************************************************************************************** 191 * @brief Alloc system memory flags. 192 * @note These flags are reserved for future use and if flags are added will minimize the impact 193 * of the client. 194 **************************************************************************************************** 195 */ 196 typedef union _ADDR_ALLOCSYSMEM_FLAGS 197 { 198 struct 199 { 200 UINT_32 reserved : 32; ///< Reserved for future use. 201 } fields; 202 UINT_32 value; 203 204 } ADDR_ALLOCSYSMEM_FLAGS; 205 206 /** 207 **************************************************************************************************** 208 * @brief Alloc system memory input structure 209 **************************************************************************************************** 210 */ 211 typedef struct _ADDR_ALLOCSYSMEM_INPUT 212 { 213 UINT_32 size; ///< Size of this structure in bytes 214 215 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags. 216 UINT_32 sizeInBytes; ///< System memory allocation size in bytes. 217 ADDR_CLIENT_HANDLE hClient; ///< Client handle 218 } ADDR_ALLOCSYSMEM_INPUT; 219 220 /** 221 **************************************************************************************************** 222 * ADDR_ALLOCSYSMEM 223 * @brief 224 * Allocate system memory callback function. Returns valid pointer on success. 225 **************************************************************************************************** 226 */ 227 typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 228 const ADDR_ALLOCSYSMEM_INPUT* pInput); 229 230 /** 231 **************************************************************************************************** 232 * @brief Free system memory input structure 233 **************************************************************************************************** 234 */ 235 typedef struct _ADDR_FREESYSMEM_INPUT 236 { 237 UINT_32 size; ///< Size of this structure in bytes 238 239 VOID* pVirtAddr; ///< Virtual address 240 ADDR_CLIENT_HANDLE hClient; ///< Client handle 241 } ADDR_FREESYSMEM_INPUT; 242 243 /** 244 **************************************************************************************************** 245 * ADDR_FREESYSMEM 246 * @brief 247 * Free system memory callback function. 248 * Returns ADDR_OK on success. 249 **************************************************************************************************** 250 */ 251 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 252 const ADDR_FREESYSMEM_INPUT* pInput); 253 254 /** 255 **************************************************************************************************** 256 * @brief Print debug message input structure 257 **************************************************************************************************** 258 */ 259 typedef struct _ADDR_DEBUGPRINT_INPUT 260 { 261 UINT_32 size; ///< Size of this structure in bytes 262 263 CHAR* pDebugString; ///< Debug print string 264 va_list ap; ///< Variable argument list 265 ADDR_CLIENT_HANDLE hClient; ///< Client handle 266 } ADDR_DEBUGPRINT_INPUT; 267 268 /** 269 **************************************************************************************************** 270 * ADDR_DEBUGPRINT 271 * @brief 272 * Print debug message callback function. 273 * Returns ADDR_OK on success. 274 **************************************************************************************************** 275 */ 276 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 277 const ADDR_DEBUGPRINT_INPUT* pInput); 278 279 /** 280 **************************************************************************************************** 281 * ADDR_CALLBACKS 282 * 283 * @brief 284 * Address Library needs client to provide system memory alloc/free routines. 285 **************************************************************************************************** 286 */ 287 typedef struct _ADDR_CALLBACKS 288 { 289 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory 290 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory 291 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message 292 } ADDR_CALLBACKS; 293 294 //////////////////////////////////////////////////////////////////////////////////////////////////// 295 // Create/Destroy functions 296 //////////////////////////////////////////////////////////////////////////////////////////////////// 297 298 /** 299 **************************************************************************************************** 300 * ADDR_CREATE_FLAGS 301 * 302 * @brief 303 * This structure is used to pass some setup in creation of AddrLib 304 * @note 305 **************************************************************************************************** 306 */ 307 typedef union _ADDR_CREATE_FLAGS 308 { 309 struct 310 { 311 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off 312 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and 313 /// output structure 314 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid 315 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle 316 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level 317 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment 318 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize 319 UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility 320 UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2 321 UINT_32 enableAltTiling : 1; ///< Enable alt tile mode 322 UINT_32 reserved : 22; ///< Reserved bits for future use 323 }; 324 325 UINT_32 value; 326 } ADDR_CREATE_FLAGS; 327 328 /** 329 **************************************************************************************************** 330 * ADDR_REGISTER_VALUE 331 * 332 * @brief 333 * Data from registers to setup AddrLib global data, used in AddrCreate 334 **************************************************************************************************** 335 */ 336 typedef struct _ADDR_REGISTER_VALUE 337 { 338 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value. 339 /// For R6xx/R7xx, use GB_TILING_CONFIG. 340 /// But they can be treated as the same. 341 /// if this value is 0, use chip to set default value 342 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled. 343 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE 344 345 /// R800 registers----------------------------------------------- 346 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK 347 /// No enums for this value in h/w header files 348 /// 0: 4 349 /// 1: 8 350 /// 2: 16 351 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK 352 /// 0: 1 353 /// 1: 2 354 /// SI (R1000) registers----------------------------------------- 355 const UINT_32* pTileConfig; ///< Global tile setting tables 356 UINT_32 noOfEntries; ///< Number of entries in pTileConfig 357 358 ///< CI registers------------------------------------------------- 359 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table 360 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig 361 } ADDR_REGISTER_VALUE; 362 363 /** 364 **************************************************************************************************** 365 * ADDR_CREATE_INPUT 366 * 367 * @brief 368 * Parameters use to create an AddrLib Object. Caller must provide all fields. 369 * 370 **************************************************************************************************** 371 */ 372 typedef struct _ADDR_CREATE_INPUT 373 { 374 UINT_32 size; ///< Size of this structure in bytes 375 376 UINT_32 chipEngine; ///< Chip Engine 377 UINT_32 chipFamily; ///< Chip Family 378 UINT_32 chipRevision; ///< Chip Revision 379 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print 380 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib 381 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data 382 ADDR_CLIENT_HANDLE hClient; ///< Client handle 383 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels 384 } ADDR_CREATE_INPUT; 385 386 /** 387 **************************************************************************************************** 388 * ADDR_CREATEINFO_OUTPUT 389 * 390 * @brief 391 * Return AddrLib handle to client driver 392 * 393 **************************************************************************************************** 394 */ 395 typedef struct _ADDR_CREATE_OUTPUT 396 { 397 UINT_32 size; ///< Size of this structure in bytes 398 399 ADDR_HANDLE hLib; ///< Address lib handle 400 401 UINT_32 numEquations; ///< Number of equations in the table 402 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table 403 } ADDR_CREATE_OUTPUT; 404 405 /** 406 **************************************************************************************************** 407 * AddrCreate 408 * 409 * @brief 410 * Create AddrLib object, must be called before any interface calls 411 * 412 * @return 413 * ADDR_OK if successful 414 **************************************************************************************************** 415 */ 416 ADDR_E_RETURNCODE ADDR_API AddrCreate( 417 const ADDR_CREATE_INPUT* pAddrCreateIn, 418 ADDR_CREATE_OUTPUT* pAddrCreateOut); 419 420 421 422 /** 423 **************************************************************************************************** 424 * AddrDestroy 425 * 426 * @brief 427 * Destroy AddrLib object, must be called to free internally allocated resources. 428 * 429 * @return 430 * ADDR_OK if successful 431 **************************************************************************************************** 432 */ 433 ADDR_E_RETURNCODE ADDR_API AddrDestroy( 434 ADDR_HANDLE hLib); 435 436 437 //////////////////////////////////////////////////////////////////////////////////////////////////// 438 // Surface functions 439 //////////////////////////////////////////////////////////////////////////////////////////////////// 440 441 /** 442 **************************************************************************************************** 443 * @brief 444 * Bank/tiling parameters. On function input, these can be set as desired or 445 * left 0 for AddrLib to calculate/default. On function output, these are the actual 446 * parameters used. 447 * @note 448 * Valid bankWidth/bankHeight value: 449 * 1,2,4,8. They are factors instead of pixels or bytes. 450 * 451 * The bank number remains constant across each row of the 452 * macro tile as each pipe is selected, so the number of 453 * tiles in the x direction with the same bank number will 454 * be bank_width * num_pipes. 455 **************************************************************************************************** 456 */ 457 typedef struct _ADDR_TILEINFO 458 { 459 /// Any of these parameters can be set to 0 to use the HW default. 460 UINT_32 banks; ///< Number of banks, numerical value 461 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank 462 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank 463 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1 464 UINT_32 tileSplitBytes; ///< Tile split size, in bytes 465 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1 466 } ADDR_TILEINFO; 467 468 // Create a define to avoid client change. The removal of R800 is because we plan to implement SI 469 // within 800 HWL - An AddrPipeCfg is added in above data structure 470 typedef ADDR_TILEINFO ADDR_R800_TILEINFO; 471 472 /** 473 **************************************************************************************************** 474 * @brief 475 * Information needed by quad buffer stereo support 476 **************************************************************************************************** 477 */ 478 typedef struct _ADDR_QBSTEREOINFO 479 { 480 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye 481 UINT_32 rightOffset; ///< Offset (in bytes) to right eye 482 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes 483 } ADDR_QBSTEREOINFO; 484 485 /** 486 **************************************************************************************************** 487 * ADDR_SURFACE_FLAGS 488 * 489 * @brief 490 * Surface flags 491 **************************************************************************************************** 492 */ 493 typedef union _ADDR_SURFACE_FLAGS 494 { 495 struct 496 { 497 UINT_32 color : 1; ///< Flag indicates this is a color buffer 498 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer 499 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer 500 UINT_32 texture : 1; ///< Flag indicates this is a texture 501 UINT_32 cube : 1; ///< Flag indicates this is a cubemap 502 UINT_32 volume : 1; ///< Flag indicates this is a volume texture 503 UINT_32 fmask : 1; ///< Flag indicates this is an fmask 504 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays 505 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed 506 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface 507 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil 508 UINT_32 display : 1; ///< Flag indicates this should match display controller req. 509 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space 510 /// i.e. save some memory but may lose performance 511 UINT_32 prt : 1; ///< Flag for partially resident texture 512 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 513 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) 514 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 515 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 516 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce 517 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear 518 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that 519 /// dcc can't be enabled if pipe config of tile mode 520 /// is different from that of ASIC, this flag 521 /// is address lib internal flag, client should ignore it 522 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. 523 /// This flag indicates we need to follow the 524 /// alignment with CZ families or other ASICs under 525 /// PX configuration + CZ. 526 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split 527 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear 528 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible. 529 /// This flag indicates we need to override tile 530 /// mode to PRT_* tile mode to disable slice rotation, 531 /// which is needed by swizzle pattern equation. 532 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. 533 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type 534 UINT_32 minimizeAlignment : 1; ///< Minimize alignment 535 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode 536 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface 537 /// to make sure they share same tile config parameters 538 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade 539 UINT_32 reserved : 1; ///< Reserved bits 540 }; 541 542 UINT_32 value; 543 } ADDR_SURFACE_FLAGS; 544 545 /** 546 **************************************************************************************************** 547 * ADDR_COMPUTE_SURFACE_INFO_INPUT 548 * 549 * @brief 550 * Input structure for AddrComputeSurfaceInfo 551 **************************************************************************************************** 552 */ 553 typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT 554 { 555 UINT_32 size; ///< Size of this structure in bytes 556 557 AddrTileMode tileMode; ///< Tile mode 558 AddrFormat format; ///< If format is set to valid one, bpp/width/height 559 /// might be overwritten 560 UINT_32 bpp; ///< Bits per pixel 561 UINT_32 numSamples; ///< Number of samples 562 UINT_32 width; ///< Width, in pixels 563 UINT_32 height; ///< Height, in pixels 564 UINT_32 numSlices; ///< Number of surface slices or depth 565 UINT_32 slice; ///< Slice index 566 UINT_32 mipLevel; ///< Current mipmap level 567 UINT_32 numMipLevels; ///< Number of mips in mip chain 568 ADDR_SURFACE_FLAGS flags; ///< Surface type flags 569 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 570 /// number of samples for normal AA; Set it to the 571 /// number of fragments for EQAA 572 /// r800 and later HWL parameters 573 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's 574 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate 575 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1 576 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 577 /// while the global useTileIndex is set to 1 578 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a 579 /// must for mip levels from SI+. 580 /// Don't use pitch in blocks for compressed formats! 581 UINT_32 maxBaseAlign; ///< Max base alignment request from client 582 UINT_32 pitchAlign; ///< Pitch alignment request from client 583 UINT_32 heightAlign; ///< Height alignment request from client 584 } ADDR_COMPUTE_SURFACE_INFO_INPUT; 585 586 /** 587 **************************************************************************************************** 588 * ADDR_COMPUTE_SURFACE_INFO_OUTPUT 589 * 590 * @brief 591 * Output structure for AddrComputeSurfInfo 592 * @note 593 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 594 Pixel: Original pixel 595 **************************************************************************************************** 596 */ 597 typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT 598 { 599 UINT_32 size; ///< Size of this structure in bytes 600 601 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats) 602 UINT_32 height; ///< Height in elements (in blocks for compressed formats) 603 UINT_32 depth; ///< Number of slice/depth 604 UINT_64 surfSize; ///< Surface size in bytes 605 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input 606 UINT_32 baseAlign; ///< Base address alignment 607 UINT_32 pitchAlign; ///< Pitch alignment, in elements 608 UINT_32 heightAlign; ///< Height alignment, in elements 609 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture 610 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit) 611 UINT_32 pixelPitch; ///< Pitch in original pixels 612 UINT_32 pixelHeight; ///< Height in original pixels 613 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 614 UINT_64 sliceSize; ///< Size of slice specified by input's slice 615 /// The result is controlled by surface flags & createFlags 616 /// By default this value equals to surfSize for volume 617 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register 618 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register 619 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register 620 621 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call 622 623 /// r800 and later HWL parameters 624 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input 625 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1 626 INT_32 tileIndex; ///< Tile index, MAY be "downgraded" 627 628 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 629 /// Output flags 630 struct 631 { 632 /// Special information to work around SI mipmap swizzle bug UBTS #317508 633 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled 634 ///< Only meaningful when create flag checkLast2DLevel is set 635 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible 636 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering 637 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT 638 ///< If address lib return true for mip 0, client should set prt flag 639 ///< for child mips in subsequent compute surface info calls 640 UINT_32 reserved :28; ///< Reserved bits 641 }; 642 643 UINT_32 equationIndex; ///< Equation index in the equation table; 644 645 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro) 646 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro) 647 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro) 648 649 /// Stereo info 650 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE 651 652 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set 653 } ADDR_COMPUTE_SURFACE_INFO_OUTPUT; 654 655 /** 656 **************************************************************************************************** 657 * AddrComputeSurfaceInfo 658 * 659 * @brief 660 * Compute surface width/height/depth/alignments and suitable tiling mode 661 **************************************************************************************************** 662 */ 663 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo( 664 ADDR_HANDLE hLib, 665 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 666 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 667 668 669 670 /** 671 **************************************************************************************************** 672 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 673 * 674 * @brief 675 * Input structure for AddrComputeSurfaceAddrFromCoord 676 **************************************************************************************************** 677 */ 678 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 679 { 680 UINT_32 size; ///< Size of this structure in bytes 681 682 UINT_32 x; ///< X coordinate 683 UINT_32 y; ///< Y coordinate 684 UINT_32 slice; ///< Slice index 685 UINT_32 sample; ///< Sample index, use fragment index for EQAA 686 687 UINT_32 bpp; ///< Bits per pixel 688 UINT_32 pitch; ///< Surface pitch, in pixels 689 UINT_32 height; ///< Surface height, in pixels 690 UINT_32 numSlices; ///< Surface depth 691 UINT_32 numSamples; ///< Number of samples 692 693 AddrTileMode tileMode; ///< Tile mode 694 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within 695 /// micro tile. Textures can also choose depth sample order 696 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 697 /// the case that components are stored separately 698 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 699 700 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 701 /// number of samples for normal AA; Set it to the 702 /// number of fragments for EQAA 703 /// r800 and later HWL parameters 704 // Used for 1D tiling above 705 AddrTileType tileType; ///< See defintion of AddrTileType 706 struct 707 { 708 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 709 /// only flag. Only non-RT texture can set this to TRUE 710 UINT_32 reserved :31; ///< Reserved for future use. 711 }; 712 // 2D tiling needs following structure 713 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 714 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 715 /// while the global useTileIndex is set to 1 716 union 717 { 718 struct 719 { 720 UINT_32 bankSwizzle; ///< Bank swizzle 721 UINT_32 pipeSwizzle; ///< Pipe swizzle 722 }; 723 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 724 }; 725 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 726 727 /** 728 **************************************************************************************************** 729 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 730 * 731 * @brief 732 * Output structure for AddrComputeSurfaceAddrFromCoord 733 **************************************************************************************************** 734 */ 735 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 736 { 737 UINT_32 size; ///< Size of this structure in bytes 738 739 UINT_64 addr; ///< Byte address 740 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 741 /// For surface bpp < 8, e.g. FMT_1. 742 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 743 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 744 745 /** 746 **************************************************************************************************** 747 * AddrComputeSurfaceAddrFromCoord 748 * 749 * @brief 750 * Compute surface address from a given coordinate. 751 **************************************************************************************************** 752 */ 753 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord( 754 ADDR_HANDLE hLib, 755 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 756 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 757 758 759 760 /** 761 **************************************************************************************************** 762 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 763 * 764 * @brief 765 * Input structure for AddrComputeSurfaceCoordFromAddr 766 **************************************************************************************************** 767 */ 768 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 769 { 770 UINT_32 size; ///< Size of this structure in bytes 771 772 UINT_64 addr; ///< Address in bytes 773 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 774 /// e.g. FMT_1; 775 UINT_32 bpp; ///< Bits per pixel 776 UINT_32 pitch; ///< Pitch, in pixels 777 UINT_32 height; ///< Height in pixels 778 UINT_32 numSlices; ///< Surface depth 779 UINT_32 numSamples; ///< Number of samples 780 781 AddrTileMode tileMode; ///< Tile mode 782 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile. 783 /// Note: Textures can choose depth sample order as well. 784 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 785 /// the case that components are stored separately 786 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 787 788 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 789 /// number of samples for normal AA; Set it to the 790 /// number of fragments for EQAA 791 /// r800 and later HWL parameters 792 // Used for 1D tiling above 793 AddrTileType tileType; ///< See defintion of AddrTileType 794 struct 795 { 796 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 797 /// only flag. Only non-RT texture can set this to TRUE 798 UINT_32 reserved :31; ///< Reserved for future use. 799 }; 800 // 2D tiling needs following structure 801 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 802 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 803 /// while the global useTileIndex is set to 1 804 union 805 { 806 struct 807 { 808 UINT_32 bankSwizzle; ///< Bank swizzle 809 UINT_32 pipeSwizzle; ///< Pipe swizzle 810 }; 811 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 812 }; 813 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 814 815 /** 816 **************************************************************************************************** 817 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 818 * 819 * @brief 820 * Output structure for AddrComputeSurfaceCoordFromAddr 821 **************************************************************************************************** 822 */ 823 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 824 { 825 UINT_32 size; ///< Size of this structure in bytes 826 827 UINT_32 x; ///< X coordinate 828 UINT_32 y; ///< Y coordinate 829 UINT_32 slice; ///< Index of slices 830 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 831 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 832 833 /** 834 **************************************************************************************************** 835 * AddrComputeSurfaceCoordFromAddr 836 * 837 * @brief 838 * Compute coordinate from a given surface address 839 **************************************************************************************************** 840 */ 841 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr( 842 ADDR_HANDLE hLib, 843 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 844 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 845 846 //////////////////////////////////////////////////////////////////////////////////////////////////// 847 // HTile functions 848 //////////////////////////////////////////////////////////////////////////////////////////////////// 849 850 /** 851 **************************************************************************************************** 852 * ADDR_HTILE_FLAGS 853 * 854 * @brief 855 * HTILE flags 856 **************************************************************************************************** 857 */ 858 typedef union _ADDR_HTILE_FLAGS 859 { 860 struct 861 { 862 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 863 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile 864 /// size to 256xBankxPipe when computing tc-compatible 865 /// htile info. 866 UINT_32 reserved : 30; ///< Reserved bits 867 }; 868 869 UINT_32 value; 870 } ADDR_HTILE_FLAGS; 871 872 /** 873 **************************************************************************************************** 874 * ADDR_COMPUTE_HTILE_INFO_INPUT 875 * 876 * @brief 877 * Input structure of AddrComputeHtileInfo 878 **************************************************************************************************** 879 */ 880 typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT 881 { 882 UINT_32 size; ///< Size of this structure in bytes 883 884 ADDR_HTILE_FLAGS flags; ///< HTILE flags 885 UINT_32 pitch; ///< Surface pitch, in pixels 886 UINT_32 height; ///< Surface height, in pixels 887 UINT_32 numSlices; ///< Number of slices 888 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 889 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8 890 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8 891 ADDR_TILEINFO* pTileInfo; ///< Tile info 892 893 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 894 /// while the global useTileIndex is set to 1 895 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 896 ///< README: When tileIndex is not -1, this must be valid 897 } ADDR_COMPUTE_HTILE_INFO_INPUT; 898 899 /** 900 **************************************************************************************************** 901 * ADDR_COMPUTE_HTILE_INFO_OUTPUT 902 * 903 * @brief 904 * Output structure of AddrComputeHtileInfo 905 **************************************************************************************************** 906 */ 907 typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT 908 { 909 UINT_32 size; ///< Size of this structure in bytes 910 911 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 912 /// HTile buffer. This might be larger than original depth 913 /// buffer pitch when called with an unaligned pitch. 914 UINT_32 height; ///< Height in pixels, as above 915 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes 916 UINT_32 baseAlign; ///< Base alignment 917 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block! 918 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 919 UINT_32 macroHeight; ///< Macro height in pixels 920 UINT_64 sliceSize; ///< Slice size, in bytes. 921 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved 922 /// Compute engine clear can't be used if htile is interleaved 923 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in 924 /// next mip level, it also indicates if memory set based 925 /// fast clear can be used for current mip level. 926 } ADDR_COMPUTE_HTILE_INFO_OUTPUT; 927 928 /** 929 **************************************************************************************************** 930 * AddrComputeHtileInfo 931 * 932 * @brief 933 * Compute Htile pitch, height, base alignment and size in bytes 934 **************************************************************************************************** 935 */ 936 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo( 937 ADDR_HANDLE hLib, 938 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn, 939 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut); 940 941 942 943 /** 944 **************************************************************************************************** 945 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 946 * 947 * @brief 948 * Input structure for AddrComputeHtileAddrFromCoord 949 **************************************************************************************************** 950 */ 951 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 952 { 953 UINT_32 size; ///< Size of this structure in bytes 954 955 UINT_32 pitch; ///< Pitch, in pixels 956 UINT_32 height; ///< Height in pixels 957 UINT_32 x; ///< X coordinate 958 UINT_32 y; ///< Y coordinate 959 UINT_32 slice; ///< Index of slice 960 UINT_32 numSlices; ///< Number of slices 961 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 962 ADDR_HTILE_FLAGS flags; ///< htile flags 963 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 964 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 965 ADDR_TILEINFO* pTileInfo; ///< Tile info 966 967 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 968 /// while the global useTileIndex is set to 1 969 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 970 ///< README: When tileIndex is not -1, this must be valid 971 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size 972 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address 973 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 974 975 /** 976 **************************************************************************************************** 977 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 978 * 979 * @brief 980 * Output structure for AddrComputeHtileAddrFromCoord 981 **************************************************************************************************** 982 */ 983 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 984 { 985 UINT_32 size; ///< Size of this structure in bytes 986 987 UINT_64 addr; ///< Address in bytes 988 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method. 989 /// So we keep bitPosition for HTILE as well 990 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 991 992 /** 993 **************************************************************************************************** 994 * AddrComputeHtileAddrFromCoord 995 * 996 * @brief 997 * Compute Htile address according to coordinates (of depth buffer) 998 **************************************************************************************************** 999 */ 1000 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord( 1001 ADDR_HANDLE hLib, 1002 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 1003 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 1004 1005 1006 1007 /** 1008 **************************************************************************************************** 1009 * ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1010 * 1011 * @brief 1012 * Input structure for AddrComputeHtileCoordFromAddr 1013 **************************************************************************************************** 1014 */ 1015 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1016 { 1017 UINT_32 size; ///< Size of this structure in bytes 1018 1019 UINT_64 addr; ///< Address 1020 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods 1021 /// so we keep bitPosition for HTILE as well 1022 UINT_32 pitch; ///< Pitch, in pixels 1023 UINT_32 height; ///< Height, in pixels 1024 UINT_32 numSlices; ///< Number of slices 1025 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 1026 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1027 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1028 ADDR_TILEINFO* pTileInfo; ///< Tile info 1029 1030 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1031 /// while the global useTileIndex is set to 1 1032 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1033 ///< README: When tileIndex is not -1, this must be valid 1034 } ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT; 1035 1036 /** 1037 **************************************************************************************************** 1038 * ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1039 * 1040 * @brief 1041 * Output structure for AddrComputeHtileCoordFromAddr 1042 **************************************************************************************************** 1043 */ 1044 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1045 { 1046 UINT_32 size; ///< Size of this structure in bytes 1047 1048 UINT_32 x; ///< X coordinate 1049 UINT_32 y; ///< Y coordinate 1050 UINT_32 slice; ///< Slice index 1051 } ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 1052 1053 /** 1054 **************************************************************************************************** 1055 * AddrComputeHtileCoordFromAddr 1056 * 1057 * @brief 1058 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 1059 * Htile address 1060 **************************************************************************************************** 1061 */ 1062 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr( 1063 ADDR_HANDLE hLib, 1064 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 1065 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 1066 1067 1068 1069 //////////////////////////////////////////////////////////////////////////////////////////////////// 1070 // C-mask functions 1071 //////////////////////////////////////////////////////////////////////////////////////////////////// 1072 1073 /** 1074 **************************************************************************************************** 1075 * ADDR_CMASK_FLAGS 1076 * 1077 * @brief 1078 * CMASK flags 1079 **************************************************************************************************** 1080 */ 1081 typedef union _ADDR_CMASK_FLAGS 1082 { 1083 struct 1084 { 1085 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 1086 UINT_32 reserved :31; ///< Reserved bits 1087 }; 1088 1089 UINT_32 value; 1090 } ADDR_CMASK_FLAGS; 1091 1092 /** 1093 **************************************************************************************************** 1094 * ADDR_COMPUTE_CMASK_INFO_INPUT 1095 * 1096 * @brief 1097 * Input structure of AddrComputeCmaskInfo 1098 **************************************************************************************************** 1099 */ 1100 typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT 1101 { 1102 UINT_32 size; ///< Size of this structure in bytes 1103 1104 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1105 UINT_32 pitch; ///< Pitch, in pixels, of color buffer 1106 UINT_32 height; ///< Height, in pixels, of color buffer 1107 UINT_32 numSlices; ///< Number of slices, of color buffer 1108 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1109 ADDR_TILEINFO* pTileInfo; ///< Tile info 1110 1111 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1112 /// while the global useTileIndex is set to 1 1113 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1114 ///< README: When tileIndex is not -1, this must be valid 1115 } ADDR_COMPUTE_CMASK_INFO_INPUT; 1116 1117 /** 1118 **************************************************************************************************** 1119 * ADDR_COMPUTE_CMASK_INFO_OUTPUT 1120 * 1121 * @brief 1122 * Output structure of AddrComputeCmaskInfo 1123 **************************************************************************************************** 1124 */ 1125 typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT 1126 { 1127 UINT_32 size; ///< Size of this structure in bytes 1128 1129 UINT_32 pitch; ///< Pitch in pixels of color buffer which 1130 /// this Cmask matches. The size might be larger than 1131 /// original color buffer pitch when called with 1132 /// an unaligned pitch. 1133 UINT_32 height; ///< Height in pixels, as above 1134 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer 1135 UINT_32 baseAlign; ///< Base alignment 1136 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register 1137 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 1138 UINT_32 macroHeight; ///< Macro height in pixels 1139 UINT_64 sliceSize; ///< Slice size, in bytes. 1140 } ADDR_COMPUTE_CMASK_INFO_OUTPUT; 1141 1142 /** 1143 **************************************************************************************************** 1144 * AddrComputeCmaskInfo 1145 * 1146 * @brief 1147 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 1148 * info 1149 **************************************************************************************************** 1150 */ 1151 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo( 1152 ADDR_HANDLE hLib, 1153 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn, 1154 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut); 1155 1156 1157 1158 /** 1159 **************************************************************************************************** 1160 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1161 * 1162 * @brief 1163 * Input structure for AddrComputeCmaskAddrFromCoord 1164 * 1165 **************************************************************************************************** 1166 */ 1167 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1168 { 1169 UINT_32 size; ///< Size of this structure in bytes 1170 UINT_32 x; ///< X coordinate 1171 UINT_32 y; ///< Y coordinate 1172 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask 1173 UINT_32 slice; ///< Slice index 1174 UINT_32 pitch; ///< Pitch in pixels, of color buffer 1175 UINT_32 height; ///< Height in pixels, of color buffer 1176 UINT_32 numSlices; ///< Number of slices 1177 UINT_32 bpp; 1178 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1179 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1180 ADDR_TILEINFO* pTileInfo; ///< Tile info 1181 1182 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1183 ///< while the global useTileIndex is set to 1 1184 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1185 ///< README: When tileIndex is not -1, this must be valid 1186 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 1187 1188 /** 1189 **************************************************************************************************** 1190 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1191 * 1192 * @brief 1193 * Output structure for AddrComputeCmaskAddrFromCoord 1194 **************************************************************************************************** 1195 */ 1196 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1197 { 1198 UINT_32 size; ///< Size of this structure in bytes 1199 1200 UINT_64 addr; ///< CMASK address in bytes 1201 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1202 /// so the address may be located in bit 0 (0) or 4 (4) 1203 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 1204 1205 /** 1206 **************************************************************************************************** 1207 * AddrComputeCmaskAddrFromCoord 1208 * 1209 * @brief 1210 * Compute Cmask address according to coordinates (of MSAA color buffer) 1211 **************************************************************************************************** 1212 */ 1213 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord( 1214 ADDR_HANDLE hLib, 1215 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 1216 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 1217 1218 1219 1220 /** 1221 **************************************************************************************************** 1222 * ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1223 * 1224 * @brief 1225 * Input structure for AddrComputeCmaskCoordFromAddr 1226 **************************************************************************************************** 1227 */ 1228 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1229 { 1230 UINT_32 size; ///< Size of this structure in bytes 1231 1232 UINT_64 addr; ///< CMASK address in bytes 1233 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1234 /// so the address may be located in bit 0 (0) or 4 (4) 1235 UINT_32 pitch; ///< Pitch, in pixels 1236 UINT_32 height; ///< Height in pixels 1237 UINT_32 numSlices; ///< Number of slices 1238 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1239 ADDR_TILEINFO* pTileInfo; ///< Tile info 1240 1241 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1242 /// while the global useTileIndex is set to 1 1243 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1244 ///< README: When tileIndex is not -1, this must be valid 1245 } ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT; 1246 1247 /** 1248 **************************************************************************************************** 1249 * ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1250 * 1251 * @brief 1252 * Output structure for AddrComputeCmaskCoordFromAddr 1253 **************************************************************************************************** 1254 */ 1255 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1256 { 1257 UINT_32 size; ///< Size of this structure in bytes 1258 1259 UINT_32 x; ///< X coordinate 1260 UINT_32 y; ///< Y coordinate 1261 UINT_32 slice; ///< Slice index 1262 } ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 1263 1264 /** 1265 **************************************************************************************************** 1266 * AddrComputeCmaskCoordFromAddr 1267 * 1268 * @brief 1269 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 1270 * Cmask address 1271 **************************************************************************************************** 1272 */ 1273 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr( 1274 ADDR_HANDLE hLib, 1275 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 1276 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 1277 1278 1279 1280 //////////////////////////////////////////////////////////////////////////////////////////////////// 1281 // F-mask functions 1282 //////////////////////////////////////////////////////////////////////////////////////////////////// 1283 1284 /** 1285 **************************************************************************************************** 1286 * ADDR_COMPUTE_FMASK_INFO_INPUT 1287 * 1288 * @brief 1289 * Input structure for AddrComputeFmaskInfo 1290 **************************************************************************************************** 1291 */ 1292 typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT 1293 { 1294 UINT_32 size; ///< Size of this structure in bytes 1295 1296 AddrTileMode tileMode; ///< Tile mode 1297 UINT_32 pitch; ///< Surface pitch, in pixels 1298 UINT_32 height; ///< Surface height, in pixels 1299 UINT_32 numSlices; ///< Number of slice/depth 1300 UINT_32 numSamples; ///< Number of samples 1301 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1302 /// number of samples for normal AA; Set it to the 1303 /// number of fragments for EQAA 1304 /// r800 and later HWL parameters 1305 struct 1306 { 1307 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used 1308 /// by H/W clients. S/W should always set it to FALSE. 1309 UINT_32 reserved: 31; ///< Reserved for future use. 1310 }; 1311 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data 1312 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1313 /// while the global useTileIndex is set to 1 1314 } ADDR_COMPUTE_FMASK_INFO_INPUT; 1315 1316 /** 1317 **************************************************************************************************** 1318 * ADDR_COMPUTE_FMASK_INFO_OUTPUT 1319 * 1320 * @brief 1321 * Output structure for AddrComputeFmaskInfo 1322 **************************************************************************************************** 1323 */ 1324 typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT 1325 { 1326 UINT_32 size; ///< Size of this structure in bytes 1327 1328 UINT_32 pitch; ///< Pitch of fmask in pixels 1329 UINT_32 height; ///< Height of fmask in pixels 1330 UINT_32 numSlices; ///< Slices of fmask 1331 UINT_64 fmaskBytes; ///< Size of fmask in bytes 1332 UINT_32 baseAlign; ///< Base address alignment 1333 UINT_32 pitchAlign; ///< Pitch alignment 1334 UINT_32 heightAlign; ///< Height alignment 1335 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 1336 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input 1337 /// may be changed in 9xx and above 1338 /// r800 and later HWL parameters 1339 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different 1340 /// bank_height from color buffer 1341 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1342 /// while the global useTileIndex is set to 1 1343 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1344 UINT_64 sliceSize; ///< Size of slice in bytes 1345 } ADDR_COMPUTE_FMASK_INFO_OUTPUT; 1346 1347 /** 1348 **************************************************************************************************** 1349 * AddrComputeFmaskInfo 1350 * 1351 * @brief 1352 * Compute Fmask pitch/height/depth/alignments and size in bytes 1353 **************************************************************************************************** 1354 */ 1355 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo( 1356 ADDR_HANDLE hLib, 1357 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 1358 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 1359 1360 1361 1362 /** 1363 **************************************************************************************************** 1364 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1365 * 1366 * @brief 1367 * Input structure for AddrComputeFmaskAddrFromCoord 1368 **************************************************************************************************** 1369 */ 1370 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1371 { 1372 UINT_32 size; ///< Size of this structure in bytes 1373 1374 UINT_32 x; ///< X coordinate 1375 UINT_32 y; ///< Y coordinate 1376 UINT_32 slice; ///< Slice index 1377 UINT_32 plane; ///< Plane number 1378 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1379 1380 UINT_32 pitch; ///< Surface pitch, in pixels 1381 UINT_32 height; ///< Surface height, in pixels 1382 UINT_32 numSamples; ///< Number of samples 1383 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1384 /// number of samples for normal AA; Set it to the 1385 /// number of fragments for EQAA 1386 1387 AddrTileMode tileMode; ///< Tile mode 1388 union 1389 { 1390 struct 1391 { 1392 UINT_32 bankSwizzle; ///< Bank swizzle 1393 UINT_32 pipeSwizzle; ///< Pipe swizzle 1394 }; 1395 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1396 }; 1397 1398 /// r800 and later HWL parameters 1399 struct 1400 { 1401 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients 1402 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1403 UINT_32 reserved: 30; ///< Reserved for future use. 1404 }; 1405 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data 1406 1407 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 1408 1409 /** 1410 **************************************************************************************************** 1411 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1412 * 1413 * @brief 1414 * Output structure for AddrComputeFmaskAddrFromCoord 1415 **************************************************************************************************** 1416 */ 1417 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1418 { 1419 UINT_32 size; ///< Size of this structure in bytes 1420 1421 UINT_64 addr; ///< Fmask address 1422 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 1423 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 1424 1425 /** 1426 **************************************************************************************************** 1427 * AddrComputeFmaskAddrFromCoord 1428 * 1429 * @brief 1430 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 1431 **************************************************************************************************** 1432 */ 1433 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord( 1434 ADDR_HANDLE hLib, 1435 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 1436 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 1437 1438 1439 1440 /** 1441 **************************************************************************************************** 1442 * ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1443 * 1444 * @brief 1445 * Input structure for AddrComputeFmaskCoordFromAddr 1446 **************************************************************************************************** 1447 */ 1448 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1449 { 1450 UINT_32 size; ///< Size of this structure in bytes 1451 1452 UINT_64 addr; ///< Address 1453 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 1454 1455 UINT_32 pitch; ///< Pitch, in pixels 1456 UINT_32 height; ///< Height in pixels 1457 UINT_32 numSamples; ///< Number of samples 1458 UINT_32 numFrags; ///< Number of fragments 1459 AddrTileMode tileMode; ///< Tile mode 1460 union 1461 { 1462 struct 1463 { 1464 UINT_32 bankSwizzle; ///< Bank swizzle 1465 UINT_32 pipeSwizzle; ///< Pipe swizzle 1466 }; 1467 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1468 }; 1469 1470 /// r800 and later HWL parameters 1471 struct 1472 { 1473 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components 1474 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1475 UINT_32 reserved: 30; ///< Reserved for future use. 1476 }; 1477 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1478 1479 } ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT; 1480 1481 /** 1482 **************************************************************************************************** 1483 * ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1484 * 1485 * @brief 1486 * Output structure for AddrComputeFmaskCoordFromAddr 1487 **************************************************************************************************** 1488 */ 1489 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1490 { 1491 UINT_32 size; ///< Size of this structure in bytes 1492 1493 UINT_32 x; ///< X coordinate 1494 UINT_32 y; ///< Y coordinate 1495 UINT_32 slice; ///< Slice index 1496 UINT_32 plane; ///< Plane number 1497 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1498 } ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 1499 1500 /** 1501 **************************************************************************************************** 1502 * AddrComputeFmaskCoordFromAddr 1503 * 1504 * @brief 1505 * Compute FMASK coordinate from an given address 1506 **************************************************************************************************** 1507 */ 1508 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr( 1509 ADDR_HANDLE hLib, 1510 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 1511 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 1512 1513 1514 //////////////////////////////////////////////////////////////////////////////////////////////////// 1515 // Element/utility functions 1516 //////////////////////////////////////////////////////////////////////////////////////////////////// 1517 1518 /** 1519 **************************************************************************************************** 1520 * AddrGetVersion 1521 * 1522 * @brief 1523 * Get AddrLib version number 1524 **************************************************************************************************** 1525 */ 1526 UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib); 1527 1528 /** 1529 **************************************************************************************************** 1530 * AddrUseTileIndex 1531 * 1532 * @brief 1533 * Return TRUE if tileIndex is enabled in this address library 1534 **************************************************************************************************** 1535 */ 1536 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib); 1537 1538 /** 1539 **************************************************************************************************** 1540 * AddrUseCombinedSwizzle 1541 * 1542 * @brief 1543 * Return TRUE if combined swizzle is enabled in this address library 1544 **************************************************************************************************** 1545 */ 1546 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib); 1547 1548 /** 1549 **************************************************************************************************** 1550 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1551 * 1552 * @brief 1553 * Input structure of AddrExtractBankPipeSwizzle 1554 **************************************************************************************************** 1555 */ 1556 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1557 { 1558 UINT_32 size; ///< Size of this structure in bytes 1559 1560 UINT_32 base256b; ///< Base256b value 1561 1562 /// r800 and later HWL parameters 1563 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1564 1565 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1566 /// while the global useTileIndex is set to 1 1567 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1568 ///< README: When tileIndex is not -1, this must be valid 1569 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT; 1570 1571 /** 1572 **************************************************************************************************** 1573 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1574 * 1575 * @brief 1576 * Output structure of AddrExtractBankPipeSwizzle 1577 **************************************************************************************************** 1578 */ 1579 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1580 { 1581 UINT_32 size; ///< Size of this structure in bytes 1582 1583 UINT_32 bankSwizzle; ///< Bank swizzle 1584 UINT_32 pipeSwizzle; ///< Pipe swizzle 1585 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT; 1586 1587 /** 1588 **************************************************************************************************** 1589 * AddrExtractBankPipeSwizzle 1590 * 1591 * @brief 1592 * Extract Bank and Pipe swizzle from base256b 1593 * @return 1594 * ADDR_OK if no error 1595 **************************************************************************************************** 1596 */ 1597 ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle( 1598 ADDR_HANDLE hLib, 1599 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 1600 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1601 1602 1603 /** 1604 **************************************************************************************************** 1605 * ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1606 * 1607 * @brief 1608 * Input structure of AddrCombineBankPipeSwizzle 1609 **************************************************************************************************** 1610 */ 1611 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1612 { 1613 UINT_32 size; ///< Size of this structure in bytes 1614 1615 UINT_32 bankSwizzle; ///< Bank swizzle 1616 UINT_32 pipeSwizzle; ///< Pipe swizzle 1617 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients) 1618 1619 /// r800 and later HWL parameters 1620 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1621 1622 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1623 /// while the global useTileIndex is set to 1 1624 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1625 ///< README: When tileIndex is not -1, this must be valid 1626 } ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT; 1627 1628 /** 1629 **************************************************************************************************** 1630 * ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1631 * 1632 * @brief 1633 * Output structure of AddrCombineBankPipeSwizzle 1634 **************************************************************************************************** 1635 */ 1636 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1637 { 1638 UINT_32 size; ///< Size of this structure in bytes 1639 1640 UINT_32 tileSwizzle; ///< Combined swizzle 1641 } ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT; 1642 1643 /** 1644 **************************************************************************************************** 1645 * AddrCombineBankPipeSwizzle 1646 * 1647 * @brief 1648 * Combine Bank and Pipe swizzle 1649 * @return 1650 * ADDR_OK if no error 1651 * @note 1652 * baseAddr here is full MCAddress instead of base256b 1653 **************************************************************************************************** 1654 */ 1655 ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle( 1656 ADDR_HANDLE hLib, 1657 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn, 1658 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1659 1660 1661 1662 /** 1663 **************************************************************************************************** 1664 * ADDR_COMPUTE_SLICESWIZZLE_INPUT 1665 * 1666 * @brief 1667 * Input structure of AddrComputeSliceSwizzle 1668 **************************************************************************************************** 1669 */ 1670 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT 1671 { 1672 UINT_32 size; ///< Size of this structure in bytes 1673 1674 AddrTileMode tileMode; ///< Tile Mode 1675 UINT_32 baseSwizzle; ///< Base tile swizzle 1676 UINT_32 slice; ///< Slice index 1677 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases 1678 1679 /// r800 and later HWL parameters 1680 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1681 1682 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1683 /// while the global useTileIndex is set to 1 1684 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1685 ///< README: When tileIndex is not -1, this must be valid 1686 } ADDR_COMPUTE_SLICESWIZZLE_INPUT; 1687 1688 1689 1690 /** 1691 **************************************************************************************************** 1692 * ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1693 * 1694 * @brief 1695 * Output structure of AddrComputeSliceSwizzle 1696 **************************************************************************************************** 1697 */ 1698 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1699 { 1700 UINT_32 size; ///< Size of this structure in bytes 1701 1702 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value 1703 } ADDR_COMPUTE_SLICESWIZZLE_OUTPUT; 1704 1705 /** 1706 **************************************************************************************************** 1707 * AddrComputeSliceSwizzle 1708 * 1709 * @brief 1710 * Extract Bank and Pipe swizzle from base256b 1711 * @return 1712 * ADDR_OK if no error 1713 **************************************************************************************************** 1714 */ 1715 ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle( 1716 ADDR_HANDLE hLib, 1717 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 1718 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut); 1719 1720 1721 /** 1722 **************************************************************************************************** 1723 * AddrSwizzleGenOption 1724 * 1725 * @brief 1726 * Which swizzle generating options: legacy or linear 1727 **************************************************************************************************** 1728 */ 1729 typedef enum _AddrSwizzleGenOption 1730 { 1731 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle 1732 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle 1733 } AddrSwizzleGenOption; 1734 1735 /** 1736 **************************************************************************************************** 1737 * AddrBlockType 1738 * 1739 * @brief 1740 * Macro define resource block type 1741 **************************************************************************************************** 1742 */ 1743 typedef enum 1744 { 1745 AddrBlockLinear = 0, // Resource uses linear swizzle mode 1746 AddrBlockMicro = 1, // Resource uses 256B block 1747 AddrBlockThin4KB = 2, // Resource uses thin 4KB block 1748 AddrBlockThick4KB = 3, // Resource uses thick 4KB block 1749 AddrBlockThin64KB = 4, // Resource uses thin 64KB block 1750 AddrBlockThick64KB = 5, // Resource uses thick 64KB block 1751 AddrBlockThinVar = 6, // Resource uses thin var block 1752 AddrBlockThickVar = 7, // Resource uses thick var block 1753 AddrBlockMaxTiledType, 1754 1755 AddrBlockThin256KB = AddrBlockThinVar, 1756 AddrBlockThick256KB = AddrBlockThickVar, 1757 } AddrBlockType; 1758 1759 /** 1760 **************************************************************************************************** 1761 * AddrSwizzleOption 1762 * 1763 * @brief 1764 * Controls how swizzle is generated 1765 **************************************************************************************************** 1766 */ 1767 typedef union _ADDR_SWIZZLE_OPTION 1768 { 1769 struct 1770 { 1771 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption 1772 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits 1773 UINT_32 reserved :30; ///< Reserved bits 1774 }; 1775 1776 UINT_32 value; 1777 1778 } ADDR_SWIZZLE_OPTION; 1779 1780 /** 1781 **************************************************************************************************** 1782 * ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1783 * 1784 * @brief 1785 * Input structure of AddrComputeBaseSwizzle 1786 **************************************************************************************************** 1787 */ 1788 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1789 { 1790 UINT_32 size; ///< Size of this structure in bytes 1791 1792 ADDR_SWIZZLE_OPTION option; ///< Swizzle option 1793 UINT_32 surfIndex; ///< Index of this surface type 1794 AddrTileMode tileMode; ///< Tile Mode 1795 1796 /// r800 and later HWL parameters 1797 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1798 1799 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1800 /// while the global useTileIndex is set to 1 1801 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1802 ///< README: When tileIndex is not -1, this must be valid 1803 } ADDR_COMPUTE_BASE_SWIZZLE_INPUT; 1804 1805 /** 1806 **************************************************************************************************** 1807 * ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1808 * 1809 * @brief 1810 * Output structure of AddrComputeBaseSwizzle 1811 **************************************************************************************************** 1812 */ 1813 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1814 { 1815 UINT_32 size; ///< Size of this structure in bytes 1816 1817 UINT_32 tileSwizzle; ///< Combined swizzle 1818 } ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT; 1819 1820 /** 1821 **************************************************************************************************** 1822 * AddrComputeBaseSwizzle 1823 * 1824 * @brief 1825 * Return a Combined Bank and Pipe swizzle base on surface based on surface type/index 1826 * @return 1827 * ADDR_OK if no error 1828 **************************************************************************************************** 1829 */ 1830 ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle( 1831 ADDR_HANDLE hLib, 1832 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 1833 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut); 1834 1835 1836 /** 1837 **************************************************************************************************** 1838 * ELEM_GETEXPORTNORM_INPUT 1839 * 1840 * @brief 1841 * Input structure for ElemGetExportNorm 1842 * 1843 **************************************************************************************************** 1844 */ 1845 typedef struct _ELEM_GETEXPORTNORM_INPUT 1846 { 1847 UINT_32 size; ///< Size of this structure in bytes 1848 1849 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat 1850 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType 1851 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap 1852 UINT_32 numSamples; ///< Number of samples 1853 } ELEM_GETEXPORTNORM_INPUT; 1854 1855 /** 1856 **************************************************************************************************** 1857 * ElemGetExportNorm 1858 * 1859 * @brief 1860 * Helper function to check one format can be EXPORT_NUM, which is a register 1861 * CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600 1862 * family 1863 * @note 1864 * The implementation is only for r600. 1865 * 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two 1866 * clocks per export) 1867 * 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one 1868 * clock per export) 1869 * 1870 **************************************************************************************************** 1871 */ 1872 BOOL_32 ADDR_API ElemGetExportNorm( 1873 ADDR_HANDLE hLib, 1874 const ELEM_GETEXPORTNORM_INPUT* pIn); 1875 1876 1877 1878 /** 1879 **************************************************************************************************** 1880 * ELEM_FLT32TODEPTHPIXEL_INPUT 1881 * 1882 * @brief 1883 * Input structure for addrFlt32ToDepthPixel 1884 * 1885 **************************************************************************************************** 1886 */ 1887 typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT 1888 { 1889 UINT_32 size; ///< Size of this structure in bytes 1890 1891 AddrDepthFormat format; ///< Depth buffer format 1892 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil) 1893 } ELEM_FLT32TODEPTHPIXEL_INPUT; 1894 1895 /** 1896 **************************************************************************************************** 1897 * ELEM_FLT32TODEPTHPIXEL_INPUT 1898 * 1899 * @brief 1900 * Output structure for ElemFlt32ToDepthPixel 1901 * 1902 **************************************************************************************************** 1903 */ 1904 typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT 1905 { 1906 UINT_32 size; ///< Size of this structure in bytes 1907 1908 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer. 1909 /// Client must provide enough storage for this type. 1910 UINT_32 depthBase; ///< Tile base in bits for depth bits 1911 UINT_32 stencilBase; ///< Tile base in bits for stencil bits 1912 UINT_32 depthBits; ///< Bits for depth 1913 UINT_32 stencilBits; ///< Bits for stencil 1914 } ELEM_FLT32TODEPTHPIXEL_OUTPUT; 1915 1916 /** 1917 **************************************************************************************************** 1918 * ElemFlt32ToDepthPixel 1919 * 1920 * @brief 1921 * Convert a FLT_32 value to a depth/stencil pixel value 1922 * 1923 * @return 1924 * Return code 1925 * 1926 **************************************************************************************************** 1927 */ 1928 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel( 1929 ADDR_HANDLE hLib, 1930 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 1931 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut); 1932 1933 1934 1935 /** 1936 **************************************************************************************************** 1937 * ELEM_FLT32TOCOLORPIXEL_INPUT 1938 * 1939 * @brief 1940 * Input structure for addrFlt32ToColorPixel 1941 * 1942 **************************************************************************************************** 1943 */ 1944 typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT 1945 { 1946 UINT_32 size; ///< Size of this structure in bytes 1947 1948 AddrColorFormat format; ///< Color buffer format 1949 AddrSurfaceNumber surfNum; ///< Surface number 1950 AddrSurfaceSwap surfSwap; ///< Surface swap 1951 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a) 1952 } ELEM_FLT32TOCOLORPIXEL_INPUT; 1953 1954 /** 1955 **************************************************************************************************** 1956 * ELEM_FLT32TOCOLORPIXEL_INPUT 1957 * 1958 * @brief 1959 * Output structure for ElemFlt32ToColorPixel 1960 * 1961 **************************************************************************************************** 1962 */ 1963 typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT 1964 { 1965 UINT_32 size; ///< Size of this structure in bytes 1966 1967 UINT_8* pPixel; ///< Real color value. Same data type as color buffer. 1968 /// Client must provide enough storage for this type. 1969 } ELEM_FLT32TOCOLORPIXEL_OUTPUT; 1970 1971 /** 1972 **************************************************************************************************** 1973 * ElemFlt32ToColorPixel 1974 * 1975 * @brief 1976 * Convert a FLT_32 value to a red/green/blue/alpha pixel value 1977 * 1978 * @return 1979 * Return code 1980 * 1981 **************************************************************************************************** 1982 */ 1983 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel( 1984 ADDR_HANDLE hLib, 1985 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 1986 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut); 1987 1988 /** 1989 **************************************************************************************************** 1990 * ElemSize 1991 * 1992 * @brief 1993 * Get bits-per-element for specified format 1994 * 1995 * @return 1996 * Bits-per-element of specified format 1997 * 1998 **************************************************************************************************** 1999 */ 2000 UINT_32 ADDR_API ElemSize( 2001 ADDR_HANDLE hLib, 2002 AddrFormat format); 2003 2004 /** 2005 **************************************************************************************************** 2006 * ADDR_CONVERT_TILEINFOTOHW_INPUT 2007 * 2008 * @brief 2009 * Input structure for AddrConvertTileInfoToHW 2010 * @note 2011 * When reverse is TRUE, indices are igonred 2012 **************************************************************************************************** 2013 */ 2014 typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT 2015 { 2016 UINT_32 size; ///< Size of this structure in bytes 2017 BOOL_32 reverse; ///< Convert control flag. 2018 /// FALSE: convert from real value to HW value; 2019 /// TRUE: convert from HW value to real value. 2020 2021 /// r800 and later HWL parameters 2022 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value 2023 2024 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 2025 /// while the global useTileIndex is set to 1 2026 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2027 ///< README: When tileIndex is not -1, this must be valid 2028 UINT_32 bpp; ///< Bits per pixel 2029 } ADDR_CONVERT_TILEINFOTOHW_INPUT; 2030 2031 /** 2032 **************************************************************************************************** 2033 * ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2034 * 2035 * @brief 2036 * Output structure for AddrConvertTileInfoToHW 2037 **************************************************************************************************** 2038 */ 2039 typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2040 { 2041 UINT_32 size; ///< Size of this structure in bytes 2042 2043 /// r800 and later HWL parameters 2044 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value 2045 2046 } ADDR_CONVERT_TILEINFOTOHW_OUTPUT; 2047 2048 /** 2049 **************************************************************************************************** 2050 * AddrConvertTileInfoToHW 2051 * 2052 * @brief 2053 * Convert tile info from real value to hardware register value 2054 **************************************************************************************************** 2055 */ 2056 ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW( 2057 ADDR_HANDLE hLib, 2058 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 2059 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut); 2060 2061 2062 2063 /** 2064 **************************************************************************************************** 2065 * ADDR_CONVERT_TILEINDEX_INPUT 2066 * 2067 * @brief 2068 * Input structure for AddrConvertTileIndex 2069 **************************************************************************************************** 2070 */ 2071 typedef struct _ADDR_CONVERT_TILEINDEX_INPUT 2072 { 2073 UINT_32 size; ///< Size of this structure in bytes 2074 2075 INT_32 tileIndex; ///< Tile index 2076 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2077 UINT_32 bpp; ///< Bits per pixel 2078 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2079 } ADDR_CONVERT_TILEINDEX_INPUT; 2080 2081 /** 2082 **************************************************************************************************** 2083 * ADDR_CONVERT_TILEINDEX_OUTPUT 2084 * 2085 * @brief 2086 * Output structure for AddrConvertTileIndex 2087 **************************************************************************************************** 2088 */ 2089 typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT 2090 { 2091 UINT_32 size; ///< Size of this structure in bytes 2092 2093 AddrTileMode tileMode; ///< Tile mode 2094 AddrTileType tileType; ///< Tile type 2095 ADDR_TILEINFO* pTileInfo; ///< Tile info 2096 2097 } ADDR_CONVERT_TILEINDEX_OUTPUT; 2098 2099 /** 2100 **************************************************************************************************** 2101 * AddrConvertTileIndex 2102 * 2103 * @brief 2104 * Convert tile index to tile mode/type/info 2105 **************************************************************************************************** 2106 */ 2107 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex( 2108 ADDR_HANDLE hLib, 2109 const ADDR_CONVERT_TILEINDEX_INPUT* pIn, 2110 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2111 2112 /** 2113 **************************************************************************************************** 2114 * ADDR_GET_MACROMODEINDEX_INPUT 2115 * 2116 * @brief 2117 * Input structure for AddrGetMacroModeIndex 2118 **************************************************************************************************** 2119 */ 2120 typedef struct _ADDR_GET_MACROMODEINDEX_INPUT 2121 { 2122 UINT_32 size; ///< Size of this structure in bytes 2123 ADDR_SURFACE_FLAGS flags; ///< Surface flag 2124 INT_32 tileIndex; ///< Tile index 2125 UINT_32 bpp; ///< Bits per pixel 2126 UINT_32 numFrags; ///< Number of color fragments 2127 } ADDR_GET_MACROMODEINDEX_INPUT; 2128 2129 /** 2130 **************************************************************************************************** 2131 * ADDR_GET_MACROMODEINDEX_OUTPUT 2132 * 2133 * @brief 2134 * Output structure for AddrGetMacroModeIndex 2135 **************************************************************************************************** 2136 */ 2137 typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT 2138 { 2139 UINT_32 size; ///< Size of this structure in bytes 2140 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2141 } ADDR_GET_MACROMODEINDEX_OUTPUT; 2142 2143 /** 2144 **************************************************************************************************** 2145 * AddrGetMacroModeIndex 2146 * 2147 * @brief 2148 * Get macro mode index based on input parameters 2149 **************************************************************************************************** 2150 */ 2151 ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex( 2152 ADDR_HANDLE hLib, 2153 const ADDR_GET_MACROMODEINDEX_INPUT* pIn, 2154 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut); 2155 2156 /** 2157 **************************************************************************************************** 2158 * ADDR_CONVERT_TILEINDEX1_INPUT 2159 * 2160 * @brief 2161 * Input structure for AddrConvertTileIndex1 (without macro mode index) 2162 **************************************************************************************************** 2163 */ 2164 typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT 2165 { 2166 UINT_32 size; ///< Size of this structure in bytes 2167 2168 INT_32 tileIndex; ///< Tile index 2169 UINT_32 bpp; ///< Bits per pixel 2170 UINT_32 numSamples; ///< Number of samples 2171 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2172 } ADDR_CONVERT_TILEINDEX1_INPUT; 2173 2174 /** 2175 **************************************************************************************************** 2176 * AddrConvertTileIndex1 2177 * 2178 * @brief 2179 * Convert tile index to tile mode/type/info 2180 **************************************************************************************************** 2181 */ 2182 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1( 2183 ADDR_HANDLE hLib, 2184 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn, 2185 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2186 2187 2188 2189 /** 2190 **************************************************************************************************** 2191 * ADDR_GET_TILEINDEX_INPUT 2192 * 2193 * @brief 2194 * Input structure for AddrGetTileIndex 2195 **************************************************************************************************** 2196 */ 2197 typedef struct _ADDR_GET_TILEINDEX_INPUT 2198 { 2199 UINT_32 size; ///< Size of this structure in bytes 2200 2201 AddrTileMode tileMode; ///< Tile mode 2202 AddrTileType tileType; ///< Tile-type: disp/non-disp/... 2203 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D 2204 } ADDR_GET_TILEINDEX_INPUT; 2205 2206 /** 2207 **************************************************************************************************** 2208 * ADDR_GET_TILEINDEX_OUTPUT 2209 * 2210 * @brief 2211 * Output structure for AddrGetTileIndex 2212 **************************************************************************************************** 2213 */ 2214 typedef struct _ADDR_GET_TILEINDEX_OUTPUT 2215 { 2216 UINT_32 size; ///< Size of this structure in bytes 2217 2218 INT_32 index; ///< index in table 2219 } ADDR_GET_TILEINDEX_OUTPUT; 2220 2221 /** 2222 **************************************************************************************************** 2223 * AddrGetTileIndex 2224 * 2225 * @brief 2226 * Get the tiling mode index in table 2227 **************************************************************************************************** 2228 */ 2229 ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex( 2230 ADDR_HANDLE hLib, 2231 const ADDR_GET_TILEINDEX_INPUT* pIn, 2232 ADDR_GET_TILEINDEX_OUTPUT* pOut); 2233 2234 2235 2236 /** 2237 **************************************************************************************************** 2238 * ADDR_PRT_INFO_INPUT 2239 * 2240 * @brief 2241 * Input structure for AddrComputePrtInfo 2242 **************************************************************************************************** 2243 */ 2244 typedef struct _ADDR_PRT_INFO_INPUT 2245 { 2246 AddrFormat format; ///< Surface format 2247 UINT_32 baseMipWidth; ///< Base mipmap width 2248 UINT_32 baseMipHeight; ///< Base mipmap height 2249 UINT_32 baseMipDepth; ///< Base mipmap depth 2250 UINT_32 numFrags; ///< Number of fragments, 2251 } ADDR_PRT_INFO_INPUT; 2252 2253 /** 2254 **************************************************************************************************** 2255 * ADDR_PRT_INFO_OUTPUT 2256 * 2257 * @brief 2258 * Input structure for AddrComputePrtInfo 2259 **************************************************************************************************** 2260 */ 2261 typedef struct _ADDR_PRT_INFO_OUTPUT 2262 { 2263 UINT_32 prtTileWidth; 2264 UINT_32 prtTileHeight; 2265 } ADDR_PRT_INFO_OUTPUT; 2266 2267 /** 2268 **************************************************************************************************** 2269 * AddrComputePrtInfo 2270 * 2271 * @brief 2272 * Compute prt surface related information 2273 **************************************************************************************************** 2274 */ 2275 ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo( 2276 ADDR_HANDLE hLib, 2277 const ADDR_PRT_INFO_INPUT* pIn, 2278 ADDR_PRT_INFO_OUTPUT* pOut); 2279 2280 2281 2282 //////////////////////////////////////////////////////////////////////////////////////////////////// 2283 // DCC key functions 2284 //////////////////////////////////////////////////////////////////////////////////////////////////// 2285 2286 /** 2287 **************************************************************************************************** 2288 * _ADDR_COMPUTE_DCCINFO_INPUT 2289 * 2290 * @brief 2291 * Input structure of AddrComputeDccInfo 2292 **************************************************************************************************** 2293 */ 2294 typedef struct _ADDR_COMPUTE_DCCINFO_INPUT 2295 { 2296 UINT_32 size; ///< Size of this structure in bytes 2297 UINT_32 bpp; ///< BitPP of color surface 2298 UINT_32 numSamples; ///< Sample number of color surface 2299 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound 2300 AddrTileMode tileMode; ///< Tile mode of color surface 2301 ADDR_TILEINFO tileInfo; ///< Tile info of color surface 2302 UINT_32 tileSwizzle; ///< Tile swizzle 2303 INT_32 tileIndex; ///< Tile index of color surface, 2304 ///< MUST be -1 if you don't want to use it 2305 ///< while the global useTileIndex is set to 1 2306 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2307 ///< README: When tileIndex is not -1, this must be valid 2308 } ADDR_COMPUTE_DCCINFO_INPUT; 2309 2310 /** 2311 **************************************************************************************************** 2312 * ADDR_COMPUTE_DCCINFO_OUTPUT 2313 * 2314 * @brief 2315 * Output structure of AddrComputeDccInfo 2316 **************************************************************************************************** 2317 */ 2318 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT 2319 { 2320 UINT_32 size; ///< Size of this structure in bytes 2321 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 2322 UINT_64 dccRamSize; ///< Size of dcc key 2323 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared 2324 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable 2325 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned 2326 } ADDR_COMPUTE_DCCINFO_OUTPUT; 2327 2328 /** 2329 **************************************************************************************************** 2330 * AddrComputeDccInfo 2331 * 2332 * @brief 2333 * Compute DCC key size, base alignment 2334 * info 2335 **************************************************************************************************** 2336 */ 2337 ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo( 2338 ADDR_HANDLE hLib, 2339 const ADDR_COMPUTE_DCCINFO_INPUT* pIn, 2340 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut); 2341 2342 2343 /** 2344 **************************************************************************************************** 2345 * ADDR_GET_MAX_ALIGNMENTS_OUTPUT 2346 * 2347 * @brief 2348 * Output structure of AddrGetMaxAlignments 2349 **************************************************************************************************** 2350 */ 2351 typedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT 2352 { 2353 UINT_32 size; ///< Size of this structure in bytes 2354 UINT_32 baseAlign; ///< Maximum base alignment in bytes 2355 } ADDR_GET_MAX_ALIGNMENTS_OUTPUT; 2356 2357 /** 2358 **************************************************************************************************** 2359 * AddrGetMaxAlignments 2360 * 2361 * @brief 2362 * Gets maximnum alignments 2363 **************************************************************************************************** 2364 */ 2365 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments( 2366 ADDR_HANDLE hLib, 2367 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2368 2369 /** 2370 **************************************************************************************************** 2371 * AddrGetMaxMetaAlignments 2372 * 2373 * @brief 2374 * Gets maximnum alignments for metadata 2375 **************************************************************************************************** 2376 */ 2377 ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments( 2378 ADDR_HANDLE hLib, 2379 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2380 2381 /** 2382 **************************************************************************************************** 2383 * Address library interface version 2 2384 * available from Gfx9 hardware 2385 **************************************************************************************************** 2386 * Addr2ComputeSurfaceInfo() 2387 * Addr2ComputeSurfaceAddrFromCoord() 2388 * Addr2ComputeSurfaceCoordFromAddr() 2389 2390 * Addr2ComputeHtileInfo() 2391 * Addr2ComputeHtileAddrFromCoord() 2392 * Addr2ComputeHtileCoordFromAddr() 2393 * 2394 * Addr2ComputeCmaskInfo() 2395 * Addr2ComputeCmaskAddrFromCoord() 2396 * Addr2ComputeCmaskCoordFromAddr() 2397 * 2398 * Addr2ComputeFmaskInfo() 2399 * Addr2ComputeFmaskAddrFromCoord() 2400 * Addr2ComputeFmaskCoordFromAddr() 2401 * 2402 * Addr2ComputeDccInfo() 2403 * 2404 **/ 2405 2406 2407 //////////////////////////////////////////////////////////////////////////////////////////////////// 2408 // Surface functions for Addr2 2409 //////////////////////////////////////////////////////////////////////////////////////////////////// 2410 2411 /** 2412 **************************************************************************************************** 2413 * ADDR2_SURFACE_FLAGS 2414 * 2415 * @brief 2416 * Surface flags 2417 **************************************************************************************************** 2418 */ 2419 typedef union _ADDR2_SURFACE_FLAGS 2420 { 2421 struct 2422 { 2423 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 2424 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV 2425 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV 2426 UINT_32 fmask : 1; ///< This is an fmask surface 2427 UINT_32 overlay : 1; ///< This is an overlay surface 2428 UINT_32 display : 1; ///< This resource is displayable, can be used with DRV 2429 UINT_32 prt : 1; ///< This is a partially resident texture 2430 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface 2431 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 2432 UINT_32 texture : 1; ///< This resource can be used with SRV 2433 UINT_32 unordered : 1; ///< This resource can be used with UAV 2434 UINT_32 rotated : 1; ///< This resource is rotated and displayable 2435 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible 2436 UINT_32 opt4space : 1; ///< This resource should be optimized for space 2437 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment 2438 UINT_32 noMetadata : 1; ///< This resource has no metadata 2439 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata 2440 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata 2441 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array 2442 UINT_32 allowExtEquation : 1; ///< If unset, only legacy DX eqs are allowed (2 XORs) 2443 UINT_32 requireMetadata : 1; ///< This resource must support metadata 2444 UINT_32 reserved : 11; ///< Reserved bits 2445 }; 2446 2447 UINT_32 value; 2448 } ADDR2_SURFACE_FLAGS; 2449 2450 /** 2451 **************************************************************************************************** 2452 * ADDR2_COMPUTE_SURFACE_INFO_INPUT 2453 * 2454 * @brief 2455 * Input structure for Addr2ComputeSurfaceInfo 2456 **************************************************************************************************** 2457 */ 2458 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT 2459 { 2460 UINT_32 size; ///< Size of this structure in bytes 2461 2462 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2463 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Addr2 2464 AddrResourceType resourceType; ///< Surface type 2465 AddrFormat format; ///< Surface format 2466 UINT_32 bpp; ///< bits per pixel 2467 UINT_32 width; ///< Width (of mip0), in pixels 2468 UINT_32 height; ///< Height (of mip0), in pixels 2469 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 2470 UINT_32 numMipLevels; ///< Total mipmap levels. 2471 UINT_32 numSamples; ///< Number of samples 2472 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2473 /// number of samples for normal AA; Set it to the 2474 /// number of fragments for EQAA 2475 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2476 UINT_32 sliceAlign; ///< Required slice size in bytes 2477 } ADDR2_COMPUTE_SURFACE_INFO_INPUT; 2478 2479 /** 2480 **************************************************************************************************** 2481 * ADDR2_MIP_INFO 2482 * 2483 * @brief 2484 * Structure that contains information for mip level 2485 * 2486 **************************************************************************************************** 2487 */ 2488 typedef struct _ADDR2_MIP_INFO 2489 { 2490 UINT_32 pitch; ///< Pitch in elements 2491 UINT_32 height; ///< Padded height in elements 2492 UINT_32 depth; ///< Padded depth 2493 UINT_32 pixelPitch; ///< Pitch in pixels 2494 UINT_32 pixelHeight; ///< Padded height in pixels 2495 UINT_32 equationIndex; ///< Equation index in the equation table 2496 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 2497 ///< to setup vam surface descriptor, can't be used 2498 ///< to setup swizzle pattern 2499 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 2500 UINT_32 mipTailOffset; ///< mip tail offset in bytes 2501 UINT_32 mipTailCoordX; ///< mip tail coord x 2502 UINT_32 mipTailCoordY; ///< mip tail coord y 2503 UINT_32 mipTailCoordZ; ///< mip tail coord z 2504 } ADDR2_MIP_INFO; 2505 2506 /** 2507 **************************************************************************************************** 2508 * ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2509 * 2510 * @brief 2511 * Output structure for Addr2ComputeSurfInfo 2512 * @note 2513 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 2514 Pixel: Original pixel 2515 **************************************************************************************************** 2516 */ 2517 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2518 { 2519 UINT_32 size; ///< Size of this structure in bytes 2520 2521 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats) 2522 UINT_32 height; ///< Padded height (of mip0) in elements 2523 UINT_32 numSlices; ///< Padded depth for 3d resource 2524 ///< or padded number of slices for 2d array resource 2525 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements 2526 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements 2527 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain) 2528 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 2529 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 2530 UINT_32 baseAlign; ///< Base address alignment 2531 UINT_32 bpp; ///< Bits per elements 2532 /// (e.g. blocks for BCn, 1/3 for 96bit) 2533 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 2534 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 2535 UINT_32 pixelPitch; ///< Pitch in original pixels 2536 UINT_32 pixelHeight; ///< Height in original pixels 2537 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 2538 2539 UINT_32 blockWidth; ///< Width in element inside one block 2540 UINT_32 blockHeight; ///< Height in element inside one block 2541 UINT_32 blockSlices; ///< Slice number inside one block 2542 ///< Prt tile is one block, its width/height/slice 2543 ///< equals to blcok width/height/slice 2544 2545 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register 2546 /// Stereo info 2547 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 2548 /// Mip info 2549 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array 2550 /// if it is not NULL, the array is assumed to 2551 /// contain numMipLevels entries 2552 2553 UINT_32 equationIndex; ///< Equation index in the equation table of mip0 2554 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 2555 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 2556 /// in tail, it will be set to number of mip levels 2557 } ADDR2_COMPUTE_SURFACE_INFO_OUTPUT; 2558 2559 /** 2560 **************************************************************************************************** 2561 * Addr2ComputeSurfaceInfo 2562 * 2563 * @brief 2564 * Compute surface width/height/slices/alignments and suitable tiling mode 2565 **************************************************************************************************** 2566 */ 2567 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo( 2568 ADDR_HANDLE hLib, 2569 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 2570 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 2571 2572 2573 2574 /** 2575 **************************************************************************************************** 2576 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2577 * 2578 * @brief 2579 * Input structure for Addr2ComputeSurfaceAddrFromCoord 2580 **************************************************************************************************** 2581 */ 2582 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2583 { 2584 UINT_32 size; ///< Size of this structure in bytes 2585 2586 UINT_32 x; ///< X coordinate 2587 UINT_32 y; ///< Y coordinate 2588 UINT_32 slice; ///< Slice index 2589 UINT_32 sample; ///< Sample index, use fragment index for EQAA 2590 UINT_32 mipId; ///< the mip ID in mip chain 2591 2592 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Addr2 2593 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2594 AddrResourceType resourceType; ///< Surface type 2595 UINT_32 bpp; ///< Bits per pixel 2596 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2597 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2598 UINT_32 numSlices; ///< Surface original slices (of mip0) 2599 UINT_32 numMipLevels; ///< Total mipmap levels 2600 UINT_32 numSamples; ///< Number of samples 2601 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2602 /// number of samples for normal AA; Set it to the 2603 /// number of fragments for EQAA 2604 2605 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2606 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2607 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 2608 2609 /** 2610 **************************************************************************************************** 2611 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2612 * 2613 * @brief 2614 * Output structure for Addr2ComputeSurfaceAddrFromCoord 2615 **************************************************************************************************** 2616 */ 2617 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2618 { 2619 UINT_32 size; ///< Size of this structure in bytes 2620 2621 UINT_64 addr; ///< Byte offset from the image starting address 2622 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 2623 /// For surface bpp < 8, e.g. FMT_1. 2624 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 2625 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 2626 2627 /** 2628 **************************************************************************************************** 2629 * Addr2ComputeSurfaceAddrFromCoord 2630 * 2631 * @brief 2632 * Compute surface address from a given coordinate. 2633 **************************************************************************************************** 2634 */ 2635 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord( 2636 ADDR_HANDLE hLib, 2637 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 2638 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 2639 2640 2641 2642 /** 2643 **************************************************************************************************** 2644 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2645 * 2646 * @brief 2647 * Input structure for Addr2ComputeSurfaceCoordFromAddr 2648 **************************************************************************************************** 2649 */ 2650 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2651 { 2652 UINT_32 size; ///< Size of this structure in bytes 2653 2654 UINT_64 addr; ///< Address in bytes 2655 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 2656 /// e.g. FMT_1; 2657 2658 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Addr2 2659 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2660 AddrResourceType resourceType; ///< Surface type 2661 UINT_32 bpp; ///< Bits per pixel 2662 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2663 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2664 UINT_32 numSlices; ///< Surface original slices (of mip0) 2665 UINT_32 numMipLevels; ///< Total mipmap levels. 2666 UINT_32 numSamples; ///< Number of samples 2667 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2668 /// number of samples for normal AA; Set it to the 2669 /// number of fragments for EQAA 2670 2671 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2672 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2673 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 2674 2675 /** 2676 **************************************************************************************************** 2677 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2678 * 2679 * @brief 2680 * Output structure for Addr2ComputeSurfaceCoordFromAddr 2681 **************************************************************************************************** 2682 */ 2683 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2684 { 2685 UINT_32 size; ///< Size of this structure in bytes 2686 2687 UINT_32 x; ///< X coordinate 2688 UINT_32 y; ///< Y coordinate 2689 UINT_32 slice; ///< Index of slices 2690 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 2691 UINT_32 mipId; ///< mipmap level id 2692 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 2693 2694 /** 2695 **************************************************************************************************** 2696 * Addr2ComputeSurfaceCoordFromAddr 2697 * 2698 * @brief 2699 * Compute coordinate from a given surface address 2700 **************************************************************************************************** 2701 */ 2702 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr( 2703 ADDR_HANDLE hLib, 2704 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 2705 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 2706 2707 2708 2709 //////////////////////////////////////////////////////////////////////////////////////////////////// 2710 // HTile functions for Addr2 2711 //////////////////////////////////////////////////////////////////////////////////////////////////// 2712 2713 /** 2714 **************************************************************************************************** 2715 * ADDR2_META_FLAGS 2716 * 2717 * @brief 2718 * Metadata flags 2719 **************************************************************************************************** 2720 */ 2721 typedef union _ADDR2_META_FLAGS 2722 { 2723 struct 2724 { 2725 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned 2726 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned 2727 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this! 2728 UINT_32 reserved : 29; ///< Reserved bits 2729 }; 2730 2731 UINT_32 value; 2732 } ADDR2_META_FLAGS; 2733 2734 /** 2735 **************************************************************************************************** 2736 * ADDR2_META_MIP_INFO 2737 * 2738 * @brief 2739 * Structure to store per mip metadata information 2740 **************************************************************************************************** 2741 */ 2742 typedef struct _ADDR2_META_MIP_INFO 2743 { 2744 BOOL_32 inMiptail; 2745 union 2746 { 2747 struct 2748 { 2749 UINT_32 startX; 2750 UINT_32 startY; 2751 UINT_32 startZ; 2752 UINT_32 width; 2753 UINT_32 height; 2754 UINT_32 depth; 2755 }; 2756 2757 // GFX10 2758 struct 2759 { 2760 UINT_32 offset; ///< Metadata offset within one slice, 2761 /// the thickness of a slice is meta block depth. 2762 UINT_32 sliceSize; ///< Metadata size within one slice, 2763 /// the thickness of a slice is meta block depth. 2764 }; 2765 }; 2766 } ADDR2_META_MIP_INFO; 2767 2768 /** 2769 **************************************************************************************************** 2770 * ADDR2_COMPUTE_HTILE_INFO_INPUT 2771 * 2772 * @brief 2773 * Input structure of Addr2ComputeHtileInfo 2774 **************************************************************************************************** 2775 */ 2776 typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT 2777 { 2778 UINT_32 size; ///< Size of this structure in bytes 2779 2780 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2781 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2782 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2783 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2784 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2785 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0) 2786 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 2787 UINT_32 firstMipIdInTail; /// Id of the first mip in tail, 2788 /// if no mip is in tail, it should be set to 2789 /// number of mip levels 2790 /// Only for GFX10 2791 } ADDR2_COMPUTE_HTILE_INFO_INPUT; 2792 2793 /** 2794 **************************************************************************************************** 2795 * ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2796 * 2797 * @brief 2798 * Output structure of Addr2ComputeHtileInfo 2799 **************************************************************************************************** 2800 */ 2801 typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2802 { 2803 UINT_32 size; ///< Size of this structure in bytes 2804 2805 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 2806 /// HTile buffer. This might be larger than original depth 2807 /// buffer pitch when called with an unaligned pitch. 2808 UINT_32 height; ///< Height in pixels, as above 2809 UINT_32 baseAlign; ///< Base alignment 2810 UINT_32 sliceSize; ///< Slice size, in bytes. 2811 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes 2812 UINT_32 metaBlkWidth; ///< Meta block width 2813 UINT_32 metaBlkHeight; ///< Meta block height 2814 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2815 2816 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information 2817 2818 struct { 2819 UINT_16* gfx10_bits; /* 72 2-byte elements */ 2820 } equation; 2821 } ADDR2_COMPUTE_HTILE_INFO_OUTPUT; 2822 2823 /** 2824 **************************************************************************************************** 2825 * Addr2ComputeHtileInfo 2826 * 2827 * @brief 2828 * Compute Htile pitch, height, base alignment and size in bytes 2829 **************************************************************************************************** 2830 */ 2831 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo( 2832 ADDR_HANDLE hLib, 2833 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 2834 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut); 2835 2836 2837 2838 /** 2839 **************************************************************************************************** 2840 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2841 * 2842 * @brief 2843 * Input structure for Addr2ComputeHtileAddrFromCoord 2844 **************************************************************************************************** 2845 */ 2846 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2847 { 2848 UINT_32 size; ///< Size of this structure in bytes 2849 2850 UINT_32 x; ///< X coordinate 2851 UINT_32 y; ///< Y coordinate 2852 UINT_32 slice; ///< Index of slices 2853 UINT_32 mipId; ///< mipmap level id 2854 2855 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2856 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags 2857 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2858 UINT_32 bpp; ///< Depth surface bits per pixel 2859 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2860 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2861 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2862 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2863 UINT_32 numSamples; ///< Depth surface number of samples 2864 UINT_32 pipeXor; ///< Pipe xor setting 2865 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 2866 2867 /** 2868 **************************************************************************************************** 2869 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2870 * 2871 * @brief 2872 * Output structure for Addr2ComputeHtileAddrFromCoord 2873 **************************************************************************************************** 2874 */ 2875 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2876 { 2877 UINT_32 size; ///< Size of this structure in bytes 2878 2879 UINT_64 addr; ///< Address in bytes 2880 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 2881 2882 /** 2883 **************************************************************************************************** 2884 * Addr2ComputeHtileAddrFromCoord 2885 * 2886 * @brief 2887 * Compute Htile address according to coordinates (of depth buffer) 2888 **************************************************************************************************** 2889 */ 2890 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord( 2891 ADDR_HANDLE hLib, 2892 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 2893 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 2894 2895 2896 2897 /** 2898 **************************************************************************************************** 2899 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2900 * 2901 * @brief 2902 * Input structure for Addr2ComputeHtileCoordFromAddr 2903 **************************************************************************************************** 2904 */ 2905 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2906 { 2907 UINT_32 size; ///< Size of this structure in bytes 2908 2909 UINT_64 addr; ///< Address 2910 2911 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2912 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2913 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2914 UINT_32 bpp; ///< Depth surface bits per pixel 2915 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2916 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2917 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2918 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2919 UINT_32 numSamples; ///< Depth surface number of samples 2920 UINT_32 pipeXor; ///< Pipe xor setting 2921 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT; 2922 2923 /** 2924 **************************************************************************************************** 2925 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2926 * 2927 * @brief 2928 * Output structure for Addr2ComputeHtileCoordFromAddr 2929 **************************************************************************************************** 2930 */ 2931 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2932 { 2933 UINT_32 size; ///< Size of this structure in bytes 2934 2935 UINT_32 x; ///< X coordinate 2936 UINT_32 y; ///< Y coordinate 2937 UINT_32 slice; ///< Index of slices 2938 UINT_32 mipId; ///< mipmap level id 2939 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 2940 2941 /** 2942 **************************************************************************************************** 2943 * Addr2ComputeHtileCoordFromAddr 2944 * 2945 * @brief 2946 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 2947 * Htile address 2948 **************************************************************************************************** 2949 */ 2950 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr( 2951 ADDR_HANDLE hLib, 2952 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 2953 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 2954 2955 2956 2957 //////////////////////////////////////////////////////////////////////////////////////////////////// 2958 // C-mask functions for Addr2 2959 //////////////////////////////////////////////////////////////////////////////////////////////////// 2960 2961 /** 2962 **************************************************************************************************** 2963 * ADDR2_COMPUTE_CMASK_INFO_INPUT 2964 * 2965 * @brief 2966 * Input structure of Addr2ComputeCmaskInfo 2967 **************************************************************************************************** 2968 */ 2969 typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT 2970 { 2971 UINT_32 size; ///< Size of this structure in bytes 2972 2973 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2974 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 2975 AddrResourceType resourceType; ///< Color surface type 2976 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2977 UINT_32 unalignedWidth; ///< Color surface original width 2978 UINT_32 unalignedHeight; ///< Color surface original height 2979 UINT_32 numSlices; ///< Number of slices of color buffer 2980 UINT_32 numMipLevels; ///< Number of mip levels 2981 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 2982 /// it should be number of mip levels 2983 /// Only for GFX10 2984 } ADDR2_COMPUTE_CMASK_INFO_INPUT; 2985 2986 /* DCC addr meta equation for GFX9. */ 2987 struct gfx9_addr_meta_equation { 2988 UINT_8 num_bits; 2989 2990 struct { 2991 struct { 2992 UINT_8 dim; /* 0..4 as index, 5 means invalid */ 2993 UINT_8 ord; /* 0..31 */ 2994 } coord[8]; /* 0..num_coords */ 2995 } bit[32]; /* 0..num_bits */ 2996 2997 UINT_8 numPipeBits; 2998 }; 2999 3000 /** 3001 **************************************************************************************************** 3002 * ADDR2_COMPUTE_CMASK_INFO_OUTPUT 3003 * 3004 * @brief 3005 * Output structure of Addr2ComputeCmaskInfo 3006 **************************************************************************************************** 3007 */ 3008 typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT 3009 { 3010 UINT_32 size; ///< Size of this structure in bytes 3011 3012 UINT_32 pitch; ///< Pitch in pixels of color buffer which 3013 /// this Cmask matches. The size might be larger than 3014 /// original color buffer pitch when called with 3015 /// an unaligned pitch. 3016 UINT_32 height; ///< Height in pixels, as above 3017 UINT_32 baseAlign; ///< Base alignment 3018 UINT_32 sliceSize; ///< Slice size, in bytes. 3019 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer 3020 UINT_32 metaBlkWidth; ///< Meta block width 3021 UINT_32 metaBlkHeight; ///< Meta block height 3022 3023 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3024 3025 ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information 3026 3027 /* The equation for doing CMASK address computations in shaders. */ 3028 union { 3029 /* This is chip-specific, and it varies with: 3030 * - resource type 3031 * - swizzle_mode 3032 * - bpp 3033 * - pipe_aligned 3034 * - rb_aligned 3035 */ 3036 struct gfx9_addr_meta_equation gfx9; 3037 3038 /* This is chip-specific, it requires 64KB_Z_X. */ 3039 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3040 } equation; 3041 } ADDR2_COMPUTE_CMASK_INFO_OUTPUT; 3042 3043 /** 3044 **************************************************************************************************** 3045 * Addr2ComputeCmaskInfo 3046 * 3047 * @brief 3048 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 3049 * info 3050 **************************************************************************************************** 3051 */ 3052 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo( 3053 ADDR_HANDLE hLib, 3054 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 3055 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut); 3056 3057 3058 3059 /** 3060 **************************************************************************************************** 3061 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3062 * 3063 * @brief 3064 * Input structure for Addr2ComputeCmaskAddrFromCoord 3065 * 3066 **************************************************************************************************** 3067 */ 3068 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3069 { 3070 UINT_32 size; ///< Size of this structure in bytes 3071 3072 UINT_32 x; ///< X coordinate 3073 UINT_32 y; ///< Y coordinate 3074 UINT_32 slice; ///< Index of slices 3075 3076 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3077 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3078 AddrResourceType resourceType; ///< Color surface type 3079 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3080 3081 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3082 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3083 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3084 3085 UINT_32 numSamples; ///< Color surfae sample number 3086 UINT_32 numFrags; ///< Color surface fragment number 3087 3088 UINT_32 pipeXor; ///< pipe Xor setting 3089 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 3090 3091 /** 3092 **************************************************************************************************** 3093 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3094 * 3095 * @brief 3096 * Output structure for Addr2ComputeCmaskAddrFromCoord 3097 **************************************************************************************************** 3098 */ 3099 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3100 { 3101 UINT_32 size; ///< Size of this structure in bytes 3102 3103 UINT_64 addr; ///< CMASK address in bytes 3104 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3105 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 3106 3107 /** 3108 **************************************************************************************************** 3109 * Addr2ComputeCmaskAddrFromCoord 3110 * 3111 * @brief 3112 * Compute Cmask address according to coordinates (of MSAA color buffer) 3113 **************************************************************************************************** 3114 */ 3115 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord( 3116 ADDR_HANDLE hLib, 3117 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 3118 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 3119 3120 3121 3122 /** 3123 **************************************************************************************************** 3124 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3125 * 3126 * @brief 3127 * Input structure for Addr2ComputeCmaskCoordFromAddr 3128 **************************************************************************************************** 3129 */ 3130 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3131 { 3132 UINT_32 size; ///< Size of this structure in bytes 3133 3134 UINT_64 addr; ///< CMASK address in bytes 3135 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3136 3137 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3138 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3139 AddrResourceType resourceType; ///< Color surface type 3140 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3141 3142 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3143 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3144 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3145 UINT_32 numMipLevels; ///< Color surface total mipmap levels. 3146 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT; 3147 3148 /** 3149 **************************************************************************************************** 3150 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3151 * 3152 * @brief 3153 * Output structure for Addr2ComputeCmaskCoordFromAddr 3154 **************************************************************************************************** 3155 */ 3156 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3157 { 3158 UINT_32 size; ///< Size of this structure in bytes 3159 3160 UINT_32 x; ///< X coordinate 3161 UINT_32 y; ///< Y coordinate 3162 UINT_32 slice; ///< Index of slices 3163 UINT_32 mipId; ///< mipmap level id 3164 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 3165 3166 /** 3167 **************************************************************************************************** 3168 * Addr2ComputeCmaskCoordFromAddr 3169 * 3170 * @brief 3171 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 3172 * Cmask address 3173 **************************************************************************************************** 3174 */ 3175 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr( 3176 ADDR_HANDLE hLib, 3177 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 3178 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 3179 3180 3181 3182 //////////////////////////////////////////////////////////////////////////////////////////////////// 3183 // F-mask functions for Addr2 3184 //////////////////////////////////////////////////////////////////////////////////////////////////// 3185 3186 /** 3187 **************************************************************************************************** 3188 * ADDR2_FMASK_FLAGS 3189 * 3190 * @brief 3191 * FMASK flags 3192 **************************************************************************************************** 3193 */ 3194 typedef union _ADDR2_FMASK_FLAGS 3195 { 3196 struct 3197 { 3198 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients 3199 /// by H/W clients. S/W should always set it to FALSE. 3200 UINT_32 reserved : 31; ///< Reserved for future use. 3201 }; 3202 3203 UINT_32 value; 3204 } ADDR2_FMASK_FLAGS; 3205 3206 /** 3207 **************************************************************************************************** 3208 * ADDR2_COMPUTE_FMASK_INFO_INPUT 3209 * 3210 * @brief 3211 * Input structure for Addr2ComputeFmaskInfo 3212 **************************************************************************************************** 3213 */ 3214 typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT 3215 { 3216 UINT_32 size; ///< Size of this structure in bytes 3217 3218 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3219 UINT_32 unalignedWidth; ///< Color surface original width 3220 UINT_32 unalignedHeight; ///< Color surface original height 3221 UINT_32 numSlices; ///< Number of slices/depth 3222 UINT_32 numSamples; ///< Number of samples 3223 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3224 /// number of samples for normal AA; Set it to the 3225 /// number of fragments for EQAA 3226 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3227 } ADDR2_COMPUTE_FMASK_INFO_INPUT; 3228 3229 /** 3230 **************************************************************************************************** 3231 * ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3232 * 3233 * @brief 3234 * Output structure for Addr2ComputeFmaskInfo 3235 **************************************************************************************************** 3236 */ 3237 typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3238 { 3239 UINT_32 size; ///< Size of this structure in bytes 3240 3241 UINT_32 pitch; ///< Pitch of fmask in pixels 3242 UINT_32 height; ///< Height of fmask in pixels 3243 UINT_32 baseAlign; ///< Base alignment 3244 UINT_32 numSlices; ///< Slices of fmask 3245 UINT_32 fmaskBytes; ///< Size of fmask in bytes 3246 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 3247 UINT_32 numSamples; ///< Number of samples 3248 UINT_32 sliceSize; ///< Size of slice in bytes 3249 } ADDR2_COMPUTE_FMASK_INFO_OUTPUT; 3250 3251 /** 3252 **************************************************************************************************** 3253 * Addr2ComputeFmaskInfo 3254 * 3255 * @brief 3256 * Compute Fmask pitch/height/slices/alignments and size in bytes 3257 **************************************************************************************************** 3258 */ 3259 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo( 3260 ADDR_HANDLE hLib, 3261 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 3262 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 3263 3264 3265 3266 /** 3267 **************************************************************************************************** 3268 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3269 * 3270 * @brief 3271 * Input structure for Addr2ComputeFmaskAddrFromCoord 3272 **************************************************************************************************** 3273 */ 3274 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3275 { 3276 UINT_32 size; ///< Size of this structure in bytes 3277 3278 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3279 UINT_32 x; ///< X coordinate 3280 UINT_32 y; ///< Y coordinate 3281 UINT_32 slice; ///< Slice index 3282 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3283 UINT_32 plane; ///< Plane number 3284 3285 UINT_32 unalignedWidth; ///< Color surface original width 3286 UINT_32 unalignedHeight; ///< Color surface original height 3287 UINT_32 numSamples; ///< Number of samples 3288 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3289 /// number of samples for normal AA; Set it to the 3290 /// number of fragments for EQAA 3291 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3292 3293 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3294 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 3295 3296 /** 3297 **************************************************************************************************** 3298 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3299 * 3300 * @brief 3301 * Output structure for Addr2ComputeFmaskAddrFromCoord 3302 **************************************************************************************************** 3303 */ 3304 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3305 { 3306 UINT_32 size; ///< Size of this structure in bytes 3307 3308 UINT_64 addr; ///< Fmask address 3309 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 3310 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 3311 3312 /** 3313 **************************************************************************************************** 3314 * Addr2ComputeFmaskAddrFromCoord 3315 * 3316 * @brief 3317 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 3318 **************************************************************************************************** 3319 */ 3320 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord( 3321 ADDR_HANDLE hLib, 3322 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 3323 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 3324 3325 3326 3327 /** 3328 **************************************************************************************************** 3329 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3330 * 3331 * @brief 3332 * Input structure for Addr2ComputeFmaskCoordFromAddr 3333 **************************************************************************************************** 3334 */ 3335 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3336 { 3337 UINT_32 size; ///< Size of this structure in bytes 3338 3339 UINT_64 addr; ///< Address 3340 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 3341 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3342 3343 UINT_32 unalignedWidth; ///< Color surface original width 3344 UINT_32 unalignedHeight; ///< Color surface original height 3345 UINT_32 numSamples; ///< Number of samples 3346 UINT_32 numFrags; ///< Number of fragments 3347 3348 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3349 3350 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3351 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT; 3352 3353 /** 3354 **************************************************************************************************** 3355 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3356 * 3357 * @brief 3358 * Output structure for Addr2ComputeFmaskCoordFromAddr 3359 **************************************************************************************************** 3360 */ 3361 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3362 { 3363 UINT_32 size; ///< Size of this structure in bytes 3364 3365 UINT_32 x; ///< X coordinate 3366 UINT_32 y; ///< Y coordinate 3367 UINT_32 slice; ///< Slice index 3368 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3369 UINT_32 plane; ///< Plane number 3370 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 3371 3372 /** 3373 **************************************************************************************************** 3374 * Addr2ComputeFmaskCoordFromAddr 3375 * 3376 * @brief 3377 * Compute FMASK coordinate from an given address 3378 **************************************************************************************************** 3379 */ 3380 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr( 3381 ADDR_HANDLE hLib, 3382 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 3383 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 3384 3385 3386 3387 //////////////////////////////////////////////////////////////////////////////////////////////////// 3388 // DCC key functions for Addr2 3389 //////////////////////////////////////////////////////////////////////////////////////////////////// 3390 3391 /** 3392 **************************************************************************************************** 3393 * _ADDR2_COMPUTE_DCCINFO_INPUT 3394 * 3395 * @brief 3396 * Input structure of Addr2ComputeDccInfo 3397 **************************************************************************************************** 3398 */ 3399 typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT 3400 { 3401 UINT_32 size; ///< Size of this structure in bytes 3402 3403 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags 3404 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3405 AddrResourceType resourceType; ///< Color surface type 3406 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3407 UINT_32 bpp; ///< bits per pixel 3408 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3409 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3410 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0) 3411 UINT_32 numFrags; ///< Fragment number of color surface 3412 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 3413 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels 3414 ///< useful in meta linear case 3415 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3416 /// it should be number of mip levels 3417 /// Only for GFX10 3418 } ADDR2_COMPUTE_DCCINFO_INPUT; 3419 3420 /** 3421 **************************************************************************************************** 3422 * ADDR2_COMPUTE_DCCINFO_OUTPUT 3423 * 3424 * @brief 3425 * Output structure of Addr2ComputeDccInfo 3426 **************************************************************************************************** 3427 */ 3428 typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT 3429 { 3430 UINT_32 size; ///< Size of this structure in bytes 3431 3432 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 3433 UINT_32 dccRamSize; ///< Size of dcc key 3434 3435 UINT_32 pitch; ///< DCC surface mip chain pitch 3436 UINT_32 height; ///< DCC surface mip chain height 3437 UINT_32 depth; ///< DCC surface mip chain depth 3438 3439 UINT_32 compressBlkWidth; ///< DCC compress block width 3440 UINT_32 compressBlkHeight; ///< DCC compress block height 3441 UINT_32 compressBlkDepth; ///< DCC compress block depth 3442 3443 UINT_32 metaBlkWidth; ///< DCC meta block width 3444 UINT_32 metaBlkHeight; ///< DCC meta block height 3445 UINT_32 metaBlkDepth; ///< DCC meta block depth 3446 UINT_32 metaBlkSize; ///< DCC meta block size in bytes 3447 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3448 3449 union 3450 { 3451 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared 3452 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's 3453 /// the slize size of a mip chain, the thickness of a 3454 /// a slice is meta block depth 3455 /// Only for GFX10 3456 }; 3457 3458 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information 3459 3460 /* The equation for doing DCC address computations in shaders. */ 3461 union { 3462 /* This is chip-specific, and it varies with: 3463 * - resource type 3464 * - swizzle_mode 3465 * - bpp 3466 * - number of fragments 3467 * - pipe_aligned 3468 * - rb_aligned 3469 */ 3470 struct gfx9_addr_meta_equation gfx9; 3471 3472 /* This is chip-specific, it requires 64KB_R_X, and it varies with: 3473 * - bpp 3474 * - pipe_aligned 3475 */ 3476 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3477 } equation; 3478 } ADDR2_COMPUTE_DCCINFO_OUTPUT; 3479 3480 /** 3481 **************************************************************************************************** 3482 * Addr2ComputeDccInfo 3483 * 3484 * @brief 3485 * Compute DCC key size, base alignment 3486 * info 3487 **************************************************************************************************** 3488 */ 3489 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo( 3490 ADDR_HANDLE hLib, 3491 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 3492 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut); 3493 3494 3495 /** 3496 **************************************************************************************************** 3497 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3498 * 3499 * @brief 3500 * Input structure for Addr2ComputeDccAddrFromCoord 3501 * 3502 **************************************************************************************************** 3503 */ 3504 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3505 { 3506 UINT_32 size; ///< Size of this structure in bytes 3507 3508 UINT_32 x; ///< X coordinate 3509 UINT_32 y; ///< Y coordinate 3510 UINT_32 slice; ///< Index of slices 3511 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 3512 UINT_32 mipId; ///< mipmap level id 3513 3514 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags 3515 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3516 AddrResourceType resourceType; ///< Color surface type 3517 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3518 UINT_32 bpp; ///< Color surface bits per pixel 3519 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3520 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3521 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3522 UINT_32 numMipLevels; ///< Color surface mipmap levels 3523 UINT_32 numFrags; ///< Color surface fragment number 3524 3525 UINT_32 pipeXor; ///< pipe Xor setting 3526 UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch 3527 UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height 3528 UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth 3529 UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight 3530 UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth 3531 UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth 3532 UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight 3533 UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth 3534 UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize 3535 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT; 3536 3537 /** 3538 **************************************************************************************************** 3539 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3540 * 3541 * @brief 3542 * Output structure for Addr2ComputeDccAddrFromCoord 3543 **************************************************************************************************** 3544 */ 3545 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3546 { 3547 UINT_32 size; ///< Size of this structure in bytes 3548 3549 UINT_64 addr; ///< DCC address in bytes 3550 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT; 3551 3552 /** 3553 **************************************************************************************************** 3554 * Addr2ComputeDccAddrFromCoord 3555 * 3556 * @brief 3557 * Compute DCC address according to coordinates (of MSAA color buffer) 3558 **************************************************************************************************** 3559 */ 3560 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord( 3561 ADDR_HANDLE hLib, 3562 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 3563 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 3564 3565 //////////////////////////////////////////////////////////////////////////////////////////////////// 3566 // Misc functions for Addr2 3567 //////////////////////////////////////////////////////////////////////////////////////////////////// 3568 3569 /** 3570 **************************************************************************************************** 3571 * ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3572 * 3573 * @brief 3574 * Input structure of Addr2ComputePipebankXor 3575 **************************************************************************************************** 3576 */ 3577 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3578 { 3579 UINT_32 size; ///< Size of this structure in bytes 3580 UINT_32 surfIndex; ///< Input surface index 3581 ADDR2_SURFACE_FLAGS flags; ///< Surface flag 3582 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3583 AddrResourceType resourceType; ///< Surface resource type 3584 AddrFormat format; ///< Surface format 3585 UINT_32 numSamples; ///< Number of samples 3586 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3587 /// number of samples for normal AA; Set it to the 3588 /// number of fragments for EQAA 3589 } ADDR2_COMPUTE_PIPEBANKXOR_INPUT; 3590 3591 /** 3592 **************************************************************************************************** 3593 * ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3594 * 3595 * @brief 3596 * Output structure of Addr2ComputePipebankXor 3597 **************************************************************************************************** 3598 */ 3599 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3600 { 3601 UINT_32 size; ///< Size of this structure in bytes 3602 UINT_32 pipeBankXor; ///< Pipe bank xor 3603 } ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT; 3604 3605 /** 3606 **************************************************************************************************** 3607 * Addr2ComputePipeBankXor 3608 * 3609 * @brief 3610 * Calculate a valid bank pipe xor value for client to use. 3611 **************************************************************************************************** 3612 */ 3613 ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor( 3614 ADDR_HANDLE hLib, 3615 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 3616 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 3617 3618 /** 3619 **************************************************************************************************** 3620 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3621 * 3622 * @brief 3623 * Input structure of Addr2ComputeSlicePipeBankXor 3624 **************************************************************************************************** 3625 */ 3626 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3627 { 3628 UINT_32 size; ///< Size of this structure in bytes 3629 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3630 AddrResourceType resourceType; ///< Surface resource type 3631 UINT_32 bpe; ///< bits per element (e.g. block size for BCn format) 3632 UINT_32 basePipeBankXor; ///< Base pipe bank xor 3633 UINT_32 slice; ///< Slice id 3634 UINT_32 numSamples; ///< Number of samples 3635 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 3636 3637 /** 3638 **************************************************************************************************** 3639 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3640 * 3641 * @brief 3642 * Output structure of Addr2ComputeSlicePipeBankXor 3643 **************************************************************************************************** 3644 */ 3645 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3646 { 3647 UINT_32 size; ///< Size of this structure in bytes 3648 UINT_32 pipeBankXor; ///< Pipe bank xor 3649 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 3650 3651 /** 3652 **************************************************************************************************** 3653 * Addr2ComputeSlicePipeBankXor 3654 * 3655 * @brief 3656 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 3657 **************************************************************************************************** 3658 */ 3659 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor( 3660 ADDR_HANDLE hLib, 3661 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 3662 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 3663 3664 /** 3665 **************************************************************************************************** 3666 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3667 * 3668 * @brief 3669 * Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3670 **************************************************************************************************** 3671 */ 3672 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3673 { 3674 UINT_32 size; ///< Size of this structure in bytes 3675 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3676 AddrResourceType resourceType; ///< Surface resource type 3677 UINT_32 pipeBankXor; ///< Per resource xor 3678 UINT_32 slice; ///< Slice id 3679 UINT_64 sliceSize; ///< Slice size of a mip chain 3680 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO 3681 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO 3682 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 3683 3684 /** 3685 **************************************************************************************************** 3686 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3687 * 3688 * @brief 3689 * Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3690 **************************************************************************************************** 3691 */ 3692 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3693 { 3694 UINT_32 size; ///< Size of this structure in bytes 3695 UINT_64 offset; ///< offset 3696 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 3697 3698 /** 3699 **************************************************************************************************** 3700 * Addr2ComputeSubResourceOffsetForSwizzlePattern 3701 * 3702 * @brief 3703 * Calculate sub resource offset to support swizzle pattern. 3704 **************************************************************************************************** 3705 */ 3706 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern( 3707 ADDR_HANDLE hLib, 3708 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 3709 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 3710 3711 /** 3712 **************************************************************************************************** 3713 * ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3714 * 3715 * @brief 3716 * Input structure of Addr2ComputeNonBlockCompressedView 3717 **************************************************************************************************** 3718 */ 3719 typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3720 { 3721 UINT_32 size; ///< Size of this structure in bytes 3722 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3723 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Addr2 3724 AddrResourceType resourceType; ///< Surface type 3725 AddrFormat format; ///< Surface format 3726 UINT_32 width; ///< Width of mip0 in texels (not in compressed block) 3727 UINT_32 height; ///< Height of mip0 in texels (not in compressed block) 3728 UINT_32 numSlices; ///< Number surface slice/depth of mip0 3729 UINT_32 numMipLevels; ///< Total mipmap levels. 3730 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 3731 UINT_32 slice; ///< Index of slice to view 3732 UINT_32 mipId; ///< Id of mip to view 3733 } ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT; 3734 3735 /** 3736 **************************************************************************************************** 3737 * ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3738 * 3739 * @brief 3740 * Output structure of Addr2ComputeNonBlockCompressedView 3741 **************************************************************************************************** 3742 */ 3743 typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3744 { 3745 UINT_32 size; ///< Size of this structure in bytes 3746 UINT_64 offset; ///< Offset shifted from resource base for the view 3747 UINT_32 pipeBankXor; ///< Pipe bank xor for the view 3748 UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view 3749 UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view 3750 UINT_32 numMipLevels; ///< Total mipmap levels for the view 3751 UINT_32 mipId; ///< Mip ID for the view 3752 } ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT; 3753 3754 /** 3755 **************************************************************************************************** 3756 * Addr2ComputeNonBlockCompressedView 3757 * 3758 * @brief 3759 * Compute non-block-compressed view for a given mipmap level/slice 3760 **************************************************************************************************** 3761 */ 3762 ADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView( 3763 ADDR_HANDLE hLib, 3764 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 3765 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 3766 3767 /** 3768 **************************************************************************************************** 3769 * ADDR2_BLOCK_SET 3770 * 3771 * @brief 3772 * Bit field that defines block type 3773 **************************************************************************************************** 3774 */ 3775 typedef union _ADDR2_BLOCK_SET 3776 { 3777 struct 3778 { 3779 UINT_32 micro : 1; // 256B block for 2D resource 3780 UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource 3781 UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource 3782 UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource 3783 UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource 3784 UINT_32 var : 1; // VAR block 3785 UINT_32 : 1; 3786 UINT_32 linear : 1; // Linear block 3787 UINT_32 reserved : 24; 3788 }; 3789 3790 struct 3791 { 3792 UINT_32 : 5; 3793 UINT_32 thin256KB : 1; // Thin 256KB block 3794 UINT_32 thick256KB : 1; // Thick 256KB block 3795 UINT_32 : 25; 3796 } gfx11; 3797 3798 UINT_32 value; 3799 } ADDR2_BLOCK_SET; 3800 3801 /** 3802 **************************************************************************************************** 3803 * ADDR2_SWTYPE_SET 3804 * 3805 * @brief 3806 * Bit field that defines swizzle type 3807 **************************************************************************************************** 3808 */ 3809 typedef union _ADDR2_SWTYPE_SET 3810 { 3811 struct 3812 { 3813 UINT_32 sw_Z : 1; // SW_*_Z_* 3814 UINT_32 sw_S : 1; // SW_*_S_* 3815 UINT_32 sw_D : 1; // SW_*_D_* 3816 UINT_32 sw_R : 1; // SW_*_R_* 3817 UINT_32 reserved : 28; 3818 }; 3819 3820 UINT_32 value; 3821 } ADDR2_SWTYPE_SET; 3822 3823 /** 3824 **************************************************************************************************** 3825 * ADDR2_SWMODE_SET 3826 * 3827 * @brief 3828 * Bit field that defines swizzle type 3829 **************************************************************************************************** 3830 */ 3831 typedef union _ADDR2_SWMODE_SET 3832 { 3833 struct 3834 { 3835 UINT_32 swLinear : 1; 3836 UINT_32 sw256B_S : 1; 3837 UINT_32 sw256B_D : 1; 3838 UINT_32 sw256B_R : 1; 3839 UINT_32 sw4KB_Z : 1; 3840 UINT_32 sw4KB_S : 1; 3841 UINT_32 sw4KB_D : 1; 3842 UINT_32 sw4KB_R : 1; 3843 UINT_32 sw64KB_Z : 1; 3844 UINT_32 sw64KB_S : 1; 3845 UINT_32 sw64KB_D : 1; 3846 UINT_32 sw64KB_R : 1; 3847 UINT_32 swMiscDef12 : 1; 3848 UINT_32 swMiscDef13 : 1; 3849 UINT_32 swMiscDef14 : 1; 3850 UINT_32 swMiscDef15 : 1; 3851 UINT_32 sw64KB_Z_T : 1; 3852 UINT_32 sw64KB_S_T : 1; 3853 UINT_32 sw64KB_D_T : 1; 3854 UINT_32 sw64KB_R_T : 1; 3855 UINT_32 sw4KB_Z_X : 1; 3856 UINT_32 sw4KB_S_X : 1; 3857 UINT_32 sw4KB_D_X : 1; 3858 UINT_32 sw4KB_R_X : 1; 3859 UINT_32 sw64KB_Z_X : 1; 3860 UINT_32 sw64KB_S_X : 1; 3861 UINT_32 sw64KB_D_X : 1; 3862 UINT_32 sw64KB_R_X : 1; 3863 UINT_32 swMiscDef28 : 1; 3864 UINT_32 swMiscDef29 : 1; 3865 UINT_32 swMiscDef30 : 1; 3866 UINT_32 swMiscDef31 : 1; 3867 }; 3868 3869 struct 3870 { 3871 UINT_32 : 28; 3872 UINT_32 swVar_Z_X : 1; 3873 UINT_32 : 2; 3874 UINT_32 swVar_R_X : 1; 3875 } gfx10; 3876 3877 struct 3878 { 3879 UINT_32 : 28; 3880 UINT_32 sw256KB_Z_X : 1; 3881 UINT_32 sw256KB_S_X : 1; 3882 UINT_32 sw256KB_D_X : 1; 3883 UINT_32 sw256KB_R_X : 1; 3884 } gfx11; 3885 3886 UINT_32 value; 3887 } ADDR2_SWMODE_SET; 3888 3889 /** 3890 **************************************************************************************************** 3891 * ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3892 * 3893 * @brief 3894 * Input structure of Addr2GetPreferredSurfaceSetting 3895 **************************************************************************************************** 3896 */ 3897 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3898 { 3899 UINT_32 size; ///< Size of this structure in bytes 3900 3901 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3902 AddrResourceType resourceType; ///< Surface type 3903 AddrFormat format; ///< Surface format 3904 AddrResrouceLocation resourceLoction; ///< Surface heap choice 3905 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting 3906 ///< such as linear for DXTn, tiled for YUV 3907 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted 3908 BOOL_32 noXor; ///< Do not use xor mode for this resource 3909 UINT_32 bpp; ///< bits per pixel 3910 UINT_32 width; ///< Width (of mip0), in pixels 3911 UINT_32 height; ///< Height (of mip0), in pixels 3912 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 3913 UINT_32 numMipLevels; ///< Total mipmap levels. 3914 UINT_32 numSamples; ///< Number of samples 3915 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3916 /// number of samples for normal AA; Set it to the 3917 /// number of fragments for EQAA 3918 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 3919 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will 3920 /// be padded to multiple of this value (in bytes) 3921 DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible 3922 /// size. 3923 } ADDR2_GET_PREFERRED_SURF_SETTING_INPUT; 3924 3925 /** 3926 **************************************************************************************************** 3927 * ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3928 * 3929 * @brief 3930 * Output structure of Addr2GetPreferredSurfaceSetting 3931 **************************************************************************************************** 3932 */ 3933 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3934 { 3935 UINT_32 size; ///< Size of this structure in bytes 3936 3937 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used 3938 AddrResourceType resourceType; ///< Suggested resource type to program HW 3939 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination 3940 BOOL_32 canXor; ///< If client can use xor on a valid macro block 3941 /// type 3942 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination 3943 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination 3944 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination 3945 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT; 3946 3947 /** 3948 **************************************************************************************************** 3949 * Addr2GetPreferredSurfaceSetting 3950 * 3951 * @brief 3952 * Suggest a preferred setting for client driver to program HW register 3953 **************************************************************************************************** 3954 */ 3955 ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting( 3956 ADDR_HANDLE hLib, 3957 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3958 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3959 3960 /** 3961 **************************************************************************************************** 3962 * Addr2GetPossibleSwizzleModes 3963 * 3964 * @brief 3965 * Returns a list of swizzle modes that are valid from the hardware's perspective for the 3966 * client to choose from 3967 **************************************************************************************************** 3968 */ 3969 ADDR_E_RETURNCODE ADDR_API Addr2GetPossibleSwizzleModes( 3970 ADDR_HANDLE hLib, 3971 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3972 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3973 3974 /** 3975 **************************************************************************************************** 3976 * Addr2IsValidDisplaySwizzleMode 3977 * 3978 * @brief 3979 * Return whether the swizzle mode is supported by display engine 3980 **************************************************************************************************** 3981 */ 3982 ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode( 3983 ADDR_HANDLE hLib, 3984 AddrSwizzleMode swizzleMode, 3985 UINT_32 bpp, 3986 BOOL_32 *pResult); 3987 3988 /** 3989 **************************************************************************************************** 3990 * Addr2GetAllowedBlockSet 3991 * 3992 * @brief 3993 * Returns the set of allowed block sizes given the allowed swizzle modes and resource type 3994 **************************************************************************************************** 3995 */ 3996 ADDR_E_RETURNCODE ADDR_API Addr2GetAllowedBlockSet( 3997 ADDR_HANDLE hLib, 3998 ADDR2_SWMODE_SET allowedSwModeSet, 3999 AddrResourceType rsrcType, 4000 ADDR2_BLOCK_SET* pAllowedBlockSet); 4001 4002 /** 4003 **************************************************************************************************** 4004 * Addr2GetAllowedSwSet 4005 * 4006 * @brief 4007 * Returns the set of allowed swizzle types given the allowed swizzle modes 4008 **************************************************************************************************** 4009 */ 4010 ADDR_E_RETURNCODE ADDR_API Addr2GetAllowedSwSet( 4011 ADDR_HANDLE hLib, 4012 ADDR2_SWMODE_SET allowedSwModeSet, 4013 ADDR2_SWTYPE_SET* pAllowedSwSet); 4014 4015 /** 4016 **************************************************************************************************** 4017 * Addr2IsBlockTypeAvailable 4018 * 4019 * @brief 4020 * Determine whether a block type is allowed in a given blockSet 4021 **************************************************************************************************** 4022 */ 4023 BOOL_32 Addr2IsBlockTypeAvailable(ADDR2_BLOCK_SET blockSet, AddrBlockType blockType); 4024 4025 /** 4026 **************************************************************************************************** 4027 * Addr2BlockTypeWithinMemoryBudget 4028 * 4029 * @brief 4030 * Determine whether a new block type is acceptable based on memory waste ratio. Will favor 4031 * larger block types. 4032 **************************************************************************************************** 4033 */ 4034 BOOL_32 Addr2BlockTypeWithinMemoryBudget( 4035 UINT_64 minSize, 4036 UINT_64 newBlockTypeSize, 4037 UINT_32 ratioLow, 4038 UINT_32 ratioHi, 4039 #if defined(__cplusplus) 4040 DOUBLE memoryBudget = 0.0f, 4041 BOOL_32 newBlockTypeBigger = TRUE); 4042 #else 4043 DOUBLE memoryBudget, 4044 BOOL_32 newBlockTypeBigger); 4045 #endif 4046 4047 /** 4048 **************************************************************************************************** 4049 * ADDR3_SURFACE_FLAGS 4050 * 4051 * @brief 4052 * Surface flags 4053 **************************************************************************************************** 4054 */ 4055 typedef union _ADDR3_SURFACE_FLAGS 4056 { 4057 struct 4058 { 4059 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 4060 UINT_32 depth : 1; ///< This resource is a depth buffer, can be used with DSV 4061 UINT_32 stencil : 1; ///< This resource is a stencil buffer, can be used with DSV 4062 UINT_32 texture : 1; ///< This resource can be used with SRV 4063 UINT_32 unordered : 1; ///< This resource can be used with UAV 4064 UINT_32 hiZHiS : 1; 4065 UINT_32 blockCompressed : 1; 4066 UINT_32 nv12 : 1; 4067 UINT_32 p010 : 1; 4068 UINT_32 view3dAs2dArray : 1; 4069 UINT_32 isVrsImage : 1; ///< This resource is a VRS source image 4070 UINT_32 reserved1 : 2; 4071 UINT_32 denseSliceExact : 1; ///< Pad dimensions such that 4072 /// Pow2Align(pitch*height, surfAlign)==pitch*height 4073 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 4074 UINT_32 display : 1; ///< This resource is displayable, can be used with DRV 4075 UINT_32 reserved : 16; ///< Reserved bits 4076 }; 4077 4078 UINT_32 value; 4079 } ADDR3_SURFACE_FLAGS; 4080 4081 /** 4082 **************************************************************************************************** 4083 * ADDR3_COMPUTE_SURFACE_INFO_INPUT 4084 * 4085 * @brief 4086 * Input structure for Addr3ComputeSurfaceInfo 4087 **************************************************************************************************** 4088 */ 4089 typedef struct _ADDR3_COMPUTE_SURFACE_INFO_INPUT 4090 { 4091 UINT_32 size; ///< Size of this structure in bytes 4092 4093 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4094 Addr3SwizzleMode swizzleMode; ///< Swizzle Mode for Gfx12 4095 AddrResourceType resourceType; ///< Surface type 4096 AddrFormat format; ///< Surface format 4097 UINT_32 bpp; ///< bits per pixel 4098 UINT_32 width; ///< Width (of mip0), in pixels 4099 UINT_32 height; ///< Height (of mip0), in pixels 4100 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 4101 UINT_32 numMipLevels; ///< Total mipmap levels. 4102 UINT_32 numSamples; ///< Number of samples 4103 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 4104 UINT_32 sliceAlign; ///< Required slice size in bytes 4105 } ADDR3_COMPUTE_SURFACE_INFO_INPUT; 4106 4107 /** 4108 **************************************************************************************************** 4109 * ADDR3_MIP_INFO 4110 * 4111 * @brief 4112 * Structure that contains information for mip level 4113 * 4114 **************************************************************************************************** 4115 */ 4116 typedef struct _ADDR3_MIP_INFO 4117 { 4118 UINT_32 pitch; ///< Pitch in elements of image data 4119 UINT_32 pitchForSlice; ///< Pitch in elements used to compute slice size 4120 UINT_32 height; ///< Padded height in elements 4121 UINT_32 depth; ///< Padded depth 4122 UINT_32 pixelPitch; ///< Pitch in pixels for image data 4123 UINT_32 pixelHeight; ///< Padded height in pixels 4124 UINT_32 equationIndex; ///< Equation index in the equation table 4125 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 4126 ///< to setup vam surface descriptor, can't be used 4127 ///< to setup swizzle pattern 4128 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 4129 UINT_32 mipTailOffset; ///< mip tail offset in bytes 4130 UINT_32 mipTailCoordX; ///< mip tail coord x 4131 UINT_32 mipTailCoordY; ///< mip tail coord y 4132 UINT_32 mipTailCoordZ; ///< mip tail coord z 4133 } ADDR3_MIP_INFO; 4134 4135 /** 4136 **************************************************************************************************** 4137 * ADDR3_COMPUTE_SURFACE_INFO_OUTPUT 4138 * 4139 * @brief 4140 * Output structure for Addr3ComputeSurfaceInfo 4141 * @note 4142 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 4143 Pixel: Original pixel 4144 **************************************************************************************************** 4145 */ 4146 typedef struct _ADDR3_COMPUTE_SURFACE_INFO_OUTPUT 4147 { 4148 UINT_32 size; ///< Size of this structure in bytes 4149 UINT_32 pitch; ///< Pitch in elements for image data 4150 UINT_32 pitchForSlice; ///< Pitch in elements used to compute slice size 4151 UINT_32 pixelPitch; ///< Pitch in original pixels 4152 UINT_32 pixelHeight; ///< Height in original pixels 4153 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 4154 UINT_32 bpp; ///< Bits per elements 4155 /// (e.g. blocks for BCn, 1/3 for 96bit) 4156 UINT_32 numSlices; ///< Padded depth for 3d resource 4157 /// or padded number of slices for 2d array resource 4158 UINT_32 height; ///< Padded height (of mip0) in elements 4159 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 4160 UINT_64 sliceSizeDensePacked; ///< Slice (total mip chain) size of image data in bytes 4161 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 4162 UINT_32 baseAlign; ///< Base address alignment 4163 ADDR_EXTENT3D blockExtent; ///< Dimensions in element inside one block 4164 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 4165 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 4166 ADDR3_MIP_INFO* pMipInfo; ///< Info regarding the start, sizes of the mip levels 4167 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 4168 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 4169 /// in tail, it will be set to number of mip levels 4170 /// Stereo info 4171 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 4172 } ADDR3_COMPUTE_SURFACE_INFO_OUTPUT; 4173 4174 /** 4175 **************************************************************************************************** 4176 * ADDR3_SWMODE_SET 4177 * 4178 * @brief 4179 * Bit field that defines swizzle type 4180 **************************************************************************************************** 4181 */ 4182 // The bit order MUST be the same as Addr3SwizzleMode enumerations, otherwise using bitset to enable 4183 // or disable swizzle modes will be problematic. 4184 typedef union _ADDR3_SWMODE_SET 4185 { 4186 struct 4187 { 4188 UINT_32 swLinear : 1; 4189 UINT_32 sw2d256B : 1; 4190 UINT_32 sw2d4kB : 1; 4191 UINT_32 sw2d64kB : 1; 4192 UINT_32 sw2d256kB : 1; 4193 UINT_32 sw3d4kB : 1; 4194 UINT_32 sw3d64kB : 1; 4195 UINT_32 sw3d256kB : 1; 4196 UINT_32 reserved1 : 2; 4197 UINT_32 reserved : 22; 4198 }; 4199 4200 UINT_32 value; 4201 } ADDR3_SWMODE_SET; 4202 4203 /** 4204 **************************************************************************************************** 4205 * ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT 4206 * 4207 * @brief 4208 * Input structure of Addr3GetPossibleSwizzleModes 4209 **************************************************************************************************** 4210 */ 4211 typedef struct _ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT 4212 { 4213 UINT_32 size; ///< Size of this structure in bytes 4214 4215 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4216 AddrResourceType resourceType; ///< Surface type 4217 UINT_32 bpp; ///< bits per pixel 4218 UINT_32 width; ///< Width (of mip0), in pixels 4219 UINT_32 height; ///< Height (of mip0), in pixels 4220 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 4221 UINT_32 numMipLevels; ///< Total mipmap levels. 4222 UINT_32 numSamples; ///< Number of samples 4223 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 4224 } ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT; 4225 4226 /** 4227 **************************************************************************************************** 4228 * ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT 4229 * 4230 * @brief 4231 * Output structure of Addr3GetPossibleSwizzleModes 4232 **************************************************************************************************** 4233 */ 4234 typedef struct _ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT 4235 { 4236 UINT_32 size; ///< Size of this structure in bytes 4237 ADDR3_SWMODE_SET validModes; ///< List of valid swizzle modes for this function. 4238 } ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT; 4239 4240 /** 4241 **************************************************************************************************** 4242 * Addr3ComputeSurfaceInfo 4243 * 4244 * @brief 4245 * Compute surface width/height/slices/alignments and suitable tiling mode 4246 **************************************************************************************************** 4247 */ 4248 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSurfaceInfo( 4249 ADDR_HANDLE hLib, 4250 const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn, 4251 ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 4252 4253 /** 4254 **************************************************************************************************** 4255 * Addr3GetPossibleSwizzleModes 4256 * 4257 * @brief 4258 * Returns a list of swizzle modes that are valid from the hardware's perspective for the 4259 * client to choose from 4260 **************************************************************************************************** 4261 */ 4262 ADDR_E_RETURNCODE ADDR_API Addr3GetPossibleSwizzleModes( 4263 ADDR_HANDLE hLib, 4264 const ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT* pIn, 4265 ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT* pOut); 4266 4267 /** 4268 **************************************************************************************************** 4269 * ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 4270 * 4271 * @brief 4272 * Input structure for Addr3ComputeSurfaceAddrFromCoord 4273 **************************************************************************************************** 4274 */ 4275 typedef struct _ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 4276 { 4277 UINT_32 size; ///< Size of this structure in bytes 4278 4279 UINT_32 x; ///< X coordinate 4280 UINT_32 y; ///< Y coordinate 4281 UINT_32 slice; ///< Slice index 4282 UINT_32 sample; ///< Sample index, use fragment index for EQAA 4283 UINT_32 mipId; ///< the mip ID in mip chain 4284 4285 Addr3SwizzleMode swizzleMode; ///< Swizzle mode for Gfx12 4286 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4287 AddrResourceType resourceType; ///< Surface type 4288 UINT_32 bpp; ///< Bits per pixel 4289 ADDR_EXTENT3D unAlignedDims; ///< Surface original dimensions (of mip0) 4290 UINT_32 numMipLevels; ///< Total mipmap levels 4291 UINT_32 numSamples; ///< Number of samples 4292 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 4293 } ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 4294 4295 /** 4296 **************************************************************************************************** 4297 * ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 4298 * 4299 * @brief 4300 * Output structure for Addr3ComputeSurfaceAddrFromCoord 4301 **************************************************************************************************** 4302 */ 4303 typedef struct _ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 4304 { 4305 UINT_32 size; ///< Size of this structure in bytes 4306 4307 UINT_64 addr; ///< Byte offset from the image starting address 4308 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 4309 /// For surface bpp < 8, e.g. FMT_1. 4310 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 4311 } ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 4312 4313 /** 4314 **************************************************************************************************** 4315 * Addr3ComputeSurfaceAddrFromCoord 4316 * 4317 * @brief 4318 * Compute surface address from a given coordinate. 4319 **************************************************************************************************** 4320 */ 4321 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSurfaceAddrFromCoord( 4322 ADDR_HANDLE hLib, 4323 const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 4324 ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 4325 4326 /** 4327 **************************************************************************************************** 4328 * ADDR3_COMPUTE_PIPEBANKXOR_INPUT 4329 * 4330 * @brief 4331 * Input structure of Addr3ComputePipebankXor 4332 **************************************************************************************************** 4333 */ 4334 typedef struct _ADDR3_COMPUTE_PIPEBANKXOR_INPUT 4335 { 4336 UINT_32 size; ///< Size of this structure in bytes 4337 UINT_32 surfIndex; ///< Input surface index 4338 Addr3SwizzleMode swizzleMode; ///< Surface swizzle mode 4339 } ADDR3_COMPUTE_PIPEBANKXOR_INPUT; 4340 4341 /** 4342 **************************************************************************************************** 4343 * ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT 4344 * 4345 * @brief 4346 * Output structure of Addr3ComputePipebankXor 4347 **************************************************************************************************** 4348 */ 4349 typedef struct _ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT 4350 { 4351 UINT_32 size; ///< Size of this structure in bytes 4352 UINT_32 pipeBankXor; ///< Pipe bank xor 4353 } ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT; 4354 4355 /** 4356 **************************************************************************************************** 4357 * Addr3ComputePipeBankXor 4358 * 4359 * @brief 4360 * Calculate a valid bank pipe xor value for client to use. 4361 **************************************************************************************************** 4362 */ 4363 ADDR_E_RETURNCODE ADDR_API Addr3ComputePipeBankXor( 4364 ADDR_HANDLE hLib, 4365 const ADDR3_COMPUTE_PIPEBANKXOR_INPUT* pIn, 4366 ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 4367 4368 /** 4369 **************************************************************************************************** 4370 * ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 4371 * 4372 * @brief 4373 * Input structure of Addr3ComputeNonBlockCompressedView 4374 **************************************************************************************************** 4375 */ 4376 typedef struct _ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 4377 { 4378 UINT_32 size; ///< Size of this structure in bytes 4379 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4380 Addr3SwizzleMode swizzleMode; ///< Swizzle Mode for Gfx12 4381 AddrResourceType resourceType; ///< Surface type 4382 AddrFormat format; ///< Surface format 4383 ADDR_EXTENT3D unAlignedDims; ///< Surface original dimensions (of mip0) 4384 UINT_32 numMipLevels; ///< Total mipmap levels. 4385 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 4386 UINT_32 slice; ///< Index of slice to view 4387 UINT_32 mipId; ///< Id of mip to view 4388 } ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT; 4389 4390 /** 4391 **************************************************************************************************** 4392 * ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 4393 * 4394 * @brief 4395 * Output structure of Addr3ComputeNonBlockCompressedView 4396 **************************************************************************************************** 4397 */ 4398 typedef struct _ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 4399 { 4400 UINT_32 size; ///< Size of this structure in bytes 4401 UINT_64 offset; ///< Offset from resource base for the view 4402 UINT_32 pipeBankXor; ///< Pipe bank xor for the view 4403 ADDR_EXTENT3D unAlignedDims; ///< Mip0 dimens (in element) for the view 4404 UINT_32 numMipLevels; ///< Total mipmap levels for the view 4405 UINT_32 mipId; ///< Mip ID for the view 4406 } ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT; 4407 4408 /** 4409 **************************************************************************************************** 4410 * Addr3ComputeNonBlockCompressedView 4411 * 4412 * @brief 4413 * Compute non-block-compressed view for a given mipmap level/slice 4414 **************************************************************************************************** 4415 */ 4416 ADDR_E_RETURNCODE ADDR_API Addr3ComputeNonBlockCompressedView( 4417 ADDR_HANDLE hLib, 4418 const ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 4419 ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 4420 4421 /** 4422 **************************************************************************************************** 4423 * ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 4424 * 4425 * @brief 4426 * Input structure of Addr3ComputeSubResourceOffsetForSwizzlePattern 4427 **************************************************************************************************** 4428 */ 4429 typedef struct _ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 4430 { 4431 UINT_32 size; ///< Size of this structure in bytes 4432 Addr3SwizzleMode swizzleMode; ///< Surface swizzle mode 4433 AddrResourceType resourceType; ///< Surface resource type 4434 UINT_32 pipeBankXor; ///< Per resource xor 4435 UINT_32 slice; ///< Slice id 4436 UINT_64 sliceSize; ///< Slice size of a mip chain 4437 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR3_MIP_INFO 4438 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR3_MIP_INFO 4439 } ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 4440 4441 /** 4442 **************************************************************************************************** 4443 * ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 4444 * 4445 * @brief 4446 * Output structure of Addr3ComputeSubResourceOffsetForSwizzlePattern 4447 **************************************************************************************************** 4448 */ 4449 typedef struct _ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 4450 { 4451 UINT_32 size; ///< Size of this structure in bytes 4452 UINT_64 offset; ///< offset 4453 } ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 4454 4455 /** 4456 **************************************************************************************************** 4457 * Addr3ComputeSubResourceOffsetForSwizzlePattern 4458 * 4459 * @brief 4460 * Calculate sub resource offset to support swizzle pattern. 4461 **************************************************************************************************** 4462 */ 4463 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSubResourceOffsetForSwizzlePattern( 4464 ADDR_HANDLE hLib, 4465 const ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 4466 ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 4467 4468 /** 4469 **************************************************************************************************** 4470 * ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT 4471 * 4472 * @brief 4473 * Input structure of Addr2ComputeSlicePipeBankXor 4474 **************************************************************************************************** 4475 */ 4476 typedef struct _ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT 4477 { 4478 UINT_32 size; ///< Size of this structure in bytes 4479 Addr3SwizzleMode swizzleMode; ///< Surface swizzle mode 4480 AddrResourceType resourceType; ///< Surface resource type 4481 UINT_32 bpe; ///< bits per element (e.g. block size for BCn format) 4482 UINT_32 basePipeBankXor; ///< Base pipe bank xor 4483 UINT_32 slice; ///< Slice id 4484 UINT_32 numSamples; ///< Number of samples 4485 } ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 4486 4487 /** 4488 **************************************************************************************************** 4489 * ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 4490 * 4491 * @brief 4492 * Output structure of Addr3ComputeSlicePipeBankXor 4493 **************************************************************************************************** 4494 */ 4495 typedef struct _ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 4496 { 4497 UINT_32 size; ///< Size of this structure in bytes 4498 UINT_32 pipeBankXor; ///< Pipe bank xor 4499 } ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 4500 4501 /** 4502 **************************************************************************************************** 4503 * Addr3ComputeSlicePipeBankXor 4504 * 4505 * @brief 4506 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 4507 **************************************************************************************************** 4508 */ 4509 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSlicePipeBankXor( 4510 ADDR_HANDLE hLib, 4511 const ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 4512 ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 4513 4514 #if defined(__cplusplus) 4515 } 4516 #endif 4517 4518 #endif // __ADDR_INTERFACE_H__ 4519