1 /* 2 * Copyright (C) 2011 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef SID_H 8 #define SID_H 9 10 #include "amdgfxregs.h" 11 12 /* si values */ 13 #define SI_CONFIG_REG_OFFSET 0x00008000 14 #define SI_CONFIG_REG_END 0x0000B000 15 #define SI_SH_REG_OFFSET 0x0000B000 16 #define SI_SH_REG_END 0x0000C000 17 #define SI_CONTEXT_REG_OFFSET 0x00028000 18 #define SI_CONTEXT_REG_END 0x00030000 19 #define CIK_UCONFIG_REG_OFFSET 0x00030000 20 #define CIK_UCONFIG_REG_END 0x00040000 21 #define SI_UCONFIG_PERF_REG_OFFSET 0x00034000 22 #define SI_UCONFIG_PERF_REG_END 0x00038000 23 24 /* For register shadowing: */ 25 #define SI_SH_REG_SPACE_SIZE (SI_SH_REG_END - SI_SH_REG_OFFSET) 26 #define SI_CONTEXT_REG_SPACE_SIZE (SI_CONTEXT_REG_END - SI_CONTEXT_REG_OFFSET) 27 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET) 28 #define SI_UCONFIG_PERF_REG_SPACE_SIZE (SI_UCONFIG_PERF_REG_END - SI_UCONFIG_PERF_REG_OFFSET) 29 30 #define SI_SHADOWED_SH_REG_OFFSET 0 31 #define SI_SHADOWED_CONTEXT_REG_OFFSET SI_SH_REG_SPACE_SIZE 32 #define SI_SHADOWED_UCONFIG_REG_OFFSET (SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE) 33 #define SI_SHADOWED_REG_BUFFER_SIZE \ 34 (SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE + SI_UCONFIG_REG_SPACE_SIZE) 35 36 /* All registers defined in this packet section don't exist and the only 37 * purpose of these definitions is to define packet encoding that 38 * the IB parser understands, and also to have an accurate documentation. 39 */ 40 #define PKT3_NOP 0x10 41 #define PKT3_SET_BASE 0x11 42 #define PKT3_CLEAR_STATE 0x12 43 #define PKT3_INDEX_BUFFER_SIZE 0x13 44 #define PKT3_DISPATCH_DIRECT 0x15 45 #define PKT3_DISPATCH_INDIRECT 0x16 46 #define PKT3_ATOMIC_MEM 0x1E 47 #define ATOMIC_OP(x) ((unsigned)((x)&0x7f) << 0) 48 #define TC_OP_ATOMIC_SUB_32 0x10 49 #define TC_OP_ATOMIC_CMPSWAP_32 0x48 50 #define ATOMIC_COMMAND(x) ((unsigned)((x)&0x3) << 8) 51 #define ATOMIC_COMMAND_SINGLE_PASS 0x0 52 #define ATOMIC_COMMAND_LOOP 0x1 53 #define PKT3_OCCLUSION_QUERY 0x1F /* GFX7+ */ 54 #define PKT3_SET_PREDICATION 0x20 55 #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) 56 #define PREDICATION_DRAW_VISIBLE (1 << 8) 57 #define PREDICATION_HINT_WAIT (0 << 12) 58 #define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) 59 #define PRED_OP(x) ((x) << 16) 60 #define PREDICATION_OP_CLEAR 0x0 61 #define PREDICATION_OP_ZPASS 0x1 62 #define PREDICATION_OP_PRIMCOUNT 0x2 63 #define PREDICATION_OP_BOOL64 0x3 64 #define PREDICATION_OP_BOOL32 0x4 65 #define PREDICATION_CONTINUE (1 << 31) 66 #define PKT3_COND_EXEC 0x22 67 #define PKT3_PRED_EXEC 0x23 68 #define PKT3_DRAW_INDIRECT 0x24 69 #define PKT3_DRAW_INDEX_INDIRECT 0x25 70 #define PKT3_INDEX_BASE 0x26 71 #define PKT3_DRAW_INDEX_2 0x27 72 #define PKT3_CONTEXT_CONTROL 0x28 73 #define CC0_LOAD_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) 74 #define CC0_LOAD_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) 75 #define CC0_LOAD_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) 76 #define CC0_LOAD_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) 77 #define CC0_LOAD_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) 78 #define CC0_LOAD_CE_RAM(x) (((unsigned)(x)&0x1) << 28) 79 #define CC0_UPDATE_LOAD_ENABLES(x) (((unsigned)(x)&0x1) << 31) 80 #define CC1_SHADOW_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) 81 #define CC1_SHADOW_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) 82 #define CC1_SHADOW_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) 83 #define CC1_SHADOW_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) 84 #define CC1_SHADOW_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) 85 #define CC1_UPDATE_SHADOW_ENABLES(x) (((unsigned)(x)&0x1) << 31) 86 #define PKT3_INDEX_TYPE 0x2A /* GFX6-8 */ 87 #define PKT3_DRAW_INDIRECT_MULTI 0x2C 88 #define R_2C3_DRAW_INDEX_LOC 0x2C3 89 #define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x)&0x1) << 30) 90 #define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x)&0x1) << 31) 91 #define PKT3_DRAW_INDEX_AUTO 0x2D 92 #define PKT3_DRAW_INDEX_IMMD 0x2E /* GFX6 only */ 93 #define PKT3_NUM_INSTANCES 0x2F 94 #define PKT3_DRAW_INDEX_MULTI_AUTO 0x30 95 #define PKT3_INDIRECT_BUFFER_SI 0x32 /* GFX6 only */ 96 #define PKT3_INDIRECT_BUFFER_CONST 0x33 97 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34 98 #define STRMOUT_STORE_BUFFER_FILLED_SIZE 1 99 #define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x)&0x3) << 1) 100 #define STRMOUT_OFFSET_FROM_PACKET 0 101 #define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1 102 #define STRMOUT_OFFSET_FROM_MEM 2 103 #define STRMOUT_OFFSET_NONE 3 104 #define STRMOUT_DATA_TYPE(x) (((unsigned)(x)&0x1) << 7) 105 #define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x)&0x3) << 8) 106 #define PKT3_DRAW_INDEX_OFFSET_2 0x35 107 #define PKT3_WRITE_DATA 0x37 108 #define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38 109 #define PKT3_MEM_SEMAPHORE 0x39 110 #define PKT3_MPEG_INDEX 0x3A /* GFX6 only */ 111 #define PKT3_WAIT_REG_MEM 0x3C 112 #define WAIT_REG_MEM_EQUAL 3 113 #define WAIT_REG_MEM_NOT_EQUAL 4 114 #define WAIT_REG_MEM_GREATER_OR_EQUAL 5 115 #define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x)&0x3) << 4) 116 #define WAIT_REG_MEM_PFP (1 << 8) 117 #define PKT3_MEM_WRITE 0x3D /* GFX6 only */ 118 #define PKT3_INDIRECT_BUFFER 0x3F /* GFX6+ */ 119 #define PKT3_COPY_DATA 0x40 120 #define COPY_DATA_SRC_SEL(x) ((x)&0xf) 121 #define COPY_DATA_REG 0 122 #define COPY_DATA_SRC_MEM 1 /* only valid as source */ 123 #define COPY_DATA_TC_L2 2 124 #define COPY_DATA_GDS 3 125 #define COPY_DATA_PERF 4 126 #define COPY_DATA_IMM 5 127 #define COPY_DATA_TIMESTAMP 9 128 #define COPY_DATA_DST_SEL(x) (((unsigned)(x)&0xf) << 8) 129 #define COPY_DATA_DST_MEM_GRBM 1 /* sync across GRBM, deprecated */ 130 #define COPY_DATA_TC_L2 2 131 #define COPY_DATA_GDS 3 132 #define COPY_DATA_PERF 4 133 #define COPY_DATA_DST_MEM 5 134 #define COPY_DATA_COUNT_SEL (1 << 16) 135 #define COPY_DATA_WR_CONFIRM (1 << 20) 136 #define COPY_DATA_ENGINE_PFP (1 << 30) 137 /* 1. header 138 * 2. SRC_ADDR_LO [31:0] or DATA [31:0] 139 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0] 140 * 4. DST_ADDR_LO [31:0] 141 * 5. DST_ADDR_HI [15:0] 142 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 143 */ 144 #define PKT3_CP_DMA 0x41 /* GFX6 only */ 145 #define PKT3_PFP_SYNC_ME 0x42 146 #define PKT3_SURFACE_SYNC 0x43 /* deprecated on GFX7, use ACQUIRE_MEM */ 147 #define PKT3_ME_INITIALIZE 0x44 /* GFX6 only */ 148 #define PKT3_COND_WRITE 0x45 149 #define PKT3_EVENT_WRITE 0x46 150 #define EVENT_TYPE(x) ((x) << 0) 151 /* 0 - any non-TS event 152 * 1 - ZPASS_DONE 153 * 2 - SAMPLE_PIPELINESTAT 154 * 3 - SAMPLE_STREAMOUTSTAT* 155 * 4 - *S_PARTIAL_FLUSH 156 * 5 - TS events 157 */ 158 #define EVENT_INDEX(x) ((x) << 8) 159 #define PIXEL_PIPE_STATE_CNTL_COUNTER_ID(x) ((x) << 3) 160 #define PIXEL_PIPE_STATE_CNTL_STRIDE(x) ((x) << 9) 161 /* 0 - 32 bits 162 * 1 - 64 bits 163 * 2 - 128 bits 164 * 3 - 256 bits 165 */ 166 #define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(x) ((x) << 11) 167 #define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(x) ((x) >> 21) 168 #define PKT3_EVENT_WRITE_EOP 0x47 /* GFX6-8 */ 169 /* EVENT_WRITE_EOP (GFX6-8) & RELEASE_MEM (GFX9) */ 170 #define EVENT_TCL1_VOL_ACTION_ENA (1 << 12) 171 #define EVENT_TC_VOL_ACTION_ENA (1 << 13) 172 #define EVENT_TC_WB_ACTION_ENA (1 << 15) 173 #define EVENT_TCL1_ACTION_ENA (1 << 16) 174 #define EVENT_TC_ACTION_ENA (1 << 17) 175 #define EVENT_TC_NC_ACTION_ENA (1 << 19) /* GFX9+ */ 176 #define EVENT_TC_WC_ACTION_ENA (1 << 20) /* GFX9+ */ 177 #define EVENT_TC_MD_ACTION_ENA (1 << 21) /* GFX9+ */ 178 #define EOP_DST_SEL(x) ((x) << 16) 179 #define EOP_DST_SEL_MEM 0 180 #define EOP_DST_SEL_TC_L2 1 181 #define EOP_INT_SEL(x) ((x) << 24) 182 #define EOP_INT_SEL_NONE 0 183 #define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3 184 #define EOP_DATA_SEL(x) ((x) << 29) 185 #define EOP_DATA_SEL_DISCARD 0 186 #define EOP_DATA_SEL_VALUE_32BIT 1 187 #define EOP_DATA_SEL_VALUE_64BIT 2 188 #define EOP_DATA_SEL_TIMESTAMP 3 189 #define EOP_DATA_SEL_GDS 5 190 #define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16)) 191 #define PKT3_EVENT_WRITE_EOS 0x48 /* GFX6-8 */ 192 #define EOS_DATA_SEL(x) ((x) << 29) 193 #define EOS_DATA_SEL_APPEND_COUNT 0 194 #define EOS_DATA_SEL_GDS 1 195 #define EOS_DATA_SEL_VALUE_32BIT 2 196 /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets 197 * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and 198 * DST_SEL=MC. Only GFX7 chips are affected. 199 */ 200 #define PKT3_EVENT_WRITE_EOS 0x48 /* GFX6-8, breaks CP DMA */ 201 #define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */ 202 /* 1. header 203 * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0] 204 * 2. SRC_ADDR_LO [31:0] or DATA [31:0] 205 * 3. SRC_ADDR_HI [31:0] 206 * 4. DST_ADDR_LO [31:0] 207 * 5. DST_ADDR_HI [31:0] 208 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 209 */ 210 #define PKT3_DISPATCH_MESH_INDIRECT_MULTI 0x4C /* Indirect mesh shader only dispatch [GFX only], GFX10.3+ */ 211 #define S_4C1_XYZ_DIM_REG(x) ((x & 0xFFFF)) 212 #define S_4C1_DRAW_INDEX_REG(x) ((x & 0xFFFF) << 16) 213 #define S_4C2_DRAW_INDEX_ENABLE(x) ((x & 1) << 31) 214 #define S_4C2_COUNT_INDIRECT_ENABLE(x) ((x & 1) << 30) 215 #define S_4C2_THREAD_TRACE_MARKER_ENABLE(x) ((x & 1) << 29) 216 #define S_4C2_XYZ_DIM_ENABLE(x) ((x & 1) << 28) /* GFX11+ */ 217 #define S_4C2_MODE1_ENABLE(x) ((x & 1) << 27) /* GFX11+ */ 218 #define PKT3_DISPATCH_TASKMESH_GFX 0x4D /* Task + mesh shader dispatch [GFX side], GFX10.3+ */ 219 #define S_4D0_RING_ENTRY_REG(x) ((x & 0xFFFF) << 16) 220 #define S_4D0_XYZ_DIM_REG(x) ((x & 0xFFFF)) 221 #define S_4D1_THREAD_TRACE_MARKER_ENABLE(x) ((x & 1) << 31) 222 #define S_4D1_XYZ_DIM_ENABLE(x) ((x & 1) << 30) /* GFX11+ */ 223 #define S_4D1_MODE1_ENABLE(x) ((x & 1) << 29) /* GFX11+ */ 224 #define S_4D1_LINEAR_DISPATCH_ENABLE(x) ((x & 1) << 28) /* GFX11+ */ 225 #define PKT3_DISPATCH_MESH_DIRECT 0x4E /* Direct mesh shader only dispatch [GFX only], GFX11+ */ 226 #define PKT3_DMA_DATA 0x50 /* GFX7+ */ 227 #define PKT3_CONTEXT_REG_RMW 0x51 /* older firmware versions on older chips don't have this */ 228 #define PKT3_ONE_REG_WRITE 0x57 /* GFX6 only */ 229 #define PKT3_ACQUIRE_MEM 0x58 /* GFX7+ */ 230 #define PKT3_REWIND 0x59 /* GFX8+ [any ring] or GFX7 [compute ring only] */ 231 #define PKT3_PRIME_UTCL2 0x5D 232 #define PKT3_LOAD_UCONFIG_REG 0x5E /* GFX7+ */ 233 #define PKT3_LOAD_SH_REG 0x5F 234 #define PKT3_LOAD_CONTEXT_REG 0x61 235 #define PKT3_LOAD_SH_REG_INDEX 0x63 /* GFX8+ */ 236 #define PKT3_SET_CONFIG_REG 0x68 237 #define PKT3_SET_CONTEXT_REG 0x69 238 #define PKT3_SET_SH_REG 0x76 239 #define PKT3_SET_SH_REG_OFFSET 0x77 240 #define PKT3_SET_UCONFIG_REG 0x79 /* GFX7+ */ 241 #define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */ 242 #define PKT3_LOAD_CONST_RAM 0x80 243 #define PKT3_WRITE_CONST_RAM 0x81 244 #define PKT3_DUMP_CONST_RAM 0x83 245 #define PKT3_INCREMENT_CE_COUNTER 0x84 246 #define PKT3_INCREMENT_DE_COUNTER 0x85 247 #define PKT3_WAIT_ON_CE_COUNTER 0x86 248 #define PKT3_SET_SH_REG_INDEX 0x9B 249 #define PKT3_LOAD_CONTEXT_REG_INDEX 0x9F /* GFX8+ */ 250 #define PKT3_DISPATCH_DIRECT_INTERLEAVED 0xA7 /* GFX12+ */ 251 #define PKT3_DISPATCH_INDIRECT_INTERLEAVED 0xA8 /* GFX12+ */ 252 #define PKT3_DISPATCH_TASK_STATE_INIT 0xA9 /* Tells the HW about the task control buffer, GFX10.3+ */ 253 #define PKT3_DISPATCH_TASKMESH_DIRECT_ACE 0xAA /* Direct task + mesh shader dispatch [ACE side], GFX10.3+ */ 254 #define PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE 0xAD /* Indirect task + mesh shader dispatch [ACE side], GFX10.3+ */ 255 #define S_AD2_RING_ENTRY_REG(x) ((x & 0xFFFF)) 256 #define S_AD3_COUNT_INDIRECT_ENABLE(x) ((x & 1) << 1) 257 #define S_AD3_DRAW_INDEX_ENABLE(x) ((x & 1) << 2) 258 #define S_AD3_XYZ_DIM_ENABLE(x) ((x & 1) << 3) 259 #define S_AD3_DRAW_INDEX_REG(x) ((x & 0xFFFF) << 16) 260 #define S_AD4_XYZ_DIM_REG(x) ((x & 0xFFFF)) 261 #define PKT3_EVENT_WRITE_ZPASS 0xB1 /* GFX11+ & PFP version >= 1458 */ 262 #define EVENT_WRITE_ZPASS_PFP_VERSION 1458 263 /* Use these on GFX11 with a high PFP firmware version (only dGPUs should have that, not APUs) 264 * because they are the fastest SET packets there. 265 * SET_CONTEXT_REG_PAIRS_PACKED: 266 * SET_SH_REG_PAIRS_PACKED: 267 * SET_SH_REG_PAIRS_PACKED_N: 268 * Format: header, count, (offset0 | (offset1 << 16), value0, value1)^(count / 2) 269 * - "count" is the register count and must be aligned to 2. 270 * - Consecutive offsets must not be equal. 271 * - RESET_FILTER_CAM must be set to 1. 272 * - If the register count is odd, write the first register again at the end to make it even. 273 * - The SH_*_PACKED* variants require register shadowing to be enabled. 274 * - The *_N variant is identical to the non-N variant, but the maximum allowed "count" is 14 275 * and it's faster. 276 * 277 * Use these on GFX12 because they are the fastest SET packets there. The PACKED variants don't 278 * exist on GFX12. 279 * SET_CONTEXT_REG_PAIRS: 280 * SET_SH_REG_PAIRS: 281 * SET_UCONFIG_REG_PAIRS: 282 * Format: header, (offset, value)^n. 283 * - Consecutive offsets must not be equal. 284 * - RESET_FILTER_CAM must be set to 1. 285 */ 286 #define PKT3_SET_CONTEXT_REG_PAIRS 0xB8 /* GFX11+; only use on GFX12, not GFX11 */ 287 #define PKT3_SET_CONTEXT_REG_PAIRS_PACKED 0xB9 /* GFX11 dGPUs only */ 288 #define PKT3_SET_SH_REG_PAIRS 0xBA /* GFX11+; only use on GFX12, not GFX11 */ 289 #define PKT3_SET_SH_REG_PAIRS_PACKED 0xBB /* GFX11 dGPUs only */ 290 #define PKT3_SET_SH_REG_PAIRS_PACKED_N 0xBD /* GFX11 dGPUs only */ 291 #define PKT3_SET_UCONFIG_REG_PAIRS 0xBE /* GFX12+ */ 292 293 #define PKT_TYPE_S(x) (((unsigned)(x)&0x3) << 30) 294 #define PKT_TYPE_G(x) (((x) >> 30) & 0x3) 295 #define PKT_TYPE_C 0x3FFFFFFF 296 #define PKT_COUNT_S(x) (((unsigned)(x)&0x3FFF) << 16) 297 #define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) 298 #define PKT_COUNT_C 0xC000FFFF 299 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x)&0xFF) << 8) 300 #define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) 301 #define PKT3_IT_OPCODE_C 0xFFFF00FF 302 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 303 #define PKT3_SHADER_TYPE_S(x) (((unsigned)(x) & 0x1) << 1) 304 #define PKT3_SHADER_TYPE_G(x) (((x) >> 1) & 0x1) 305 #define PKT3_RESET_FILTER_CAM_S(x) (((unsigned)(x) & 0x1) << 2) 306 #define PKT3_RESET_FILTER_CAM_G(x) (((unsigned)(x) >> 2) & 0x1) 307 #define PKT3(op, count, predicate) \ 308 (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 309 310 #define PKT2_NOP_PAD PKT_TYPE_S(2) 311 #define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */ 312 313 /* SI async DMA packets */ 314 #define SI_DMA_PACKET(cmd, sub_cmd, n) \ 315 ((((unsigned)(cmd)&0xF) << 28) | (((unsigned)(sub_cmd)&0xFF) << 20) | \ 316 (((unsigned)(n)&0xFFFFF) << 0)) 317 /* SI async DMA Packet types */ 318 #define SI_DMA_PACKET_WRITE 0x2 319 #define SI_DMA_PACKET_COPY 0x3 320 #define SI_DMA_COPY_MAX_BYTE_ALIGNED_SIZE 0xfffe0 321 /* The documentation says 0xffff8 is the maximum size in dwords, which is 322 * 0x3fffe0 in bytes. */ 323 #define SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE 0x3fffe0 324 #define SI_DMA_COPY_DWORD_ALIGNED 0x00 325 #define SI_DMA_COPY_BYTE_ALIGNED 0x40 326 #define SI_DMA_COPY_TILED 0x8 327 #define SI_DMA_PACKET_INDIRECT_BUFFER 0x4 328 #define SI_DMA_PACKET_SEMAPHORE 0x5 329 #define SI_DMA_PACKET_FENCE 0x6 330 #define SI_DMA_PACKET_TRAP 0x7 331 #define SI_DMA_PACKET_SRBM_WRITE 0x9 332 #define SI_DMA_PACKET_CONSTANT_FILL 0xd 333 #define SI_DMA_PACKET_NOP 0xf 334 335 /* CIK async DMA packets */ 336 #define SDMA_PACKET(op, sub_op, n) \ 337 ((((unsigned)(n)&0xFFFF) << 16) | (((unsigned)(sub_op)&0xFF) << 8) | \ 338 (((unsigned)(op)&0xFF) << 0)) 339 /* CIK async DMA packet types */ 340 #define SDMA_OPCODE_NOP 0x0 341 #define SDMA_OPCODE_COPY 0x1 342 #define SDMA_COPY_SUB_OPCODE_LINEAR 0x0 343 #define SDMA_COPY_SUB_OPCODE_TILED 0x1 344 #define SDMA_COPY_SUB_OPCODE_SOA 0x3 345 #define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 0x4 346 #define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 0x5 347 #define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 0x6 348 #define SDMA_OPCODE_WRITE 0x2 349 #define SDMA_WRITE_SUB_OPCODE_LINEAR 0x0 350 #define SDMA_WRITE_SUB_OPCODE_TILED 0x1 351 #define SDMA_OPCODE_INDIRECT_BUFFER 0x4 352 #define SDMA_OPCODE_FENCE 0x5 353 #define SDMA_FENCE_MTYPE_UC 0x3 354 #define SDMA_OPCODE_TRAP 0x6 355 #define SDMA_OPCODE_SEMAPHORE 0x7 356 #define SDMA_OPCODE_POLL_REGMEM 0x8 357 #define SDMA_POLL_MEM (1 << 31) 358 #define SDMA_POLL_INTERVAL_160_CLK 0xa 359 #define SDMA_POLL_RETRY_INDEFINITELY 0xfff 360 #define SDMA_OPCODE_CONSTANT_FILL 0xb 361 #define SDMA_OPCODE_TIMESTAMP 0xd 362 #define SDMA_TS_SUB_OPCODE_SET_LOCAL_TIMESTAMP 0x0 363 #define SDMA_TS_SUB_OPCODE_GET_LOCAL_TIMESTAMP 0x1 364 #define SDMA_TS_SUB_OPCODE_GET_GLOBAL_TIMESTAMP 0x2 365 #define SDMA_OPCODE_SRBM_WRITE 0xe 366 367 /* There is apparently an undocumented HW limitation that 368 * prevents the HW from copying the last 255 bytes of (1 << 22) - 1 369 */ 370 #define SDMA_V2_0_COPY_MAX_BYTES 0x3fff00 /* almost 4 MB*/ 371 #define SDMA_V5_2_COPY_MAX_BYTES 0x3fffff00 /* almost 1 GB */ 372 373 #define SDMA_NOP_PAD SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) /* header-only version */ 374 375 enum amd_cmp_class_flags 376 { 377 S_NAN = 1 << 0, // Signaling NaN 378 Q_NAN = 1 << 1, // Quiet NaN 379 N_INFINITY = 1 << 2, // Negative infinity 380 N_NORMAL = 1 << 3, // Negative normal 381 N_SUBNORMAL = 1 << 4, // Negative subnormal 382 N_ZERO = 1 << 5, // Negative zero 383 P_ZERO = 1 << 6, // Positive zero 384 P_SUBNORMAL = 1 << 7, // Positive subnormal 385 P_NORMAL = 1 << 8, // Positive normal 386 P_INFINITY = 1 << 9 // Positive infinity 387 }; 388 389 #endif /* _SID_H */ 390