1 /* 2 * Copyright 2015,2016 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AMDKERNELCODET_H 8 #define AMDKERNELCODET_H 9 10 //---------------------------------------------------------------------------// 11 // AMD Kernel Code, and its dependencies // 12 //---------------------------------------------------------------------------// 13 14 // Sets val bits for specified mask in specified dst packed instance. 15 #define AMD_HSA_BITS_SET(dst, mask, val) \ 16 dst &= (~(1 << mask##_SHIFT) & ~mask); \ 17 dst |= (((val) << mask##_SHIFT) & mask) 18 19 // Gets bits for specified mask from specified src packed instance. 20 #define AMD_HSA_BITS_GET(src, mask) ((src & mask) >> mask##_SHIFT) 21 22 /* Every amd_*_code_t has the following properties, which are composed of 23 * a number of bit fields. Every bit field has a mask (AMD_CODE_PROPERTY_*), 24 * bit width (AMD_CODE_PROPERTY_*_WIDTH, and bit shift amount 25 * (AMD_CODE_PROPERTY_*_SHIFT) for convenient access. Unused bits must be 0. 26 * 27 * (Note that bit fields cannot be used as their layout is 28 * implementation defined in the C standard and so cannot be used to 29 * specify an ABI) 30 */ 31 enum amd_code_property_mask_t 32 { 33 34 /* Enable the setup of the SGPR user data registers 35 * (AMD_CODE_PROPERTY_ENABLE_SGPR_*), see documentation of amd_kernel_code_t 36 * for initial register state. 37 * 38 * The total number of SGPRuser data registers requested must not 39 * exceed 16. Any requests beyond 16 will be ignored. 40 * 41 * Used to set COMPUTE_PGM_RSRC2.USER_SGPR (set to total count of 42 * SGPR user data registers enabled up to 16). 43 */ 44 45 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT = 0, 46 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH = 1, 47 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER = 48 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) 49 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT, 50 51 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT = 1, 52 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH = 1, 53 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR = 54 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) 55 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT, 56 57 AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT = 2, 58 AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH = 1, 59 AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = 60 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - 1) 61 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT, 62 63 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT = 3, 64 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH = 1, 65 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR = 66 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) 67 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT, 68 69 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT = 4, 70 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_WIDTH = 1, 71 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID = 72 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_WIDTH) - 1) 73 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT, 74 75 AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT = 5, 76 AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH = 1, 77 AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT = 78 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH) - 1) 79 << AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT, 80 81 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT = 6, 82 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH = 1, 83 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE = 84 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH) - 1) 85 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT, 86 87 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT = 7, 88 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH = 1, 89 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X = 90 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH) - 1) 91 << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT, 92 93 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT = 8, 94 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH = 1, 95 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y = 96 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH) - 1) 97 << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT, 98 99 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT = 9, 100 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH = 1, 101 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z = 102 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH) - 1) 103 << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT, 104 105 AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT = 10, 106 AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_WIDTH = 1, 107 AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 = 108 ((1 << AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_WIDTH) - 1) 109 << AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT, 110 111 AMD_CODE_PROPERTY_RESERVED1_SHIFT = 11, 112 AMD_CODE_PROPERTY_RESERVED1_WIDTH = 5, 113 AMD_CODE_PROPERTY_RESERVED1 = ((1 << AMD_CODE_PROPERTY_RESERVED1_WIDTH) - 1) 114 << AMD_CODE_PROPERTY_RESERVED1_SHIFT, 115 116 /* Control wave ID base counter for GDS ordered-append. Used to set 117 * COMPUTE_DISPATCH_INITIATOR.ORDERED_APPEND_ENBL. (Not sure if 118 * ORDERED_APPEND_MODE also needs to be settable) 119 */ 120 AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS_SHIFT = 16, 121 AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS_WIDTH = 1, 122 AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS = 123 ((1 << AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS_WIDTH) - 1) 124 << AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS_SHIFT, 125 126 /* The interleave (swizzle) element size in bytes required by the 127 * code for private memory. This must be 2, 4, 8 or 16. This value 128 * is provided to the finalizer when it is invoked and is recorded 129 * here. The hardware will interleave the memory requests of each 130 * lane of a wavefront by this element size to ensure each 131 * work-item gets a distinct memory memory location. Therefore, the 132 * finalizer ensures that all load and store operations done to 133 * private memory do not exceed this size. For example, if the 134 * element size is 4 (32-bits or dword) and a 64-bit value must be 135 * loaded, the finalizer will generate two 32-bit loads. This 136 * ensures that the interleaving will get the work-item 137 * specific dword for both halves of the 64-bit value. If it just 138 * did a 64-bit load then it would get one dword which belonged to 139 * its own work-item, but the second dword would belong to the 140 * adjacent lane work-item since the interleaving is in dwords. 141 * 142 * The value used must match the value that the runtime configures 143 * the GPU flat scratch (SH_STATIC_MEM_CONFIG.ELEMENT_SIZE). This 144 * is generally DWORD. 145 * 146 * USE VALUES FROM THE AMD_ELEMENT_BYTE_SIZE_T ENUM. 147 */ 148 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE_SHIFT = 17, 149 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE_WIDTH = 2, 150 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE = 151 ((1 << AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE_WIDTH) - 1) 152 << AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE_SHIFT, 153 154 /* Are global memory addresses 64 bits. Must match 155 * amd_kernel_code_t.hsail_machine_model == 156 * HSA_MACHINE_LARGE. Must also match 157 * SH_MEM_CONFIG.PTR32 (GFX6 (SI)/GFX7 (CI)), 158 * SH_MEM_CONFIG.ADDRESS_MODE (GFX8 (VI)+). 159 */ 160 AMD_CODE_PROPERTY_IS_PTR64_SHIFT = 19, 161 AMD_CODE_PROPERTY_IS_PTR64_WIDTH = 1, 162 AMD_CODE_PROPERTY_IS_PTR64 = ((1 << AMD_CODE_PROPERTY_IS_PTR64_WIDTH) - 1) 163 << AMD_CODE_PROPERTY_IS_PTR64_SHIFT, 164 165 /* Indicate if the generated ISA is using a dynamically sized call 166 * stack. This can happen if calls are implemented using a call 167 * stack and recursion, alloca or calls to indirect functions are 168 * present. In these cases the Finalizer cannot compute the total 169 * private segment size at compile time. In this case the 170 * workitem_private_segment_byte_size only specifies the statically 171 * know private segment size, and additional space must be added 172 * for the call stack. 173 */ 174 AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_SHIFT = 20, 175 AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_WIDTH = 1, 176 AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK = 177 ((1 << AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_WIDTH) - 1) 178 << AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_SHIFT, 179 180 /* Indicate if code generated has support for debugging. */ 181 AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED_SHIFT = 21, 182 AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED_WIDTH = 1, 183 AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED = ((1 << AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED_WIDTH) - 1) 184 << AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED_SHIFT, 185 186 AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED_SHIFT = 22, 187 AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED_WIDTH = 1, 188 AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED = ((1 << AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED_WIDTH) - 1) 189 << AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED_SHIFT, 190 191 AMD_CODE_PROPERTY_RESERVED2_SHIFT = 23, 192 AMD_CODE_PROPERTY_RESERVED2_WIDTH = 9, 193 AMD_CODE_PROPERTY_RESERVED2 = ((1 << AMD_CODE_PROPERTY_RESERVED2_WIDTH) - 1) 194 << AMD_CODE_PROPERTY_RESERVED2_SHIFT 195 }; 196 197 /* AMD Kernel Code Object (amd_kernel_code_t). GPU CP uses the AMD Kernel 198 * Code Object to set up the hardware to execute the kernel dispatch. 199 * 200 * Initial Kernel Register State. 201 * 202 * Initial kernel register state will be set up by CP/SPI prior to the start 203 * of execution of every wavefront. This is limited by the constraints of the 204 * current hardware. 205 * 206 * The order of the SGPR registers is defined, but the Finalizer can specify 207 * which ones are actually setup in the amd_kernel_code_t object using the 208 * enable_sgpr_* bit fields. The register numbers used for enabled registers 209 * are dense starting at SGPR0: the first enabled register is SGPR0, the next 210 * enabled register is SGPR1 etc.; disabled registers do not have an SGPR 211 * number. 212 * 213 * The initial SGPRs comprise up to 16 User SRGPs that are set up by CP and 214 * apply to all waves of the grid. It is possible to specify more than 16 User 215 * SGPRs using the enable_sgpr_* bit fields, in which case only the first 16 216 * are actually initialized. These are then immediately followed by the System 217 * SGPRs that are set up by ADC/SPI and can have different values for each wave 218 * of the grid dispatch. 219 * 220 * SGPR register initial state is defined as follows: 221 * 222 * Private Segment Buffer (enable_sgpr_private_segment_buffer): 223 * Number of User SGPR registers: 4. V# that can be used, together with 224 * Scratch Wave Offset as an offset, to access the Private/Spill/Arg 225 * segments using a segment address. It must be set as follows: 226 * - Base address: of the scratch memory area used by the dispatch. It 227 * does not include the scratch wave offset. It will be the per process 228 * SH_HIDDEN_PRIVATE_BASE_VMID plus any offset from this dispatch (for 229 * example there may be a per pipe offset, or per AQL Queue offset). 230 * - Stride + data_format: Element Size * Index Stride (???) 231 * - Cache swizzle: ??? 232 * - Swizzle enable: SH_STATIC_MEM_CONFIG.SWIZZLE_ENABLE (must be 1 for 233 * scratch) 234 * - Num records: Flat Scratch Work Item Size / Element Size (???) 235 * - Dst_sel_*: ??? 236 * - Num_format: ??? 237 * - Element_size: SH_STATIC_MEM_CONFIG.ELEMENT_SIZE (will be DWORD, must 238 * agree with amd_kernel_code_t.privateElementSize) 239 * - Index_stride: SH_STATIC_MEM_CONFIG.INDEX_STRIDE (will be 64 as must 240 * be number of wavefront lanes for scratch, must agree with 241 * amd_kernel_code_t.wavefrontSize) 242 * - Add tid enable: 1 243 * - ATC: from SH_MEM_CONFIG.PRIVATE_ATC, 244 * - Hash_enable: ??? 245 * - Heap: ??? 246 * - Mtype: from SH_STATIC_MEM_CONFIG.PRIVATE_MTYPE 247 * - Type: 0 (a buffer) (???) 248 * 249 * Dispatch Ptr (enable_sgpr_dispatch_ptr): 250 * Number of User SGPR registers: 2. 64 bit address of AQL dispatch packet 251 * for kernel actually executing. 252 * 253 * Queue Ptr (enable_sgpr_queue_ptr): 254 * Number of User SGPR registers: 2. 64 bit address of AmdQueue object for 255 * AQL queue on which the dispatch packet was queued. 256 * 257 * Kernarg Segment Ptr (enable_sgpr_kernarg_segment_ptr): 258 * Number of User SGPR registers: 2. 64 bit address of Kernarg segment. This 259 * is directly copied from the kernargPtr in the dispatch packet. Having CP 260 * load it once avoids loading it at the beginning of every wavefront. 261 * 262 * Dispatch Id (enable_sgpr_dispatch_id): 263 * Number of User SGPR registers: 2. 64 bit Dispatch ID of the dispatch 264 * packet being executed. 265 * 266 * Flat Scratch Init (enable_sgpr_flat_scratch_init): 267 * Number of User SGPR registers: 2. This is 2 SGPRs. 268 * 269 * For CI/VI: 270 * The first SGPR is a 32 bit byte offset from SH_MEM_HIDDEN_PRIVATE_BASE 271 * to base of memory for scratch for this dispatch. This is the same offset 272 * used in computing the Scratch Segment Buffer base address. The value of 273 * Scratch Wave Offset must be added by the kernel code and moved to 274 * SGPRn-4 for use as the FLAT SCRATCH BASE in flat memory instructions. 275 * 276 * The second SGPR is 32 bit byte size of a single work-item's scratch 277 * memory usage. This is directly loaded from the dispatch packet Private 278 * Segment Byte Size and rounded up to a multiple of DWORD. 279 * 280 * \todo [Does CP need to round this to >4 byte alignment?] 281 * 282 * The kernel code must move to SGPRn-3 for use as the FLAT SCRATCH SIZE in 283 * flat memory instructions. Having CP load it once avoids loading it at 284 * the beginning of every wavefront. 285 * 286 * Private Segment Size (enable_sgpr_private_segment_size): 287 * Number of User SGPR registers: 1. The 32 bit byte size of a single 288 * work-item's scratch memory allocation. This is the value from the dispatch 289 * packet. Private Segment Byte Size rounded up by CP to a multiple of DWORD. 290 * 291 * \todo [Does CP need to round this to >4 byte alignment?] 292 * 293 * Having CP load it once avoids loading it at the beginning of every 294 * wavefront. 295 * 296 * \todo [This will not be used for CI/VI since it is the same value as 297 * the second SGPR of Flat Scratch Init. 298 * 299 * Grid Work-Group Count X (enable_sgpr_grid_workgroup_count_x): 300 * Number of User SGPR registers: 1. 32 bit count of the number of 301 * work-groups in the X dimension for the grid being executed. Computed from 302 * the fields in the HsaDispatchPacket as 303 * ((gridSize.x+workgroupSize.x-1)/workgroupSize.x). 304 * 305 * Grid Work-Group Count Y (enable_sgpr_grid_workgroup_count_y): 306 * Number of User SGPR registers: 1. 32 bit count of the number of 307 * work-groups in the Y dimension for the grid being executed. Computed from 308 * the fields in the HsaDispatchPacket as 309 * ((gridSize.y+workgroupSize.y-1)/workgroupSize.y). 310 * 311 * Only initialized if <16 previous SGPRs initialized. 312 * 313 * Grid Work-Group Count Z (enable_sgpr_grid_workgroup_count_z): 314 * Number of User SGPR registers: 1. 32 bit count of the number of 315 * work-groups in the Z dimension for the grid being executed. Computed 316 * from the fields in the HsaDispatchPacket as 317 * ((gridSize.z+workgroupSize.z-1)/workgroupSize.z). 318 * 319 * Only initialized if <16 previous SGPRs initialized. 320 * 321 * Work-Group Id X (enable_sgpr_workgroup_id_x): 322 * Number of System SGPR registers: 1. 32 bit work group id in X dimension 323 * of grid for wavefront. Always present. 324 * 325 * Work-Group Id Y (enable_sgpr_workgroup_id_y): 326 * Number of System SGPR registers: 1. 32 bit work group id in Y dimension 327 * of grid for wavefront. 328 * 329 * Work-Group Id Z (enable_sgpr_workgroup_id_z): 330 * Number of System SGPR registers: 1. 32 bit work group id in Z dimension 331 * of grid for wavefront. If present then Work-group Id Y will also be 332 * present 333 * 334 * Work-Group Info (enable_sgpr_workgroup_info): 335 * Number of System SGPR registers: 1. {first_wave, 14'b0000, 336 * ordered_append_term[10:0], threadgroup_size_in_waves[5:0]} 337 * 338 * Private Segment Wave Byte Offset 339 * (enable_sgpr_private_segment_wave_byte_offset): 340 * Number of System SGPR registers: 1. 32 bit byte offset from base of 341 * dispatch scratch base. Must be used as an offset with Private/Spill/Arg 342 * segment address when using Scratch Segment Buffer. It must be added to 343 * Flat Scratch Offset if setting up FLAT SCRATCH for flat addressing. 344 * 345 * 346 * The order of the VGPR registers is defined, but the Finalizer can specify 347 * which ones are actually setup in the amd_kernel_code_t object using the 348 * enableVgpr* bit fields. The register numbers used for enabled registers 349 * are dense starting at VGPR0: the first enabled register is VGPR0, the next 350 * enabled register is VGPR1 etc.; disabled registers do not have an VGPR 351 * number. 352 * 353 * VGPR register initial state is defined as follows: 354 * 355 * Work-Item Id X (always initialized): 356 * Number of registers: 1. 32 bit work item id in X dimension of work-group 357 * for wavefront lane. 358 * 359 * Work-Item Id X (enable_vgpr_workitem_id > 0): 360 * Number of registers: 1. 32 bit work item id in Y dimension of work-group 361 * for wavefront lane. 362 * 363 * Work-Item Id X (enable_vgpr_workitem_id > 0): 364 * Number of registers: 1. 32 bit work item id in Z dimension of work-group 365 * for wavefront lane. 366 * 367 * 368 * The setting of registers is being done by existing GPU hardware as follows: 369 * 1) SGPRs before the Work-Group Ids are set by CP using the 16 User Data 370 * registers. 371 * 2) Work-group Id registers X, Y, Z are set by SPI which supports any 372 * combination including none. 373 * 3) Scratch Wave Offset is also set by SPI which is why its value cannot 374 * be added into the value Flat Scratch Offset which would avoid the 375 * Finalizer generated prolog having to do the add. 376 * 4) The VGPRs are set by SPI which only supports specifying either (X), 377 * (X, Y) or (X, Y, Z). 378 * 379 * Flat Scratch Dispatch Offset and Flat Scratch Size are adjacent SGRRs so 380 * they can be moved as a 64 bit value to the hardware required SGPRn-3 and 381 * SGPRn-4 respectively using the Finalizer ?FLAT_SCRATCH? Register. 382 * 383 * The global segment can be accessed either using flat operations or buffer 384 * operations. If buffer operations are used then the Global Buffer used to 385 * access HSAIL Global/Readonly/Kernarg (which are combine) segments using a 386 * segment address is not passed into the kernel code by CP since its base 387 * address is always 0. Instead the Finalizer generates prolog code to 388 * initialize 4 SGPRs with a V# that has the following properties, and then 389 * uses that in the buffer instructions: 390 * - base address of 0 391 * - no swizzle 392 * - ATC=1 393 * - MTYPE set to support memory coherence specified in 394 * amd_kernel_code_t.globalMemoryCoherence 395 * 396 * When the Global Buffer is used to access the Kernarg segment, must add the 397 * dispatch packet kernArgPtr to a kernarg segment address before using this V#. 398 * Alternatively scalar loads can be used if the kernarg offset is uniform, as 399 * the kernarg segment is constant for the duration of the kernel execution. 400 */ 401 402 typedef struct amd_kernel_code_s { 403 uint32_t amd_kernel_code_version_major; 404 uint32_t amd_kernel_code_version_minor; 405 uint16_t amd_machine_kind; 406 uint16_t amd_machine_version_major; 407 uint16_t amd_machine_version_minor; 408 uint16_t amd_machine_version_stepping; 409 410 /* Byte offset (possibly negative) from start of amd_kernel_code_t 411 * object to kernel's entry point instruction. The actual code for 412 * the kernel is required to be 256 byte aligned to match hardware 413 * requirements (SQ cache line is 16). The code must be position 414 * independent code (PIC) for AMD devices to give runtime the 415 * option of copying code to discrete GPU memory or APU L2 416 * cache. The Finalizer should endeavour to allocate all kernel 417 * machine code in contiguous memory pages so that a device 418 * pre-fetcher will tend to only pre-fetch Kernel Code objects, 419 * improving cache performance. 420 */ 421 int64_t kernel_code_entry_byte_offset; 422 423 /* Range of bytes to consider prefetching expressed as an offset 424 * and size. The offset is from the start (possibly negative) of 425 * amd_kernel_code_t object. Set both to 0 if no prefetch 426 * information is available. 427 */ 428 int64_t kernel_code_prefetch_byte_offset; 429 uint64_t kernel_code_prefetch_byte_size; 430 431 /* Number of bytes of scratch backing memory required for full 432 * occupancy of target chip. This takes into account the number of 433 * bytes of scratch per work-item, the wavefront size, the maximum 434 * number of wavefronts per CU, and the number of CUs. This is an 435 * upper limit on scratch. If the grid being dispatched is small it 436 * may only need less than this. If the kernel uses no scratch, or 437 * the Finalizer has not computed this value, it must be 0. 438 */ 439 uint64_t max_scratch_backing_memory_byte_size; 440 441 /* Shader program settings for CS. Contains COMPUTE_PGM_RSRC1 and 442 * COMPUTE_PGM_RSRC2 registers. 443 */ 444 uint64_t compute_pgm_resource_registers; 445 446 /* Code properties. See amd_code_property_mask_t for a full list of 447 * properties. 448 */ 449 uint32_t code_properties; 450 451 /* The amount of memory required for the combined private, spill 452 * and arg segments for a work-item in bytes. If 453 * is_dynamic_callstack is 1 then additional space must be added to 454 * this value for the call stack. 455 */ 456 uint32_t workitem_private_segment_byte_size; 457 458 /* The amount of group segment memory required by a work-group in 459 * bytes. This does not include any dynamically allocated group 460 * segment memory that may be added when the kernel is 461 * dispatched. 462 */ 463 uint32_t workgroup_group_segment_byte_size; 464 465 /* Number of byte of GDS required by kernel dispatch. Must be 0 if 466 * not using GDS. 467 */ 468 uint32_t gds_segment_byte_size; 469 470 /* The size in bytes of the kernarg segment that holds the values 471 * of the arguments to the kernel. This could be used by CP to 472 * prefetch the kernarg segment pointed to by the dispatch packet. 473 */ 474 uint64_t kernarg_segment_byte_size; 475 476 /* Number of fbarrier's used in the kernel and all functions it 477 * calls. If the implementation uses group memory to allocate the 478 * fbarriers then that amount must already be included in the 479 * workgroup_group_segment_byte_size total. 480 */ 481 uint32_t workgroup_fbarrier_count; 482 483 /* Number of scalar registers used by a wavefront. This includes 484 * the special SGPRs for VCC, Flat Scratch Base, Flat Scratch Size 485 * and XNACK (for GFX8 (VI)). It does not include the 16 SGPR added if a 486 * trap handler is enabled. Used to set COMPUTE_PGM_RSRC1.SGPRS. 487 */ 488 uint16_t wavefront_sgpr_count; 489 490 /* Number of vector registers used by each work-item. Used to set 491 * COMPUTE_PGM_RSRC1.VGPRS. 492 */ 493 uint16_t workitem_vgpr_count; 494 495 /* If reserved_vgpr_count is 0 then must be 0. Otherwise, this is the 496 * first fixed VGPR number reserved. 497 */ 498 uint16_t reserved_vgpr_first; 499 500 /* The number of consecutive VGPRs reserved by the client. If 501 * is_debug_supported then this count includes VGPRs reserved 502 * for debugger use. 503 */ 504 uint16_t reserved_vgpr_count; 505 506 /* If reserved_sgpr_count is 0 then must be 0. Otherwise, this is the 507 * first fixed SGPR number reserved. 508 */ 509 uint16_t reserved_sgpr_first; 510 511 /* The number of consecutive SGPRs reserved by the client. If 512 * is_debug_supported then this count includes SGPRs reserved 513 * for debugger use. 514 */ 515 uint16_t reserved_sgpr_count; 516 517 /* If is_debug_supported is 0 then must be 0. Otherwise, this is the 518 * fixed SGPR number used to hold the wave scratch offset for the 519 * entire kernel execution, or uint16_t(-1) if the register is not 520 * used or not known. 521 */ 522 uint16_t debug_wavefront_private_segment_offset_sgpr; 523 524 /* If is_debug_supported is 0 then must be 0. Otherwise, this is the 525 * fixed SGPR number of the first of 4 SGPRs used to hold the 526 * scratch V# used for the entire kernel execution, or uint16_t(-1) 527 * if the registers are not used or not known. 528 */ 529 uint16_t debug_private_segment_buffer_sgpr; 530 531 /* The maximum byte alignment of variables used by the kernel in 532 * the specified memory segment. Expressed as a power of two. Must 533 * be at least HSA_POWERTWO_16. 534 */ 535 uint8_t kernarg_segment_alignment; 536 uint8_t group_segment_alignment; 537 uint8_t private_segment_alignment; 538 539 /* Wavefront size expressed as a power of two. Must be a power of 2 540 * in range 1..64 inclusive. Used to support runtime query that 541 * obtains wavefront size, which may be used by application to 542 * allocated dynamic group memory and set the dispatch work-group 543 * size. 544 */ 545 uint8_t wavefront_size; 546 547 int32_t call_convention; 548 uint8_t reserved3[12]; 549 uint64_t runtime_loader_kernel_symbol; 550 uint64_t control_directives[16]; 551 } amd_kernel_code_t; 552 553 #endif // AMDKERNELCODET_H 554