1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #ifndef AMD_BLOCK_ACPIMMIO_H
4 #define AMD_BLOCK_ACPIMMIO_H
5
6 #include <device/mmio.h>
7 #include <types.h>
8
9 /*
10 * Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7. Valid for Mullins and
11 * newer SoCs, but not for the generations with separate FCH or Kabini.
12 */
13 #define PM_DECODE_EN 0x00
14 #define HPET_MSI_EN (1 << 29)
15 #define HPET_WIDTH_SEL (1 << 28) /* 0=32bit, 1=64bit */
16 #define SMBUS_ASF_IO_BASE_SHIFT 8
17 #define SMBUS_ASF_IO_BASE_MASK (0xff << SMBUS_ASF_IO_BASE_SHIFT)
18 #define HPET_EN (1 << 6) /* decode HPET MMIO at 0xfed00000 */
19 #define FCH_IOAPIC_EN (1 << 5)
20 #define SMBUS_ASF_IO_EN (1 << 4)
21 #define LEGACY_DMA_IO_80_EN (1 << 3) /* pass 0x80-0x83 to legacy DMA IO range */
22 #define LEGACY_DMA_IO_EN (1 << 2)
23 #define CF9_IO_EN (1 << 1)
24 #define LEGACY_IO_EN (1 << 0)
25 #define PM_ESPI_INTR_CTRL 0x40
26 #define PM_ESPI_DEV_INTR_MASK 0x00FFFFFF
27 #define PM_RST_CTRL1 0xbe
28 #define SLPTYPE_CONTROL_EN (1 << 5)
29 #define KBRSTEN (1 << 4)
30 #define PM_RST_STATUS 0xc0
31
32 /*
33 * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs
34 * and the Kabini SoC fall into this category. Kabini's successor, Mullins, uses
35 * this newer method of enable in PMx04.
36 */
37
38 #define ACPIMMIO_DECODE_REGISTER_24 0x24
39 #define PM_24_ACPIMMIO_DECODE_EN BIT(0)
40
41 #define ACPIMMIO_DECODE_REGISTER_04 0x04
42 #define PM_04_BIOSRAM_DECODE_EN BIT(0)
43 #define PM_04_ACPIMMIO_DECODE_EN BIT(1)
44
45 /* For x86 base is constant, while PSP does mapping runtime. */
46 #define CONSTANT_ACPIMMIO_BASE_ADDRESS ENV_X86
47
48 #if CONSTANT_ACPIMMIO_BASE_ADDRESS
49 #define MAYBE_CONST const
50 #else
51 #define MAYBE_CONST
52 #endif
53
54 extern uint8_t *MAYBE_CONST acpimmio_gpio_100;
55 extern uint8_t *MAYBE_CONST acpimmio_smi;
56 extern uint8_t *MAYBE_CONST acpimmio_pmio;
57 extern uint8_t *MAYBE_CONST acpimmio_pmio2;
58 extern uint8_t *MAYBE_CONST acpimmio_biosram;
59 extern uint8_t *MAYBE_CONST acpimmio_cmosram;
60 extern uint8_t *MAYBE_CONST acpimmio_cmos;
61 extern uint8_t *MAYBE_CONST acpimmio_acpi;
62 extern uint8_t *MAYBE_CONST acpimmio_asf;
63 extern uint8_t *MAYBE_CONST acpimmio_smbus;
64 extern uint8_t *MAYBE_CONST acpimmio_wdt;
65 extern uint8_t *MAYBE_CONST acpimmio_hpet;
66 extern uint8_t *MAYBE_CONST acpimmio_iomux;
67 extern uint8_t *MAYBE_CONST acpimmio_misc;
68 extern uint8_t *MAYBE_CONST acpimmio_remote_gpio;
69 extern uint8_t *MAYBE_CONST acpimmio_dpvga;
70 extern uint8_t *MAYBE_CONST acpimmio_gpio0;
71 extern uint8_t *MAYBE_CONST acpimmio_xhci_pm;
72 extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr;
73 extern uint8_t *MAYBE_CONST acpimmio_aoac;
74
75 #undef MAYBE_CONST
76
77 /* For newer integrated FCHs */
78 void enable_acpimmio_decode_pm04(void);
79 void fch_enable_cf9_io(void);
80 void fch_enable_legacy_io(void);
81 void fch_disable_legacy_dma_io(void);
82 void fch_io_enable_legacy_io(void);
83 void fch_enable_ioapic_decode(void);
84 void fch_configure_hpet(void);
85 void fch_disable_kb_rst(void);
86
87 /* Access PM registers using IO cycles */
88 uint8_t pm_io_read8(uint8_t reg);
89 uint16_t pm_io_read16(uint8_t reg);
90 uint32_t pm_io_read32(uint8_t reg);
91 void pm_io_write8(uint8_t reg, uint8_t value);
92 void pm_io_write16(uint8_t reg, uint16_t value);
93 void pm_io_write32(uint8_t reg, uint32_t value);
94
95 /* Print source of last reset */
96 void fch_print_pmxc0_status(void);
97
smi_read8(uint8_t reg)98 static inline uint8_t smi_read8(uint8_t reg)
99 {
100 return read8(acpimmio_smi + reg);
101 }
102
smi_read16(uint8_t reg)103 static inline uint16_t smi_read16(uint8_t reg)
104 {
105 return read16(acpimmio_smi + reg);
106 }
107
smi_read32(uint8_t reg)108 static inline uint32_t smi_read32(uint8_t reg)
109 {
110 return read32(acpimmio_smi + reg);
111 }
112
smi_write8(uint8_t reg,uint8_t value)113 static inline void smi_write8(uint8_t reg, uint8_t value)
114 {
115 write8(acpimmio_smi + reg, value);
116 }
117
smi_write16(uint8_t reg,uint16_t value)118 static inline void smi_write16(uint8_t reg, uint16_t value)
119 {
120 write16(acpimmio_smi + reg, value);
121 }
122
smi_write32(uint8_t reg,uint32_t value)123 static inline void smi_write32(uint8_t reg, uint32_t value)
124 {
125 write32(acpimmio_smi + reg, value);
126 }
127
pm_read8(uint8_t reg)128 static inline uint8_t pm_read8(uint8_t reg)
129 {
130 return read8(acpimmio_pmio + reg);
131 }
132
pm_read16(uint8_t reg)133 static inline uint16_t pm_read16(uint8_t reg)
134 {
135 return read16(acpimmio_pmio + reg);
136 }
137
pm_read32(uint8_t reg)138 static inline uint32_t pm_read32(uint8_t reg)
139 {
140 return read32(acpimmio_pmio + reg);
141 }
142
pm_write8(uint8_t reg,uint8_t value)143 static inline void pm_write8(uint8_t reg, uint8_t value)
144 {
145 write8(acpimmio_pmio + reg, value);
146 }
147
pm_write16(uint8_t reg,uint16_t value)148 static inline void pm_write16(uint8_t reg, uint16_t value)
149 {
150 write16(acpimmio_pmio + reg, value);
151 }
152
pm_write32(uint8_t reg,uint32_t value)153 static inline void pm_write32(uint8_t reg, uint32_t value)
154 {
155 write32(acpimmio_pmio + reg, value);
156 }
157
pm2_read8(uint8_t reg)158 static inline uint8_t pm2_read8(uint8_t reg)
159 {
160 return read8(acpimmio_pmio2 + reg);
161 }
162
pm2_write8(uint8_t reg,uint8_t value)163 static inline void pm2_write8(uint8_t reg, uint8_t value)
164 {
165 write8(acpimmio_pmio2 + reg, value);
166 }
167
acpi_read8(uint8_t reg)168 static inline uint8_t acpi_read8(uint8_t reg)
169 {
170 return read8(acpimmio_acpi + reg);
171 }
172
acpi_read16(uint8_t reg)173 static inline uint16_t acpi_read16(uint8_t reg)
174 {
175 return read16(acpimmio_acpi + reg);
176 }
177
acpi_read32(uint8_t reg)178 static inline uint32_t acpi_read32(uint8_t reg)
179 {
180 return read32(acpimmio_acpi + reg);
181 }
182
acpi_write8(uint8_t reg,uint8_t value)183 static inline void acpi_write8(uint8_t reg, uint8_t value)
184 {
185 write8(acpimmio_acpi + reg, value);
186 }
187
acpi_write16(uint8_t reg,uint16_t value)188 static inline void acpi_write16(uint8_t reg, uint16_t value)
189 {
190 write16(acpimmio_acpi + reg, value);
191 }
192
acpi_write32(uint8_t reg,uint32_t value)193 static inline void acpi_write32(uint8_t reg, uint32_t value)
194 {
195 write32(acpimmio_acpi + reg, value);
196 }
197
asf_read8(uint8_t reg)198 static inline uint8_t asf_read8(uint8_t reg)
199 {
200 return read8(acpimmio_asf + reg);
201 }
202
asf_write8(uint8_t reg,uint8_t value)203 static inline void asf_write8(uint8_t reg, uint8_t value)
204 {
205 write8(acpimmio_asf + reg, value);
206 }
207
smbus_read8(uint8_t reg)208 static inline uint8_t smbus_read8(uint8_t reg)
209 {
210 return read8(acpimmio_smbus + reg);
211 }
212
smbus_write8(uint8_t reg,uint8_t value)213 static inline void smbus_write8(uint8_t reg, uint8_t value)
214 {
215 write8(acpimmio_smbus + reg, value);
216 }
217
misc_read8(uint8_t reg)218 static inline uint8_t misc_read8(uint8_t reg)
219 {
220 return read8(acpimmio_misc + reg);
221 }
222
misc_read16(uint8_t reg)223 static inline uint16_t misc_read16(uint8_t reg)
224 {
225 return read16(acpimmio_misc + reg);
226 }
227
misc_read32(uint8_t reg)228 static inline uint32_t misc_read32(uint8_t reg)
229 {
230 return read32(acpimmio_misc + reg);
231 }
232
misc_write8(uint8_t reg,uint8_t value)233 static inline void misc_write8(uint8_t reg, uint8_t value)
234 {
235 write8(acpimmio_misc + reg, value);
236 }
237
misc_write16(uint8_t reg,uint16_t value)238 static inline void misc_write16(uint8_t reg, uint16_t value)
239 {
240 write16(acpimmio_misc + reg, value);
241 }
242
misc_write32(uint8_t reg,uint32_t value)243 static inline void misc_write32(uint8_t reg, uint32_t value)
244 {
245 write32(acpimmio_misc + reg, value);
246 }
247
xhci_pm_read8(uint8_t reg)248 static inline uint8_t xhci_pm_read8(uint8_t reg)
249 {
250 return read8(acpimmio_xhci_pm + reg);
251 }
252
xhci_pm_read16(uint8_t reg)253 static inline uint16_t xhci_pm_read16(uint8_t reg)
254 {
255 return read16(acpimmio_xhci_pm + reg);
256 }
257
xhci_pm_read32(uint8_t reg)258 static inline uint32_t xhci_pm_read32(uint8_t reg)
259 {
260 return read32(acpimmio_xhci_pm + reg);
261 }
262
xhci_pm_write8(uint8_t reg,uint8_t value)263 static inline void xhci_pm_write8(uint8_t reg, uint8_t value)
264 {
265 write8(acpimmio_xhci_pm + reg, value);
266 }
267
xhci_pm_write16(uint8_t reg,uint16_t value)268 static inline void xhci_pm_write16(uint8_t reg, uint16_t value)
269 {
270 write16(acpimmio_xhci_pm + reg, value);
271 }
272
xhci_pm_write32(uint8_t reg,uint32_t value)273 static inline void xhci_pm_write32(uint8_t reg, uint32_t value)
274 {
275 write32(acpimmio_xhci_pm + reg, value);
276 }
277
aoac_read8(uint8_t reg)278 static inline uint8_t aoac_read8(uint8_t reg)
279 {
280 return read8(acpimmio_aoac + reg);
281 }
282
aoac_write8(uint8_t reg,uint8_t value)283 static inline void aoac_write8(uint8_t reg, uint8_t value)
284 {
285 write8(acpimmio_aoac + reg, value);
286 }
287
288 #endif /* AMD_BLOCK_ACPIMMIO_H */
289