1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_AOAC_H 4 #define AMD_BLOCK_AOAC_H 5 6 #include <types.h> 7 8 /* FCH AOAC Registers 0xfed81e00 */ 9 #define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) 10 #define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) 11 12 /* Bit definitions for Device D3 Control AOACx0000[40...7E; even byte addresses] */ 13 #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) | BIT(1)) 14 #define FCH_AOAC_D0_UNINITIALIZED 0 15 #define FCH_AOAC_D0_INITIALIZED 1 16 #define FCH_AOAC_D1_2_3_WARM 2 17 #define FCH_AOAC_D3_COLD 3 18 #define FCH_AOAC_DEVICE_STATE BIT(2) 19 #define FCH_AOAC_PWR_ON_DEV BIT(3) 20 #define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) 21 #define FCH_AOAC_SW_REF_CLK_OK BIT(5) 22 #define FCH_AOAC_SW_RST_B BIT(6) 23 #define FCH_AOAC_IS_SW_CONTROL BIT(7) 24 25 /* Bit definitions for Device D3 State AOACx0000[41...7f; odd byte addresses] */ 26 #define FCH_AOAC_PWR_RST_STATE BIT(0) 27 #define FCH_AOAC_REF_CLK_OK_STATE BIT(1) 28 #define FCH_AOAC_RST_B_STATE BIT(2) 29 #define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) 30 #define FCH_AOAC_D3COLD BIT(4) 31 #define FCH_AOAC_CLK_OK_STATE BIT(5) 32 #define FCH_AOAC_STAT0 BIT(6) 33 #define FCH_AOAC_STAT1 BIT(7) 34 35 bool is_aoac_device_enabled(unsigned int dev); 36 void power_on_aoac_device(unsigned int dev); 37 void power_off_aoac_device(unsigned int dev); 38 /* the following 2 functions are implemented in the SoC code */ 39 void enable_aoac_devices(void); 40 void wait_for_aoac_enabled(unsigned int dev); 41 42 #endif /* AMD_BLOCK_AOAC_H */ 43