1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_COMMON_BLOCK_I2C_H 4 #define AMD_COMMON_BLOCK_I2C_H 5 6 #include <amdblocks/gpio.h> 7 #include <device/i2c.h> 8 #include <drivers/i2c/designware/dw_i2c.h> 9 #include <types.h> 10 11 /* Enum to identify in which mode the I2C controller is operating. */ 12 enum i2c_ctrlr_mode { 13 I2C_MASTER_MODE, 14 I2C_PERIPHERAL_MODE, 15 }; 16 17 /** 18 * Data structure to hold SoC I2C controller information 19 * @bar: MMIO base address for the I2C bus. 20 * @acpi_name: ACPI Name corresponding to the I2C bus. 21 */ 22 struct soc_i2c_ctrlr_info { 23 enum i2c_ctrlr_mode mode; 24 uintptr_t bar; 25 const char *acpi_name; 26 }; 27 28 /** 29 * Data structure to identify GPIO to be toggled to reset peripherals on an I2C bus. 30 * @pin: GPIO corresponding to I2C SCL that needs to be toggled/bit-banged. 31 * @pin_mask: Bit Mask of a single I2C bus that needs to be reset. 32 */ 33 struct soc_i2c_scl_pin { 34 struct soc_amd_gpio pin; 35 uint8_t pin_mask; 36 }; 37 38 /* Macro to populate the elements of the array of soc_i2c_scl_pin in the SoC code */ 39 #define I2C_RESET_SCL_PIN(pin_name, pin_mask_value) \ 40 { \ 41 .pin = PAD_CFG_STRUCT(pin_name, pin_name ## _IOMUX_GPIOxx, PAD_OUTPUT(HIGH)), \ 42 .pin_mask = pin_mask_value, \ 43 } 44 45 /** 46 * Information about I2C peripherals that need to be reset. 47 * @i2c_scl_reset_mask: Bit mask of I2C buses that need to be reset based on the device tree 48 * configuration. 49 * @i2c_scl: SoC specific I2C SCL pins that need to be bit-banged as part of reset 50 * procedure. 51 * @num_pins: Number of pins defined in @i2c_scl. 52 */ 53 struct soc_i2c_peripheral_reset_info { 54 uint8_t i2c_scl_reset_mask; 55 const struct soc_i2c_scl_pin *i2c_scl; 56 size_t num_pins; 57 }; 58 59 enum i2c_pad_rx_level { 60 I2C_PAD_RX_NO_CHANGE, 61 I2C_PAD_RX_OFF, 62 I2C_PAD_RX_3_3V, 63 I2C_PAD_RX_1_8V, 64 I2C_PAD_RX_1_1V, 65 }; 66 67 struct i2c_pad_control { 68 enum i2c_pad_rx_level rx_level; 69 }; 70 71 void fch_i2c_pad_init(unsigned int bus, 72 enum i2c_speed speed, 73 const struct i2c_pad_control *ctrl); 74 75 void fch_i23c_pad_init(unsigned int bus, 76 enum i2c_speed speed, 77 const struct i2c_pad_control *ctrl); 78 79 /* Helper function to perform misc I2C configuration specific to SoC. */ 80 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg); 81 82 /* Getter function to get the SoC I2C Controller Information. */ 83 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs); 84 85 /* Getter function to get the SoC I2C bus configuration. */ 86 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses); 87 88 /* Initialize all the i2c buses that are marked with early init. */ 89 void i2c_soc_early_init(void); 90 91 /* Initialize all the i2c buses that are not marked with early init. */ 92 void i2c_soc_init(void); 93 94 /* Reset I2C peripherals. */ 95 void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info); 96 97 #endif /* AMD_COMMON_BLOCK_I2C_H */ 98