1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_RESET_H 4 #define AMD_BLOCK_RESET_H 5 6 #include <amdblocks/acpimmio.h> 7 #include <arch/cache.h> 8 #include <console/console.h> 9 #include <halt.h> 10 #include <soc/southbridge.h> 11 12 void do_warm_reset(void); 13 void do_cold_reset(void); 14 void set_warm_reset_flag(void); 15 int is_warm_reset(void); 16 warm_reset(void)17static inline __noreturn void warm_reset(void) 18 { 19 printk(BIOS_INFO, "%s() called!\n", __func__); 20 dcache_clean_all(); 21 do_warm_reset(); 22 halt(); 23 } 24 cold_reset(void)25static inline __noreturn void cold_reset(void) 26 { 27 printk(BIOS_INFO, "%s() called!\n", __func__); 28 dcache_clean_all(); 29 do_cold_reset(); 30 halt(); 31 } 32 set_resets_to_cold(void)33static inline void set_resets_to_cold(void) 34 { 35 /* De-assert and then assert all PwrGood signals on CF9 reset. */ 36 pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); 37 } 38 39 #endif /* AMD_BLOCK_RESET_H */ 40