1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef AMD_BLOCK_SMBUS_H 4 #define AMD_BLOCK_SMBUS_H 5 6 /* SMBUS MMIO offsets 0xfed80a00 */ 7 #define SMBHSTSTAT 0x0 8 #define SMBHST_STAT_FAILED (1 << 4) 9 #define SMBHST_STAT_COLLISION (1 << 3) 10 #define SMBHST_STAT_ERROR (1 << 2) 11 #define SMBHST_STAT_INTERRUPT (1 << 1) 12 #define SMBHST_STAT_BUSY (1 << 0) 13 #define SMBHST_STAT_CLEAR 0xff 14 #define SMBHST_STAT_VAL_BITS 0x1f 15 #define SMBHST_STAT_ERROR_BITS 0x1c 16 17 #define SMBSLVSTAT 0x1 18 #define SMBSLV_STAT_ALERT (1 << 5) 19 #define SMBSLV_STAT_SHADOW2 (1 << 4) 20 #define SMBSLV_STAT_SHADOW1 (1 << 3) 21 #define SMBSLV_STAT_SLV_STS (1 << 2) 22 #define SMBSLV_STAT_SLV_INIT (1 << 1) 23 #define SMBSLV_STAT_SLV_BUSY (1 << 0) 24 #define SMBSLV_STAT_CLEAR 0x1f 25 26 #define SMBHSTCTRL 0x2 27 #define SMBHST_CTRL_RST (1 << 7) 28 #define SMBHST_CTRL_STRT (1 << 6) 29 #define SMBHST_CTRL_QCK_RW (0x0 << 2) 30 #define SMBHST_CTRL_BTE_RW (0x1 << 2) 31 #define SMBHST_CTRL_BDT_RW (0x2 << 2) 32 #define SMBHST_CTRL_WDT_RW (0x3 << 2) 33 #define SMBHST_CTRL_BLK_RW (0x5 << 2) 34 #define SMBHST_CTRL_MODE_BITS (0x7 << 2) 35 #define SMBHST_CTRL_KILL (1 << 1) 36 #define SMBHST_CTRL_IEN (1 << 0) 37 38 #define SMBHSTCMD 0x3 39 #define SMBHSTADDR 0x4 40 #define SMBHSTDAT0 0x5 41 #define SMBHSTDAT1 0x6 42 #define SMBHSTBLKDAT 0x7 43 #define SMBSLVCTRL 0x8 44 #define SMBSLVCMD_SHADOW 0x9 45 #define SMBSLVEVT 0xa 46 #define SMBSLVDAT 0xc 47 #define SMBTIMING 0xe 48 49 void fch_smbus_init(void); 50 51 #endif /* AMD_BLOCK_SMBUS_H */ 52