1 /*
2 * Copyright (c) 2016, Alliance for Open Media. All rights reserved.
3 *
4 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10 */
11
12 #ifndef AOM_AOM_PORTS_X86_H_
13 #define AOM_AOM_PORTS_X86_H_
14 #include <stdlib.h>
15
16 #if defined(_MSC_VER)
17 #include <intrin.h> /* For __cpuidex, __rdtsc */
18 #endif
19
20 #include "aom/aom_integer.h"
21 #include "config/aom_config.h"
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 typedef enum {
28 AOM_CPU_UNKNOWN = -1,
29 AOM_CPU_AMD,
30 AOM_CPU_AMD_OLD,
31 AOM_CPU_CENTAUR,
32 AOM_CPU_CYRIX,
33 AOM_CPU_INTEL,
34 AOM_CPU_NEXGEN,
35 AOM_CPU_NSC,
36 AOM_CPU_RISE,
37 AOM_CPU_SIS,
38 AOM_CPU_TRANSMETA,
39 AOM_CPU_TRANSMETA_OLD,
40 AOM_CPU_UMC,
41 AOM_CPU_VIA,
42
43 AOM_CPU_LAST
44 } aom_cpu_t;
45
46 #if defined(__GNUC__) || defined(__ANDROID__)
47 #if AOM_ARCH_X86_64
48 #define cpuid(func, func2, ax, bx, cx, dx) \
49 __asm__ __volatile__("cpuid \n\t" \
50 : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \
51 : "a"(func), "c"(func2))
52 #else
53 #define cpuid(func, func2, ax, bx, cx, dx) \
54 __asm__ __volatile__( \
55 "mov %%ebx, %%edi \n\t" \
56 "cpuid \n\t" \
57 "xchg %%edi, %%ebx \n\t" \
58 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
59 : "a"(func), "c"(func2))
60 #endif
61 #elif defined(__SUNPRO_C) || \
62 defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
63 #if AOM_ARCH_X86_64
64 #define cpuid(func, func2, ax, bx, cx, dx) \
65 asm volatile( \
66 "xchg %rsi, %rbx \n\t" \
67 "cpuid \n\t" \
68 "movl %ebx, %edi \n\t" \
69 "xchg %rsi, %rbx \n\t" \
70 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
71 : "a"(func), "c"(func2))
72 #else
73 #define cpuid(func, func2, ax, bx, cx, dx) \
74 asm volatile( \
75 "pushl %ebx \n\t" \
76 "cpuid \n\t" \
77 "movl %ebx, %edi \n\t" \
78 "popl %ebx \n\t" \
79 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
80 : "a"(func), "c"(func2))
81 #endif
82 #else /* end __SUNPRO__ */
83 #if AOM_ARCH_X86_64
84 #if defined(_MSC_VER) && _MSC_VER > 1500
85 #define cpuid(func, func2, a, b, c, d) \
86 do { \
87 int regs[4]; \
88 __cpuidex(regs, func, func2); \
89 a = regs[0]; \
90 b = regs[1]; \
91 c = regs[2]; \
92 d = regs[3]; \
93 } while (0)
94 #else
95 #define cpuid(func, func2, a, b, c, d) \
96 do { \
97 int regs[4]; \
98 __cpuid(regs, func); \
99 a = regs[0]; \
100 b = regs[1]; \
101 c = regs[2]; \
102 d = regs[3]; \
103 } while (0)
104 #endif
105 #else
106 /* clang-format off */
107 #define cpuid(func, func2, a, b, c, d) \
108 __asm mov eax, func \
109 __asm mov ecx, func2 \
110 __asm cpuid \
111 __asm mov a, eax \
112 __asm mov b, ebx \
113 __asm mov c, ecx \
114 __asm mov d, edx
115 #endif
116 /* clang-format on */
117 #endif /* end others */
118
119 // NaCl has no support for xgetbv or the raw opcode.
120 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
xgetbv(void)121 static inline uint64_t xgetbv(void) {
122 const uint32_t ecx = 0;
123 uint32_t eax, edx;
124 // Use the raw opcode for xgetbv for compatibility with older toolchains.
125 __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n"
126 : "=a"(eax), "=d"(edx)
127 : "c"(ecx));
128 return ((uint64_t)edx << 32) | eax;
129 }
130 #elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \
131 _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
132 #include <immintrin.h>
133 #define xgetbv() _xgetbv(0)
134 #elif defined(_MSC_VER) && defined(_M_IX86)
xgetbv(void)135 static inline uint64_t xgetbv(void) {
136 uint32_t eax_, edx_;
137 __asm {
138 xor ecx, ecx // ecx = 0
139 // Use the raw opcode for xgetbv for compatibility with older toolchains.
140 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
141 mov eax_, eax
142 mov edx_, edx
143 }
144 return ((uint64_t)edx_ << 32) | eax_;
145 }
146 #else
147 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
148 #endif
149
150 #if defined(_MSC_VER) && _MSC_VER >= 1700
151 #undef NOMINMAX
152 #define NOMINMAX
153 #undef WIN32_LEAN_AND_MEAN
154 #define WIN32_LEAN_AND_MEAN
155 #include <windows.h>
156 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
157 #define getenv(x) NULL
158 #endif
159 #endif
160
161 #define HAS_MMX 0x01
162 #define HAS_SSE 0x02
163 #define HAS_SSE2 0x04
164 #define HAS_SSE3 0x08
165 #define HAS_SSSE3 0x10
166 #define HAS_SSE4_1 0x20
167 #define HAS_AVX 0x40
168 #define HAS_AVX2 0x80
169 #define HAS_SSE4_2 0x100
170 #ifndef BIT
171 #define BIT(n) (1u << (n))
172 #endif
173
x86_simd_caps(void)174 static inline int x86_simd_caps(void) {
175 unsigned int flags = 0;
176 unsigned int mask = ~0u;
177 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
178 char *env;
179
180 /* See if the CPU capabilities are being overridden by the environment */
181 env = getenv("AOM_SIMD_CAPS");
182
183 if (env && *env) return (int)strtol(env, NULL, 0);
184
185 env = getenv("AOM_SIMD_CAPS_MASK");
186
187 if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0);
188
189 /* Ensure that the CPUID instruction supports extended features */
190 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
191
192 if (max_cpuid_val < 1) return 0;
193
194 /* Get the standard feature flags */
195 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
196
197 if (reg_edx & BIT(23)) flags |= HAS_MMX;
198
199 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
200
201 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
202
203 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
204
205 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
206
207 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
208
209 if (reg_ecx & BIT(20)) flags |= HAS_SSE4_2;
210
211 // bits 27 (OSXSAVE) & 28 (256-bit AVX)
212 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
213 // Check for OS-support of YMM state. Necessary for AVX and AVX2.
214 if ((xgetbv() & 0x6) == 0x6) {
215 flags |= HAS_AVX;
216
217 if (max_cpuid_val >= 7) {
218 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
219 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
220
221 if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
222 }
223 }
224 }
225
226 (void)reg_eax; // Avoid compiler warning on unused-but-set variable.
227
228 return flags & mask;
229 }
230
231 // Fine-Grain Measurement Functions
232 //
233 // If you are timing a small region of code, access the timestamp counter
234 // (TSC) via:
235 //
236 // unsigned int start = x86_tsc_start();
237 // ...
238 // unsigned int end = x86_tsc_end();
239 // unsigned int diff = end - start;
240 //
241 // The start/end functions introduce a few more instructions than using
242 // x86_readtsc directly, but prevent the CPU's out-of-order execution from
243 // affecting the measurement (by having earlier/later instructions be evaluated
244 // in the time interval). See the white paper, "How to Benchmark Code
245 // Execution Times on Intel(R) IA-32 and IA-64 Instruction Set Architectures" by
246 // Gabriele Paoloni for more information.
247 //
248 // If you are timing a large function (CPU time > a couple of seconds), use
249 // x86_readtsc64 to read the timestamp counter in a 64-bit integer. The
250 // out-of-order leakage that can occur is minimal compared to total runtime.
x86_readtsc(void)251 static inline unsigned int x86_readtsc(void) {
252 #if defined(__GNUC__)
253 unsigned int tsc;
254 __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :);
255 return tsc;
256 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
257 unsigned int tsc;
258 asm volatile("rdtsc\n\t" : "=a"(tsc) :);
259 return tsc;
260 #else
261 #if AOM_ARCH_X86_64
262 return (unsigned int)__rdtsc();
263 #else
264 __asm rdtsc;
265 #endif
266 #endif
267 }
268 // 64-bit CPU cycle counter
x86_readtsc64(void)269 static inline uint64_t x86_readtsc64(void) {
270 #if defined(__GNUC__)
271 uint32_t hi, lo;
272 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
273 return ((uint64_t)hi << 32) | lo;
274 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
275 uint_t hi, lo;
276 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
277 return ((uint64_t)hi << 32) | lo;
278 #else
279 #if AOM_ARCH_X86_64
280 return (uint64_t)__rdtsc();
281 #else
282 __asm rdtsc;
283 #endif
284 #endif
285 }
286
287 // 32-bit CPU cycle counter with a partial fence against out-of-order execution.
x86_readtscp(void)288 static inline unsigned int x86_readtscp(void) {
289 #if defined(__GNUC__)
290 unsigned int tscp;
291 __asm__ __volatile__("rdtscp\n\t" : "=a"(tscp) :);
292 return tscp;
293 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
294 unsigned int tscp;
295 asm volatile("rdtscp\n\t" : "=a"(tscp) :);
296 return tscp;
297 #elif defined(_MSC_VER)
298 unsigned int ui;
299 return (unsigned int)__rdtscp(&ui);
300 #else
301 #if AOM_ARCH_X86_64
302 return (unsigned int)__rdtscp();
303 #else
304 __asm rdtscp;
305 #endif
306 #endif
307 }
308
x86_tsc_start(void)309 static inline unsigned int x86_tsc_start(void) {
310 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
311 // This call should not be removed. See function notes above.
312 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
313 // Avoid compiler warnings on unused-but-set variables.
314 (void)reg_eax;
315 (void)reg_ebx;
316 (void)reg_ecx;
317 (void)reg_edx;
318 return x86_readtsc();
319 }
320
x86_tsc_end(void)321 static inline unsigned int x86_tsc_end(void) {
322 uint32_t v = x86_readtscp();
323 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
324 // This call should not be removed. See function notes above.
325 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
326 // Avoid compiler warnings on unused-but-set variables.
327 (void)reg_eax;
328 (void)reg_ebx;
329 (void)reg_ecx;
330 (void)reg_edx;
331 return v;
332 }
333
334 #if defined(__GNUC__)
335 #define x86_pause_hint() __asm__ __volatile__("pause \n\t")
336 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
337 #define x86_pause_hint() asm volatile("pause \n\t")
338 #else
339 #if AOM_ARCH_X86_64
340 #define x86_pause_hint() _mm_pause();
341 #else
342 #define x86_pause_hint() __asm pause
343 #endif
344 #endif
345
346 #if defined(__GNUC__)
x87_set_control_word(unsigned short mode)347 static void x87_set_control_word(unsigned short mode) {
348 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
349 }
x87_get_control_word(void)350 static unsigned short x87_get_control_word(void) {
351 unsigned short mode;
352 __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :);
353 return mode;
354 }
355 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
x87_set_control_word(unsigned short mode)356 static void x87_set_control_word(unsigned short mode) {
357 asm volatile("fldcw %0" : : "m"(*&mode));
358 }
x87_get_control_word(void)359 static unsigned short x87_get_control_word(void) {
360 unsigned short mode;
361 asm volatile("fstcw %0\n\t" : "=m"(*&mode) :);
362 return mode;
363 }
364 #elif AOM_ARCH_X86_64
365 /* No fldcw intrinsics on Windows x64, punt to external asm */
366 extern void aom_winx64_fldcw(unsigned short mode);
367 extern unsigned short aom_winx64_fstcw(void);
368 #define x87_set_control_word aom_winx64_fldcw
369 #define x87_get_control_word aom_winx64_fstcw
370 #else
x87_set_control_word(unsigned short mode)371 static void x87_set_control_word(unsigned short mode) {
372 __asm { fldcw mode }
373 }
x87_get_control_word(void)374 static unsigned short x87_get_control_word(void) {
375 unsigned short mode;
376 __asm { fstcw mode }
377 return mode;
378 }
379 #endif
380
x87_set_double_precision(void)381 static inline unsigned int x87_set_double_precision(void) {
382 unsigned int mode = x87_get_control_word();
383 // Intel 64 and IA-32 Architectures Developer's Manual: Vol. 1
384 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
385 // 8.1.5.2 Precision Control Field
386 // Bits 8 and 9 (0x300) of the x87 FPU Control Word ("Precision Control")
387 // determine the number of bits used in floating point calculations. To match
388 // later SSE instructions restrict x87 operations to Double Precision (0x200).
389 // Precision PC Field
390 // Single Precision (24-Bits) 00B
391 // Reserved 01B
392 // Double Precision (53-Bits) 10B
393 // Extended Precision (64-Bits) 11B
394 x87_set_control_word((mode & ~0x300u) | 0x200u);
395 return mode;
396 }
397
398 #ifdef __cplusplus
399 } // extern "C"
400 #endif
401
402 #endif // AOM_AOM_PORTS_X86_H_
403