1 /* 2 * Copyright (c) 2023 Google Inc. All rights reserved 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files 6 * (the "Software"), to deal in the Software without restriction, 7 * including without limitation the rights to use, copy, modify, merge, 8 * publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, 10 * subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 /* 27 * PAuth key special registers 28 */ 29 30 #define APIAKeyLo_EL1 s3_0_c2_c1_0 31 #define APIAKeyHi_EL1 s3_0_c2_c1_1 32 #define APIBKeyLo_EL1 s3_0_c2_c1_2 33 #define APIBKeyHi_EL1 s3_0_c2_c1_3 34 #define APDAKeyLo_EL1 s3_0_c2_c2_0 35 #define APDAKeyHi_EL1 s3_0_c2_c2_1 36 #define APDBKeyLo_EL1 s3_0_c2_c2_2 37 #define APDBKeyHi_EL1 s3_0_c2_c2_3 38 #define APGAKeyLo_EL1 s3_0_c2_c3_0 39 #define APGAKeyHi_EL1 s3_0_c2_c3_1 40 41 /* 42 * CPACR_EL1 - Architectural Feature Access Control Register 43 */ 44 45 #define CPACR_EL1_FPEN_SHIFT 20u 46 #define CPACR_EL1_FPEN_SVE_ENABLE 0x3 47 #define CPACR_EL1_FPEN_SVE_DISABLE 0x0 48 49 #define CPACR_EL1_ZEN_SHIFT 16u 50 #define CPACR_EL1_ZEN_SVE_ENABLE 0x3 51 #define CPACR_EL1_ZEN_SVE_DISABLE 0x0 52 53 /* 54 * SCTLR_EL1 bits 55 */ 56 57 /* PACIxSP as as valid jump targets for BTI */ 58 #define SCTLR_EL1_BT0 (1llu << 35u) 59 #define SCTLR_EL1_BT1 (1llu << 36u) 60 61 /* PAuth key enabling bits in SCTLR_EL1 */ 62 #define SCTLR_EL1_ENIA (1llu << 31u) 63 #define SCTLR_EL1_ENIB (1llu << 30u) 64 #define SCTLR_EL1_ENDA (1llu << 27u) 65 #define SCTLR_EL1_ENDB (1llu << 13u) 66 67 /* WXN - Writable implies Execute Never */ 68 #define SCTLR_EL1_WXN (1llu << 19u) 69 70 /* PAN */ 71 #define SCTLR_EL1_SPAN_SHIFT 23u /* SPAN is from FEAT_PAN1 */ 72 #define SCTLR_EL1_EPAN_SHIFT 57u /* EPAN is from FEAT_PAN3 */ 73 74 /* 75 * ID_AA64ISAR1_EL1 bits - Instruction Set Attribute Register 1 76 */ 77 78 #define ID_AA64ISAR1_EL1_GPI_SHIFT 28u 79 #define ID_AA64ISAR1_EL1_GPI_MASK 0xfu 80 #define ID_AA64ISAR1_EL1_GPA_SHIFT 28u 81 #define ID_AA64ISAR1_EL1_GPA_MASK 0xfu 82 #define ID_AA64ISAR1_EL1_API_SHIFT 8u 83 #define ID_AA64ISAR1_EL1_API_MASK 0xfu 84 #define ID_AA64ISAR1_EL1_APA_SHIFT 4u 85 #define ID_AA64ISAR1_EL1_APA_MASK 0xfu 86 87 /* 88 * ID_AA64ISAR2_EL1 bits - Instruction Set Attribute Register 2 89 */ 90 91 #define ID_AA64ISAR2_EL1_PAC_FRAC_SHIFT 24u 92 #define ID_AA64ISAR2_EL1_PAC_FRAC_MASK 0xfu 93 #define ID_AA64ISAR2_EL1_APA3_SHIFT 12u 94 #define ID_AA64ISAR2_EL1_APA3_MASK 0xfu 95 #define ID_AA64ISAR2_EL1_GPA3_SHIFT 8u 96 #define ID_AA64ISAR2_EL1_GPA3_MASK 0xf4 97 98 /* 99 * ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1 100 */ 101 102 #define ID_AA64MMFR1_EL1_PAN_SHIFT 20u 103 #define ID_AA64MMFR1_EL1_PAN_MASK 0xfu 104 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED 0x0u 105 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED 0x1u 106 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED 0x2u 107 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED 0x3u 108 109 /* 110 * ID_AA64PFR0 - AArch64 Processor Feature Register 0 111 */ 112 113 #define ID_AA64PFR0_EL1_SVE_SHIFT 32u 114 #define ID_AA64PFR0_EL1_SVE_MASK 0xf 115 #define ID_AA64PFR0_EL1_SVE_SUPPORTED 0x1u 116 117 /* 118 * ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 119 */ 120 121 #define ID_AA64PFR1_EL1_BTI_SHIFT 0u 122 #define ID_AA64PFR1_EL1_BIT_MASK 0xfu 123 #define ID_AA64PFR1_EL1_BTI_NOT_SUPPORTED 0x0u 124 #define ID_AA64PFR1_EL1_BTI_SUPPORTED 0x1u 125 126 /* 127 * PAN - Privileged Access Never 128 */ 129 130 #define PAN s3_0_c4_c2_3 131 132 #define PAN_PAN_SHIFT 22u 133 #define PAN_PAN_MASK 0x1ull 134