1 /* SPDX-License-Identifier: BSD-4-Clause-UC */ 2 3 #ifndef RISCV_CSR_ENCODING_H 4 #define RISCV_CSR_ENCODING_H 5 6 #define MSTATUS_UIE 0x00000001 7 #define MSTATUS_SIE 0x00000002 8 #define MSTATUS_HIE 0x00000004 9 #define MSTATUS_MIE 0x00000008 10 #define MSTATUS_UPIE 0x00000010 11 #define MSTATUS_SPIE 0x00000020 12 #define MSTATUS_HPIE 0x00000040 13 #define MSTATUS_MPIE 0x00000080 14 #define MSTATUS_SPP 0x00000100 15 #define MSTATUS_HPP 0x00000600 16 #define MSTATUS_MPP 0x00001800 17 #define MSTATUS_FS 0x00006000 18 #define MSTATUS_XS 0x00018000 19 #define MSTATUS_MPRV 0x00020000 20 #define MSTATUS_SUM 0x00040000 21 #define MSTATUS_MXR 0x00080000 22 #define MSTATUS_TVM 0x00100000 23 #define MSTATUS_TW 0x00200000 24 #define MSTATUS_TSR 0x00400000 25 #define MSTATUS32_SD 0x80000000 26 #define MSTATUS_UXL 0x0000000300000000 27 #define MSTATUS_SXL 0x0000000C00000000 28 #define MSTATUS64_SD 0x8000000000000000 29 30 #define SSTATUS_UIE 0x00000001 31 #define SSTATUS_SIE 0x00000002 32 #define SSTATUS_UPIE 0x00000010 33 #define SSTATUS_SPIE 0x00000020 34 #define SSTATUS_SPP 0x00000100 35 #define SSTATUS_FS 0x00006000 36 #define SSTATUS_XS 0x00018000 37 #define SSTATUS_SUM 0x00040000 38 #define SSTATUS_MXR 0x00080000 39 #define SSTATUS32_SD 0x80000000 40 #define SSTATUS_UXL 0x0000000300000000 41 #define SSTATUS64_SD 0x8000000000000000 42 43 #define DCSR_XDEBUGVER (3U<<30) 44 #define DCSR_NDRESET (1<<29) 45 #define DCSR_FULLRESET (1<<28) 46 #define DCSR_EBREAKM (1<<15) 47 #define DCSR_EBREAKH (1<<14) 48 #define DCSR_EBREAKS (1<<13) 49 #define DCSR_EBREAKU (1<<12) 50 #define DCSR_STOPCYCLE (1<<10) 51 #define DCSR_STOPTIME (1<<9) 52 #define DCSR_CAUSE (7<<6) 53 #define DCSR_DEBUGINT (1<<5) 54 #define DCSR_HALT (1<<3) 55 #define DCSR_STEP (1<<2) 56 #define DCSR_PRV (3<<0) 57 58 #define DCSR_CAUSE_NONE 0 59 #define DCSR_CAUSE_SWBP 1 60 #define DCSR_CAUSE_HWBP 2 61 #define DCSR_CAUSE_DEBUGINT 3 62 #define DCSR_CAUSE_STEP 4 63 #define DCSR_CAUSE_HALT 5 64 65 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 66 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 67 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 68 69 #define MCONTROL_SELECT (1<<19) 70 #define MCONTROL_TIMING (1<<18) 71 #define MCONTROL_ACTION (0x3f<<12) 72 #define MCONTROL_CHAIN (1<<11) 73 #define MCONTROL_MATCH (0xf<<7) 74 #define MCONTROL_M (1<<6) 75 #define MCONTROL_H (1<<5) 76 #define MCONTROL_S (1<<4) 77 #define MCONTROL_U (1<<3) 78 #define MCONTROL_EXECUTE (1<<2) 79 #define MCONTROL_STORE (1<<1) 80 #define MCONTROL_LOAD (1<<0) 81 82 #define MCONTROL_TYPE_NONE 0 83 #define MCONTROL_TYPE_MATCH 2 84 85 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 86 #define MCONTROL_ACTION_DEBUG_MODE 1 87 #define MCONTROL_ACTION_TRACE_START 2 88 #define MCONTROL_ACTION_TRACE_STOP 3 89 #define MCONTROL_ACTION_TRACE_EMIT 4 90 91 #define MCONTROL_MATCH_EQUAL 0 92 #define MCONTROL_MATCH_NAPOT 1 93 #define MCONTROL_MATCH_GE 2 94 #define MCONTROL_MATCH_LT 3 95 #define MCONTROL_MATCH_MASK_LOW 4 96 #define MCONTROL_MATCH_MASK_HIGH 5 97 98 #define MIP_SSIP (1 << IRQ_S_SOFT) 99 #define MIP_HSIP (1 << IRQ_H_SOFT) 100 #define MIP_MSIP (1 << IRQ_M_SOFT) 101 #define MIP_STIP (1 << IRQ_S_TIMER) 102 #define MIP_HTIP (1 << IRQ_H_TIMER) 103 #define MIP_MTIP (1 << IRQ_M_TIMER) 104 #define MIP_SEIP (1 << IRQ_S_EXT) 105 #define MIP_HEIP (1 << IRQ_H_EXT) 106 #define MIP_MEIP (1 << IRQ_M_EXT) 107 108 #define SIP_SSIP MIP_SSIP 109 #define SIP_STIP MIP_STIP 110 111 #define PRV_U 0 112 #define PRV_S 1 113 #define PRV_H 2 114 #define PRV_M 3 115 116 #define SATP32_MODE 0x80000000 117 #define SATP32_ASID 0x7FC00000 118 #define SATP32_PPN 0x003FFFFF 119 #define SATP64_MODE 0xF000000000000000 120 #define SATP64_ASID 0x0FFFF00000000000 121 #define SATP64_PPN 0x00000FFFFFFFFFFF 122 123 #define SATP_MODE_OFF 0 124 #define SATP_MODE_SV32 1 125 #define SATP_MODE_SV39 8 126 #define SATP_MODE_SV48 9 127 #define SATP_MODE_SV57 10 128 #define SATP_MODE_SV64 11 129 130 #define PMP_R 0x01 131 #define PMP_W 0x02 132 #define PMP_X 0x04 133 #define PMP_A 0x18 134 #define PMP_L 0x80 135 #define PMP_SHIFT 2 136 137 #define PMP_TOR 0x08 138 #define PMP_NA4 0x10 139 #define PMP_NAPOT 0x18 140 141 #define IRQ_S_SOFT 1 142 #define IRQ_H_SOFT 2 143 #define IRQ_M_SOFT 3 144 #define IRQ_S_TIMER 5 145 #define IRQ_H_TIMER 6 146 #define IRQ_M_TIMER 7 147 #define IRQ_S_EXT 9 148 #define IRQ_H_EXT 10 149 #define IRQ_M_EXT 11 150 #define IRQ_COP 12 151 #define IRQ_HOST 13 152 153 #define DEFAULT_RSTVEC 0x00001000 154 #define CLINT_BASE 0x02000000 155 #define CLINT_SIZE 0x000c0000 156 #define EXT_IO_BASE 0x40000000 157 #define DRAM_BASE 0x80000000 158 159 // page table entry (PTE) fields 160 #define PTE_V 0x001 // Valid 161 #define PTE_R 0x002 // Read 162 #define PTE_W 0x004 // Write 163 #define PTE_X 0x008 // Execute 164 #define PTE_U 0x010 // User 165 #define PTE_G 0x020 // Global 166 #define PTE_A 0x040 // Accessed 167 #define PTE_D 0x080 // Dirty 168 #define PTE_SOFT 0x300 // Reserved for Software 169 170 #define PTE_PPN_SHIFT 10 171 172 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 173 174 #ifdef __riscv 175 176 #if __riscv_xlen == 64 177 # define MSTATUS_SD MSTATUS64_SD 178 # define SSTATUS_SD SSTATUS64_SD 179 # define RISCV_PGLEVEL_BITS 9 180 # define SATP_MODE SATP64_MODE 181 #else 182 # define MSTATUS_SD MSTATUS32_SD 183 # define SSTATUS_SD SSTATUS32_SD 184 # define RISCV_PGLEVEL_BITS 10 185 # define SATP_MODE SATP32_MODE 186 #endif 187 #define RISCV_PGSHIFT 12 188 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 189 190 #ifndef __ASSEMBLER__ 191 192 #ifdef __GNUC__ 193 194 #define read_csr(reg) ({ unsigned long __tmp; \ 195 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 196 __tmp; }) 197 198 #define write_csr(reg, val) ({ \ 199 asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) 200 201 #define swap_csr(reg, val) ({ unsigned long __tmp; \ 202 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ 203 __tmp; }) 204 205 #define set_csr(reg, bit) ({ unsigned long __tmp; \ 206 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 207 __tmp; }) 208 209 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 210 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 211 __tmp; }) 212 213 #define rdtime() read_csr(time) 214 #define rdcycle() read_csr(cycle) 215 #define rdinstret() read_csr(instret) 216 217 #endif 218 219 #endif 220 221 #endif 222 223 #endif 224 /* Automatically generated by parse-opcodes. */ 225 #ifndef RISCV_ENCODING_H 226 #define RISCV_ENCODING_H 227 #define MATCH_BEQ 0x63 228 #define MASK_BEQ 0x707f 229 #define MATCH_BNE 0x1063 230 #define MASK_BNE 0x707f 231 #define MATCH_BLT 0x4063 232 #define MASK_BLT 0x707f 233 #define MATCH_BGE 0x5063 234 #define MASK_BGE 0x707f 235 #define MATCH_BLTU 0x6063 236 #define MASK_BLTU 0x707f 237 #define MATCH_BGEU 0x7063 238 #define MASK_BGEU 0x707f 239 #define MATCH_JALR 0x67 240 #define MASK_JALR 0x707f 241 #define MATCH_JAL 0x6f 242 #define MASK_JAL 0x7f 243 #define MATCH_LUI 0x37 244 #define MASK_LUI 0x7f 245 #define MATCH_AUIPC 0x17 246 #define MASK_AUIPC 0x7f 247 #define MATCH_ADDI 0x13 248 #define MASK_ADDI 0x707f 249 #define MATCH_SLLI 0x1013 250 #define MASK_SLLI 0xfc00707f 251 #define MATCH_SLTI 0x2013 252 #define MASK_SLTI 0x707f 253 #define MATCH_SLTIU 0x3013 254 #define MASK_SLTIU 0x707f 255 #define MATCH_XORI 0x4013 256 #define MASK_XORI 0x707f 257 #define MATCH_SRLI 0x5013 258 #define MASK_SRLI 0xfc00707f 259 #define MATCH_SRAI 0x40005013 260 #define MASK_SRAI 0xfc00707f 261 #define MATCH_ORI 0x6013 262 #define MASK_ORI 0x707f 263 #define MATCH_ANDI 0x7013 264 #define MASK_ANDI 0x707f 265 #define MATCH_ADD 0x33 266 #define MASK_ADD 0xfe00707f 267 #define MATCH_SUB 0x40000033 268 #define MASK_SUB 0xfe00707f 269 #define MATCH_SLL 0x1033 270 #define MASK_SLL 0xfe00707f 271 #define MATCH_SLT 0x2033 272 #define MASK_SLT 0xfe00707f 273 #define MATCH_SLTU 0x3033 274 #define MASK_SLTU 0xfe00707f 275 #define MATCH_XOR 0x4033 276 #define MASK_XOR 0xfe00707f 277 #define MATCH_SRL 0x5033 278 #define MASK_SRL 0xfe00707f 279 #define MATCH_SRA 0x40005033 280 #define MASK_SRA 0xfe00707f 281 #define MATCH_OR 0x6033 282 #define MASK_OR 0xfe00707f 283 #define MATCH_AND 0x7033 284 #define MASK_AND 0xfe00707f 285 #define MATCH_ADDIW 0x1b 286 #define MASK_ADDIW 0x707f 287 #define MATCH_SLLIW 0x101b 288 #define MASK_SLLIW 0xfe00707f 289 #define MATCH_SRLIW 0x501b 290 #define MASK_SRLIW 0xfe00707f 291 #define MATCH_SRAIW 0x4000501b 292 #define MASK_SRAIW 0xfe00707f 293 #define MATCH_ADDW 0x3b 294 #define MASK_ADDW 0xfe00707f 295 #define MATCH_SUBW 0x4000003b 296 #define MASK_SUBW 0xfe00707f 297 #define MATCH_SLLW 0x103b 298 #define MASK_SLLW 0xfe00707f 299 #define MATCH_SRLW 0x503b 300 #define MASK_SRLW 0xfe00707f 301 #define MATCH_SRAW 0x4000503b 302 #define MASK_SRAW 0xfe00707f 303 #define MATCH_LB 0x3 304 #define MASK_LB 0x707f 305 #define MATCH_LH 0x1003 306 #define MASK_LH 0x707f 307 #define MATCH_LW 0x2003 308 #define MASK_LW 0x707f 309 #define MATCH_LD 0x3003 310 #define MASK_LD 0x707f 311 #define MATCH_LBU 0x4003 312 #define MASK_LBU 0x707f 313 #define MATCH_LHU 0x5003 314 #define MASK_LHU 0x707f 315 #define MATCH_LWU 0x6003 316 #define MASK_LWU 0x707f 317 #define MATCH_SB 0x23 318 #define MASK_SB 0x707f 319 #define MATCH_SH 0x1023 320 #define MASK_SH 0x707f 321 #define MATCH_SW 0x2023 322 #define MASK_SW 0x707f 323 #define MATCH_SD 0x3023 324 #define MASK_SD 0x707f 325 #define MATCH_FENCE 0xf 326 #define MASK_FENCE 0x707f 327 #define MATCH_FENCE_I 0x100f 328 #define MASK_FENCE_I 0x707f 329 #define MATCH_MUL 0x2000033 330 #define MASK_MUL 0xfe00707f 331 #define MATCH_MULH 0x2001033 332 #define MASK_MULH 0xfe00707f 333 #define MATCH_MULHSU 0x2002033 334 #define MASK_MULHSU 0xfe00707f 335 #define MATCH_MULHU 0x2003033 336 #define MASK_MULHU 0xfe00707f 337 #define MATCH_DIV 0x2004033 338 #define MASK_DIV 0xfe00707f 339 #define MATCH_DIVU 0x2005033 340 #define MASK_DIVU 0xfe00707f 341 #define MATCH_REM 0x2006033 342 #define MASK_REM 0xfe00707f 343 #define MATCH_REMU 0x2007033 344 #define MASK_REMU 0xfe00707f 345 #define MATCH_MULW 0x200003b 346 #define MASK_MULW 0xfe00707f 347 #define MATCH_DIVW 0x200403b 348 #define MASK_DIVW 0xfe00707f 349 #define MATCH_DIVUW 0x200503b 350 #define MASK_DIVUW 0xfe00707f 351 #define MATCH_REMW 0x200603b 352 #define MASK_REMW 0xfe00707f 353 #define MATCH_REMUW 0x200703b 354 #define MASK_REMUW 0xfe00707f 355 #define MATCH_AMOADD_W 0x202f 356 #define MASK_AMOADD_W 0xf800707f 357 #define MATCH_AMOXOR_W 0x2000202f 358 #define MASK_AMOXOR_W 0xf800707f 359 #define MATCH_AMOOR_W 0x4000202f 360 #define MASK_AMOOR_W 0xf800707f 361 #define MATCH_AMOAND_W 0x6000202f 362 #define MASK_AMOAND_W 0xf800707f 363 #define MATCH_AMOMIN_W 0x8000202f 364 #define MASK_AMOMIN_W 0xf800707f 365 #define MATCH_AMOMAX_W 0xa000202f 366 #define MASK_AMOMAX_W 0xf800707f 367 #define MATCH_AMOMINU_W 0xc000202f 368 #define MASK_AMOMINU_W 0xf800707f 369 #define MATCH_AMOMAXU_W 0xe000202f 370 #define MASK_AMOMAXU_W 0xf800707f 371 #define MATCH_AMOSWAP_W 0x800202f 372 #define MASK_AMOSWAP_W 0xf800707f 373 #define MATCH_LR_W 0x1000202f 374 #define MASK_LR_W 0xf9f0707f 375 #define MATCH_SC_W 0x1800202f 376 #define MASK_SC_W 0xf800707f 377 #define MATCH_AMOADD_D 0x302f 378 #define MASK_AMOADD_D 0xf800707f 379 #define MATCH_AMOXOR_D 0x2000302f 380 #define MASK_AMOXOR_D 0xf800707f 381 #define MATCH_AMOOR_D 0x4000302f 382 #define MASK_AMOOR_D 0xf800707f 383 #define MATCH_AMOAND_D 0x6000302f 384 #define MASK_AMOAND_D 0xf800707f 385 #define MATCH_AMOMIN_D 0x8000302f 386 #define MASK_AMOMIN_D 0xf800707f 387 #define MATCH_AMOMAX_D 0xa000302f 388 #define MASK_AMOMAX_D 0xf800707f 389 #define MATCH_AMOMINU_D 0xc000302f 390 #define MASK_AMOMINU_D 0xf800707f 391 #define MATCH_AMOMAXU_D 0xe000302f 392 #define MASK_AMOMAXU_D 0xf800707f 393 #define MATCH_AMOSWAP_D 0x800302f 394 #define MASK_AMOSWAP_D 0xf800707f 395 #define MATCH_LR_D 0x1000302f 396 #define MASK_LR_D 0xf9f0707f 397 #define MATCH_SC_D 0x1800302f 398 #define MASK_SC_D 0xf800707f 399 #define MATCH_ECALL 0x73 400 #define MASK_ECALL 0xffffffff 401 #define MATCH_EBREAK 0x100073 402 #define MASK_EBREAK 0xffffffff 403 #define MATCH_URET 0x200073 404 #define MASK_URET 0xffffffff 405 #define MATCH_SRET 0x10200073 406 #define MASK_SRET 0xffffffff 407 #define MATCH_MRET 0x30200073 408 #define MASK_MRET 0xffffffff 409 #define MATCH_DRET 0x7b200073 410 #define MASK_DRET 0xffffffff 411 #define MATCH_SFENCE_VMA 0x12000073 412 #define MASK_SFENCE_VMA 0xfe007fff 413 #define MATCH_WFI 0x10500073 414 #define MASK_WFI 0xffffffff 415 #define MATCH_CSRRW 0x1073 416 #define MASK_CSRRW 0x707f 417 #define MATCH_CSRRS 0x2073 418 #define MASK_CSRRS 0x707f 419 #define MATCH_CSRRC 0x3073 420 #define MASK_CSRRC 0x707f 421 #define MATCH_CSRRWI 0x5073 422 #define MASK_CSRRWI 0x707f 423 #define MATCH_CSRRSI 0x6073 424 #define MASK_CSRRSI 0x707f 425 #define MATCH_CSRRCI 0x7073 426 #define MASK_CSRRCI 0x707f 427 #define MATCH_FADD_S 0x53 428 #define MASK_FADD_S 0xfe00007f 429 #define MATCH_FSUB_S 0x8000053 430 #define MASK_FSUB_S 0xfe00007f 431 #define MATCH_FMUL_S 0x10000053 432 #define MASK_FMUL_S 0xfe00007f 433 #define MATCH_FDIV_S 0x18000053 434 #define MASK_FDIV_S 0xfe00007f 435 #define MATCH_FSGNJ_S 0x20000053 436 #define MASK_FSGNJ_S 0xfe00707f 437 #define MATCH_FSGNJN_S 0x20001053 438 #define MASK_FSGNJN_S 0xfe00707f 439 #define MATCH_FSGNJX_S 0x20002053 440 #define MASK_FSGNJX_S 0xfe00707f 441 #define MATCH_FMIN_S 0x28000053 442 #define MASK_FMIN_S 0xfe00707f 443 #define MATCH_FMAX_S 0x28001053 444 #define MASK_FMAX_S 0xfe00707f 445 #define MATCH_FSQRT_S 0x58000053 446 #define MASK_FSQRT_S 0xfff0007f 447 #define MATCH_FADD_D 0x2000053 448 #define MASK_FADD_D 0xfe00007f 449 #define MATCH_FSUB_D 0xa000053 450 #define MASK_FSUB_D 0xfe00007f 451 #define MATCH_FMUL_D 0x12000053 452 #define MASK_FMUL_D 0xfe00007f 453 #define MATCH_FDIV_D 0x1a000053 454 #define MASK_FDIV_D 0xfe00007f 455 #define MATCH_FSGNJ_D 0x22000053 456 #define MASK_FSGNJ_D 0xfe00707f 457 #define MATCH_FSGNJN_D 0x22001053 458 #define MASK_FSGNJN_D 0xfe00707f 459 #define MATCH_FSGNJX_D 0x22002053 460 #define MASK_FSGNJX_D 0xfe00707f 461 #define MATCH_FMIN_D 0x2a000053 462 #define MASK_FMIN_D 0xfe00707f 463 #define MATCH_FMAX_D 0x2a001053 464 #define MASK_FMAX_D 0xfe00707f 465 #define MATCH_FCVT_S_D 0x40100053 466 #define MASK_FCVT_S_D 0xfff0007f 467 #define MATCH_FCVT_D_S 0x42000053 468 #define MASK_FCVT_D_S 0xfff0007f 469 #define MATCH_FSQRT_D 0x5a000053 470 #define MASK_FSQRT_D 0xfff0007f 471 #define MATCH_FADD_Q 0x6000053 472 #define MASK_FADD_Q 0xfe00007f 473 #define MATCH_FSUB_Q 0xe000053 474 #define MASK_FSUB_Q 0xfe00007f 475 #define MATCH_FMUL_Q 0x16000053 476 #define MASK_FMUL_Q 0xfe00007f 477 #define MATCH_FDIV_Q 0x1e000053 478 #define MASK_FDIV_Q 0xfe00007f 479 #define MATCH_FSGNJ_Q 0x26000053 480 #define MASK_FSGNJ_Q 0xfe00707f 481 #define MATCH_FSGNJN_Q 0x26001053 482 #define MASK_FSGNJN_Q 0xfe00707f 483 #define MATCH_FSGNJX_Q 0x26002053 484 #define MASK_FSGNJX_Q 0xfe00707f 485 #define MATCH_FMIN_Q 0x2e000053 486 #define MASK_FMIN_Q 0xfe00707f 487 #define MATCH_FMAX_Q 0x2e001053 488 #define MASK_FMAX_Q 0xfe00707f 489 #define MATCH_FCVT_S_Q 0x40300053 490 #define MASK_FCVT_S_Q 0xfff0007f 491 #define MATCH_FCVT_Q_S 0x46000053 492 #define MASK_FCVT_Q_S 0xfff0007f 493 #define MATCH_FCVT_D_Q 0x42300053 494 #define MASK_FCVT_D_Q 0xfff0007f 495 #define MATCH_FCVT_Q_D 0x46100053 496 #define MASK_FCVT_Q_D 0xfff0007f 497 #define MATCH_FSQRT_Q 0x5e000053 498 #define MASK_FSQRT_Q 0xfff0007f 499 #define MATCH_FLE_S 0xa0000053 500 #define MASK_FLE_S 0xfe00707f 501 #define MATCH_FLT_S 0xa0001053 502 #define MASK_FLT_S 0xfe00707f 503 #define MATCH_FEQ_S 0xa0002053 504 #define MASK_FEQ_S 0xfe00707f 505 #define MATCH_FLE_D 0xa2000053 506 #define MASK_FLE_D 0xfe00707f 507 #define MATCH_FLT_D 0xa2001053 508 #define MASK_FLT_D 0xfe00707f 509 #define MATCH_FEQ_D 0xa2002053 510 #define MASK_FEQ_D 0xfe00707f 511 #define MATCH_FLE_Q 0xa6000053 512 #define MASK_FLE_Q 0xfe00707f 513 #define MATCH_FLT_Q 0xa6001053 514 #define MASK_FLT_Q 0xfe00707f 515 #define MATCH_FEQ_Q 0xa6002053 516 #define MASK_FEQ_Q 0xfe00707f 517 #define MATCH_FCVT_W_S 0xc0000053 518 #define MASK_FCVT_W_S 0xfff0007f 519 #define MATCH_FCVT_WU_S 0xc0100053 520 #define MASK_FCVT_WU_S 0xfff0007f 521 #define MATCH_FCVT_L_S 0xc0200053 522 #define MASK_FCVT_L_S 0xfff0007f 523 #define MATCH_FCVT_LU_S 0xc0300053 524 #define MASK_FCVT_LU_S 0xfff0007f 525 #define MATCH_FMV_X_W 0xe0000053 526 #define MASK_FMV_X_W 0xfff0707f 527 #define MATCH_FCLASS_S 0xe0001053 528 #define MASK_FCLASS_S 0xfff0707f 529 #define MATCH_FCVT_W_D 0xc2000053 530 #define MASK_FCVT_W_D 0xfff0007f 531 #define MATCH_FCVT_WU_D 0xc2100053 532 #define MASK_FCVT_WU_D 0xfff0007f 533 #define MATCH_FCVT_L_D 0xc2200053 534 #define MASK_FCVT_L_D 0xfff0007f 535 #define MATCH_FCVT_LU_D 0xc2300053 536 #define MASK_FCVT_LU_D 0xfff0007f 537 #define MATCH_FMV_X_D 0xe2000053 538 #define MASK_FMV_X_D 0xfff0707f 539 #define MATCH_FCLASS_D 0xe2001053 540 #define MASK_FCLASS_D 0xfff0707f 541 #define MATCH_FCVT_W_Q 0xc6000053 542 #define MASK_FCVT_W_Q 0xfff0007f 543 #define MATCH_FCVT_WU_Q 0xc6100053 544 #define MASK_FCVT_WU_Q 0xfff0007f 545 #define MATCH_FCVT_L_Q 0xc6200053 546 #define MASK_FCVT_L_Q 0xfff0007f 547 #define MATCH_FCVT_LU_Q 0xc6300053 548 #define MASK_FCVT_LU_Q 0xfff0007f 549 #define MATCH_FMV_X_Q 0xe6000053 550 #define MASK_FMV_X_Q 0xfff0707f 551 #define MATCH_FCLASS_Q 0xe6001053 552 #define MASK_FCLASS_Q 0xfff0707f 553 #define MATCH_FCVT_S_W 0xd0000053 554 #define MASK_FCVT_S_W 0xfff0007f 555 #define MATCH_FCVT_S_WU 0xd0100053 556 #define MASK_FCVT_S_WU 0xfff0007f 557 #define MATCH_FCVT_S_L 0xd0200053 558 #define MASK_FCVT_S_L 0xfff0007f 559 #define MATCH_FCVT_S_LU 0xd0300053 560 #define MASK_FCVT_S_LU 0xfff0007f 561 #define MATCH_FMV_W_X 0xf0000053 562 #define MASK_FMV_W_X 0xfff0707f 563 #define MATCH_FCVT_D_W 0xd2000053 564 #define MASK_FCVT_D_W 0xfff0007f 565 #define MATCH_FCVT_D_WU 0xd2100053 566 #define MASK_FCVT_D_WU 0xfff0007f 567 #define MATCH_FCVT_D_L 0xd2200053 568 #define MASK_FCVT_D_L 0xfff0007f 569 #define MATCH_FCVT_D_LU 0xd2300053 570 #define MASK_FCVT_D_LU 0xfff0007f 571 #define MATCH_FMV_D_X 0xf2000053 572 #define MASK_FMV_D_X 0xfff0707f 573 #define MATCH_FCVT_Q_W 0xd6000053 574 #define MASK_FCVT_Q_W 0xfff0007f 575 #define MATCH_FCVT_Q_WU 0xd6100053 576 #define MASK_FCVT_Q_WU 0xfff0007f 577 #define MATCH_FCVT_Q_L 0xd6200053 578 #define MASK_FCVT_Q_L 0xfff0007f 579 #define MATCH_FCVT_Q_LU 0xd6300053 580 #define MASK_FCVT_Q_LU 0xfff0007f 581 #define MATCH_FMV_Q_X 0xf6000053 582 #define MASK_FMV_Q_X 0xfff0707f 583 #define MATCH_FLW 0x2007 584 #define MASK_FLW 0x707f 585 #define MATCH_FLD 0x3007 586 #define MASK_FLD 0x707f 587 #define MATCH_FLQ 0x4007 588 #define MASK_FLQ 0x707f 589 #define MATCH_FSW 0x2027 590 #define MASK_FSW 0x707f 591 #define MATCH_FSD 0x3027 592 #define MASK_FSD 0x707f 593 #define MATCH_FSQ 0x4027 594 #define MASK_FSQ 0x707f 595 #define MATCH_FMADD_S 0x43 596 #define MASK_FMADD_S 0x600007f 597 #define MATCH_FMSUB_S 0x47 598 #define MASK_FMSUB_S 0x600007f 599 #define MATCH_FNMSUB_S 0x4b 600 #define MASK_FNMSUB_S 0x600007f 601 #define MATCH_FNMADD_S 0x4f 602 #define MASK_FNMADD_S 0x600007f 603 #define MATCH_FMADD_D 0x2000043 604 #define MASK_FMADD_D 0x600007f 605 #define MATCH_FMSUB_D 0x2000047 606 #define MASK_FMSUB_D 0x600007f 607 #define MATCH_FNMSUB_D 0x200004b 608 #define MASK_FNMSUB_D 0x600007f 609 #define MATCH_FNMADD_D 0x200004f 610 #define MASK_FNMADD_D 0x600007f 611 #define MATCH_FMADD_Q 0x6000043 612 #define MASK_FMADD_Q 0x600007f 613 #define MATCH_FMSUB_Q 0x6000047 614 #define MASK_FMSUB_Q 0x600007f 615 #define MATCH_FNMSUB_Q 0x600004b 616 #define MASK_FNMSUB_Q 0x600007f 617 #define MATCH_FNMADD_Q 0x600004f 618 #define MASK_FNMADD_Q 0x600007f 619 #define MATCH_C_NOP 0x1 620 #define MASK_C_NOP 0xffff 621 #define MATCH_C_ADDI16SP 0x6101 622 #define MASK_C_ADDI16SP 0xef83 623 #define MATCH_C_JR 0x8002 624 #define MASK_C_JR 0xf07f 625 #define MATCH_C_JALR 0x9002 626 #define MASK_C_JALR 0xf07f 627 #define MATCH_C_EBREAK 0x9002 628 #define MASK_C_EBREAK 0xffff 629 #define MATCH_C_LD 0x6000 630 #define MASK_C_LD 0xe003 631 #define MATCH_C_SD 0xe000 632 #define MASK_C_SD 0xe003 633 #define MATCH_C_ADDIW 0x2001 634 #define MASK_C_ADDIW 0xe003 635 #define MATCH_C_LDSP 0x6002 636 #define MASK_C_LDSP 0xe003 637 #define MATCH_C_SDSP 0xe002 638 #define MASK_C_SDSP 0xe003 639 #define MATCH_C_ADDI4SPN 0x0 640 #define MASK_C_ADDI4SPN 0xe003 641 #define MATCH_C_FLD 0x2000 642 #define MASK_C_FLD 0xe003 643 #define MATCH_C_LW 0x4000 644 #define MASK_C_LW 0xe003 645 #define MATCH_C_FLW 0x6000 646 #define MASK_C_FLW 0xe003 647 #define MATCH_C_FSD 0xa000 648 #define MASK_C_FSD 0xe003 649 #define MATCH_C_SW 0xc000 650 #define MASK_C_SW 0xe003 651 #define MATCH_C_FSW 0xe000 652 #define MASK_C_FSW 0xe003 653 #define MATCH_C_ADDI 0x1 654 #define MASK_C_ADDI 0xe003 655 #define MATCH_C_JAL 0x2001 656 #define MASK_C_JAL 0xe003 657 #define MATCH_C_LI 0x4001 658 #define MASK_C_LI 0xe003 659 #define MATCH_C_LUI 0x6001 660 #define MASK_C_LUI 0xe003 661 #define MATCH_C_SRLI 0x8001 662 #define MASK_C_SRLI 0xec03 663 #define MATCH_C_SRAI 0x8401 664 #define MASK_C_SRAI 0xec03 665 #define MATCH_C_ANDI 0x8801 666 #define MASK_C_ANDI 0xec03 667 #define MATCH_C_SUB 0x8c01 668 #define MASK_C_SUB 0xfc63 669 #define MATCH_C_XOR 0x8c21 670 #define MASK_C_XOR 0xfc63 671 #define MATCH_C_OR 0x8c41 672 #define MASK_C_OR 0xfc63 673 #define MATCH_C_AND 0x8c61 674 #define MASK_C_AND 0xfc63 675 #define MATCH_C_SUBW 0x9c01 676 #define MASK_C_SUBW 0xfc63 677 #define MATCH_C_ADDW 0x9c21 678 #define MASK_C_ADDW 0xfc63 679 #define MATCH_C_J 0xa001 680 #define MASK_C_J 0xe003 681 #define MATCH_C_BEQZ 0xc001 682 #define MASK_C_BEQZ 0xe003 683 #define MATCH_C_BNEZ 0xe001 684 #define MASK_C_BNEZ 0xe003 685 #define MATCH_C_SLLI 0x2 686 #define MASK_C_SLLI 0xe003 687 #define MATCH_C_FLDSP 0x2002 688 #define MASK_C_FLDSP 0xe003 689 #define MATCH_C_LWSP 0x4002 690 #define MASK_C_LWSP 0xe003 691 #define MATCH_C_FLWSP 0x6002 692 #define MASK_C_FLWSP 0xe003 693 #define MATCH_C_MV 0x8002 694 #define MASK_C_MV 0xf003 695 #define MATCH_C_ADD 0x9002 696 #define MASK_C_ADD 0xf003 697 #define MATCH_C_FSDSP 0xa002 698 #define MASK_C_FSDSP 0xe003 699 #define MATCH_C_SWSP 0xc002 700 #define MASK_C_SWSP 0xe003 701 #define MATCH_C_FSWSP 0xe002 702 #define MASK_C_FSWSP 0xe003 703 #define MATCH_CUSTOM0 0xb 704 #define MASK_CUSTOM0 0x707f 705 #define MATCH_CUSTOM0_RS1 0x200b 706 #define MASK_CUSTOM0_RS1 0x707f 707 #define MATCH_CUSTOM0_RS1_RS2 0x300b 708 #define MASK_CUSTOM0_RS1_RS2 0x707f 709 #define MATCH_CUSTOM0_RD 0x400b 710 #define MASK_CUSTOM0_RD 0x707f 711 #define MATCH_CUSTOM0_RD_RS1 0x600b 712 #define MASK_CUSTOM0_RD_RS1 0x707f 713 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 714 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f 715 #define MATCH_CUSTOM1 0x2b 716 #define MASK_CUSTOM1 0x707f 717 #define MATCH_CUSTOM1_RS1 0x202b 718 #define MASK_CUSTOM1_RS1 0x707f 719 #define MATCH_CUSTOM1_RS1_RS2 0x302b 720 #define MASK_CUSTOM1_RS1_RS2 0x707f 721 #define MATCH_CUSTOM1_RD 0x402b 722 #define MASK_CUSTOM1_RD 0x707f 723 #define MATCH_CUSTOM1_RD_RS1 0x602b 724 #define MASK_CUSTOM1_RD_RS1 0x707f 725 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 726 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f 727 #define MATCH_CUSTOM2 0x5b 728 #define MASK_CUSTOM2 0x707f 729 #define MATCH_CUSTOM2_RS1 0x205b 730 #define MASK_CUSTOM2_RS1 0x707f 731 #define MATCH_CUSTOM2_RS1_RS2 0x305b 732 #define MASK_CUSTOM2_RS1_RS2 0x707f 733 #define MATCH_CUSTOM2_RD 0x405b 734 #define MASK_CUSTOM2_RD 0x707f 735 #define MATCH_CUSTOM2_RD_RS1 0x605b 736 #define MASK_CUSTOM2_RD_RS1 0x707f 737 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 738 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f 739 #define MATCH_CUSTOM3 0x7b 740 #define MASK_CUSTOM3 0x707f 741 #define MATCH_CUSTOM3_RS1 0x207b 742 #define MASK_CUSTOM3_RS1 0x707f 743 #define MATCH_CUSTOM3_RS1_RS2 0x307b 744 #define MASK_CUSTOM3_RS1_RS2 0x707f 745 #define MATCH_CUSTOM3_RD 0x407b 746 #define MASK_CUSTOM3_RD 0x707f 747 #define MATCH_CUSTOM3_RD_RS1 0x607b 748 #define MASK_CUSTOM3_RD_RS1 0x707f 749 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 750 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f 751 #define CSR_FFLAGS 0x1 752 #define CSR_FRM 0x2 753 #define CSR_FCSR 0x3 754 #define CSR_CYCLE 0xc00 755 #define CSR_TIME 0xc01 756 #define CSR_INSTRET 0xc02 757 #define CSR_HPMCOUNTER3 0xc03 758 #define CSR_HPMCOUNTER4 0xc04 759 #define CSR_HPMCOUNTER5 0xc05 760 #define CSR_HPMCOUNTER6 0xc06 761 #define CSR_HPMCOUNTER7 0xc07 762 #define CSR_HPMCOUNTER8 0xc08 763 #define CSR_HPMCOUNTER9 0xc09 764 #define CSR_HPMCOUNTER10 0xc0a 765 #define CSR_HPMCOUNTER11 0xc0b 766 #define CSR_HPMCOUNTER12 0xc0c 767 #define CSR_HPMCOUNTER13 0xc0d 768 #define CSR_HPMCOUNTER14 0xc0e 769 #define CSR_HPMCOUNTER15 0xc0f 770 #define CSR_HPMCOUNTER16 0xc10 771 #define CSR_HPMCOUNTER17 0xc11 772 #define CSR_HPMCOUNTER18 0xc12 773 #define CSR_HPMCOUNTER19 0xc13 774 #define CSR_HPMCOUNTER20 0xc14 775 #define CSR_HPMCOUNTER21 0xc15 776 #define CSR_HPMCOUNTER22 0xc16 777 #define CSR_HPMCOUNTER23 0xc17 778 #define CSR_HPMCOUNTER24 0xc18 779 #define CSR_HPMCOUNTER25 0xc19 780 #define CSR_HPMCOUNTER26 0xc1a 781 #define CSR_HPMCOUNTER27 0xc1b 782 #define CSR_HPMCOUNTER28 0xc1c 783 #define CSR_HPMCOUNTER29 0xc1d 784 #define CSR_HPMCOUNTER30 0xc1e 785 #define CSR_HPMCOUNTER31 0xc1f 786 #define CSR_SSTATUS 0x100 787 #define CSR_SIE 0x104 788 #define CSR_STVEC 0x105 789 #define CSR_SCOUNTEREN 0x106 790 #define CSR_SSCRATCH 0x140 791 #define CSR_SEPC 0x141 792 #define CSR_SCAUSE 0x142 793 #define CSR_STVAL 0x143 794 #define CSR_SIP 0x144 795 #define CSR_SATP 0x180 796 #define CSR_MSTATUS 0x300 797 #define CSR_MISA 0x301 798 #define CSR_MEDELEG 0x302 799 #define CSR_MIDELEG 0x303 800 #define CSR_MIE 0x304 801 #define CSR_MTVEC 0x305 802 #define CSR_MCOUNTEREN 0x306 803 #define CSR_MENVCFG 0x30a 804 #define CSR_MENVCFGH 0x31a 805 #define CSR_MSCRATCH 0x340 806 #define CSR_MEPC 0x341 807 #define CSR_MCAUSE 0x342 808 #define CSR_MTVAL 0x343 809 #define CSR_MIP 0x344 810 #define CSR_PMPCFG0 0x3a0 811 #define CSR_PMPCFG1 0x3a1 812 #define CSR_PMPCFG2 0x3a2 813 #define CSR_PMPCFG3 0x3a3 814 #define CSR_PMPADDR0 0x3b0 815 #define CSR_PMPADDR1 0x3b1 816 #define CSR_PMPADDR2 0x3b2 817 #define CSR_PMPADDR3 0x3b3 818 #define CSR_PMPADDR4 0x3b4 819 #define CSR_PMPADDR5 0x3b5 820 #define CSR_PMPADDR6 0x3b6 821 #define CSR_PMPADDR7 0x3b7 822 #define CSR_PMPADDR8 0x3b8 823 #define CSR_PMPADDR9 0x3b9 824 #define CSR_PMPADDR10 0x3ba 825 #define CSR_PMPADDR11 0x3bb 826 #define CSR_PMPADDR12 0x3bc 827 #define CSR_PMPADDR13 0x3bd 828 #define CSR_PMPADDR14 0x3be 829 #define CSR_PMPADDR15 0x3bf 830 #define CSR_TSELECT 0x7a0 831 #define CSR_TDATA1 0x7a1 832 #define CSR_TDATA2 0x7a2 833 #define CSR_TDATA3 0x7a3 834 #define CSR_DCSR 0x7b0 835 #define CSR_DPC 0x7b1 836 #define CSR_DSCRATCH 0x7b2 837 #define CSR_MCYCLE 0xb00 838 #define CSR_MINSTRET 0xb02 839 #define CSR_MHPMCOUNTER3 0xb03 840 #define CSR_MHPMCOUNTER4 0xb04 841 #define CSR_MHPMCOUNTER5 0xb05 842 #define CSR_MHPMCOUNTER6 0xb06 843 #define CSR_MHPMCOUNTER7 0xb07 844 #define CSR_MHPMCOUNTER8 0xb08 845 #define CSR_MHPMCOUNTER9 0xb09 846 #define CSR_MHPMCOUNTER10 0xb0a 847 #define CSR_MHPMCOUNTER11 0xb0b 848 #define CSR_MHPMCOUNTER12 0xb0c 849 #define CSR_MHPMCOUNTER13 0xb0d 850 #define CSR_MHPMCOUNTER14 0xb0e 851 #define CSR_MHPMCOUNTER15 0xb0f 852 #define CSR_MHPMCOUNTER16 0xb10 853 #define CSR_MHPMCOUNTER17 0xb11 854 #define CSR_MHPMCOUNTER18 0xb12 855 #define CSR_MHPMCOUNTER19 0xb13 856 #define CSR_MHPMCOUNTER20 0xb14 857 #define CSR_MHPMCOUNTER21 0xb15 858 #define CSR_MHPMCOUNTER22 0xb16 859 #define CSR_MHPMCOUNTER23 0xb17 860 #define CSR_MHPMCOUNTER24 0xb18 861 #define CSR_MHPMCOUNTER25 0xb19 862 #define CSR_MHPMCOUNTER26 0xb1a 863 #define CSR_MHPMCOUNTER27 0xb1b 864 #define CSR_MHPMCOUNTER28 0xb1c 865 #define CSR_MHPMCOUNTER29 0xb1d 866 #define CSR_MHPMCOUNTER30 0xb1e 867 #define CSR_MHPMCOUNTER31 0xb1f 868 #define CSR_MHPMEVENT3 0x323 869 #define CSR_MHPMEVENT4 0x324 870 #define CSR_MHPMEVENT5 0x325 871 #define CSR_MHPMEVENT6 0x326 872 #define CSR_MHPMEVENT7 0x327 873 #define CSR_MHPMEVENT8 0x328 874 #define CSR_MHPMEVENT9 0x329 875 #define CSR_MHPMEVENT10 0x32a 876 #define CSR_MHPMEVENT11 0x32b 877 #define CSR_MHPMEVENT12 0x32c 878 #define CSR_MHPMEVENT13 0x32d 879 #define CSR_MHPMEVENT14 0x32e 880 #define CSR_MHPMEVENT15 0x32f 881 #define CSR_MHPMEVENT16 0x330 882 #define CSR_MHPMEVENT17 0x331 883 #define CSR_MHPMEVENT18 0x332 884 #define CSR_MHPMEVENT19 0x333 885 #define CSR_MHPMEVENT20 0x334 886 #define CSR_MHPMEVENT21 0x335 887 #define CSR_MHPMEVENT22 0x336 888 #define CSR_MHPMEVENT23 0x337 889 #define CSR_MHPMEVENT24 0x338 890 #define CSR_MHPMEVENT25 0x339 891 #define CSR_MHPMEVENT26 0x33a 892 #define CSR_MHPMEVENT27 0x33b 893 #define CSR_MHPMEVENT28 0x33c 894 #define CSR_MHPMEVENT29 0x33d 895 #define CSR_MHPMEVENT30 0x33e 896 #define CSR_MHPMEVENT31 0x33f 897 #define CSR_MVENDORID 0xf11 898 #define CSR_MARCHID 0xf12 899 #define CSR_MIMPID 0xf13 900 #define CSR_MHARTID 0xf14 901 #define CSR_CYCLEH 0xc80 902 #define CSR_TIMEH 0xc81 903 #define CSR_INSTRETH 0xc82 904 #define CSR_HPMCOUNTER3H 0xc83 905 #define CSR_HPMCOUNTER4H 0xc84 906 #define CSR_HPMCOUNTER5H 0xc85 907 #define CSR_HPMCOUNTER6H 0xc86 908 #define CSR_HPMCOUNTER7H 0xc87 909 #define CSR_HPMCOUNTER8H 0xc88 910 #define CSR_HPMCOUNTER9H 0xc89 911 #define CSR_HPMCOUNTER10H 0xc8a 912 #define CSR_HPMCOUNTER11H 0xc8b 913 #define CSR_HPMCOUNTER12H 0xc8c 914 #define CSR_HPMCOUNTER13H 0xc8d 915 #define CSR_HPMCOUNTER14H 0xc8e 916 #define CSR_HPMCOUNTER15H 0xc8f 917 #define CSR_HPMCOUNTER16H 0xc90 918 #define CSR_HPMCOUNTER17H 0xc91 919 #define CSR_HPMCOUNTER18H 0xc92 920 #define CSR_HPMCOUNTER19H 0xc93 921 #define CSR_HPMCOUNTER20H 0xc94 922 #define CSR_HPMCOUNTER21H 0xc95 923 #define CSR_HPMCOUNTER22H 0xc96 924 #define CSR_HPMCOUNTER23H 0xc97 925 #define CSR_HPMCOUNTER24H 0xc98 926 #define CSR_HPMCOUNTER25H 0xc99 927 #define CSR_HPMCOUNTER26H 0xc9a 928 #define CSR_HPMCOUNTER27H 0xc9b 929 #define CSR_HPMCOUNTER28H 0xc9c 930 #define CSR_HPMCOUNTER29H 0xc9d 931 #define CSR_HPMCOUNTER30H 0xc9e 932 #define CSR_HPMCOUNTER31H 0xc9f 933 #define CSR_MCYCLEH 0xb80 934 #define CSR_MINSTRETH 0xb82 935 #define CSR_MHPMCOUNTER3H 0xb83 936 #define CSR_MHPMCOUNTER4H 0xb84 937 #define CSR_MHPMCOUNTER5H 0xb85 938 #define CSR_MHPMCOUNTER6H 0xb86 939 #define CSR_MHPMCOUNTER7H 0xb87 940 #define CSR_MHPMCOUNTER8H 0xb88 941 #define CSR_MHPMCOUNTER9H 0xb89 942 #define CSR_MHPMCOUNTER10H 0xb8a 943 #define CSR_MHPMCOUNTER11H 0xb8b 944 #define CSR_MHPMCOUNTER12H 0xb8c 945 #define CSR_MHPMCOUNTER13H 0xb8d 946 #define CSR_MHPMCOUNTER14H 0xb8e 947 #define CSR_MHPMCOUNTER15H 0xb8f 948 #define CSR_MHPMCOUNTER16H 0xb90 949 #define CSR_MHPMCOUNTER17H 0xb91 950 #define CSR_MHPMCOUNTER18H 0xb92 951 #define CSR_MHPMCOUNTER19H 0xb93 952 #define CSR_MHPMCOUNTER20H 0xb94 953 #define CSR_MHPMCOUNTER21H 0xb95 954 #define CSR_MHPMCOUNTER22H 0xb96 955 #define CSR_MHPMCOUNTER23H 0xb97 956 #define CSR_MHPMCOUNTER24H 0xb98 957 #define CSR_MHPMCOUNTER25H 0xb99 958 #define CSR_MHPMCOUNTER26H 0xb9a 959 #define CSR_MHPMCOUNTER27H 0xb9b 960 #define CSR_MHPMCOUNTER28H 0xb9c 961 #define CSR_MHPMCOUNTER29H 0xb9d 962 #define CSR_MHPMCOUNTER30H 0xb9e 963 #define CSR_MHPMCOUNTER31H 0xb9f 964 #define CAUSE_MISALIGNED_FETCH 0x0 965 #define CAUSE_FETCH_ACCESS 0x1 966 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 967 #define CAUSE_BREAKPOINT 0x3 968 #define CAUSE_MISALIGNED_LOAD 0x4 969 #define CAUSE_LOAD_ACCESS 0x5 970 #define CAUSE_MISALIGNED_STORE 0x6 971 #define CAUSE_STORE_ACCESS 0x7 972 #define CAUSE_USER_ECALL 0x8 973 #define CAUSE_SUPERVISOR_ECALL 0x9 974 #define CAUSE_HYPERVISOR_ECALL 0xa 975 #define CAUSE_MACHINE_ECALL 0xb 976 #define CAUSE_FETCH_PAGE_FAULT 0xc 977 #define CAUSE_LOAD_PAGE_FAULT 0xd 978 #define CAUSE_STORE_PAGE_FAULT 0xf 979 #endif 980 #ifdef DECLARE_INSN 981 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 982 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 983 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 984 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 985 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 986 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 987 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 988 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 989 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 990 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 991 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 992 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 993 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 994 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 995 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 996 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 997 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 998 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 999 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 1000 DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 1001 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 1002 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 1003 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 1004 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 1005 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 1006 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 1007 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 1008 DECLARE_INSN(or, MATCH_OR, MASK_OR) 1009 DECLARE_INSN(and, MATCH_AND, MASK_AND) 1010 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 1011 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 1012 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 1013 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 1014 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 1015 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 1016 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 1017 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 1018 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 1019 DECLARE_INSN(lb, MATCH_LB, MASK_LB) 1020 DECLARE_INSN(lh, MATCH_LH, MASK_LH) 1021 DECLARE_INSN(lw, MATCH_LW, MASK_LW) 1022 DECLARE_INSN(ld, MATCH_LD, MASK_LD) 1023 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 1024 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 1025 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 1026 DECLARE_INSN(sb, MATCH_SB, MASK_SB) 1027 DECLARE_INSN(sh, MATCH_SH, MASK_SH) 1028 DECLARE_INSN(sw, MATCH_SW, MASK_SW) 1029 DECLARE_INSN(sd, MATCH_SD, MASK_SD) 1030 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 1031 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 1032 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 1033 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 1034 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 1035 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 1036 DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 1037 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 1038 DECLARE_INSN(rem, MATCH_REM, MASK_REM) 1039 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 1040 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 1041 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 1042 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 1043 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 1044 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 1045 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 1046 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 1047 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 1048 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 1049 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 1050 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 1051 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 1052 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 1053 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 1054 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 1055 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 1056 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 1057 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 1058 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 1059 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 1060 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 1061 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 1062 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 1063 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 1064 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 1065 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 1066 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 1067 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 1068 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 1069 DECLARE_INSN(uret, MATCH_URET, MASK_URET) 1070 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 1071 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 1072 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 1073 DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) 1074 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 1075 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 1076 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 1077 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 1078 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 1079 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 1080 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 1081 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 1082 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 1083 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 1084 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 1085 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 1086 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 1087 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 1088 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 1089 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 1090 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 1091 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 1092 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 1093 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 1094 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 1095 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 1096 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 1097 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 1098 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 1099 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 1100 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 1101 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 1102 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 1103 DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) 1104 DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) 1105 DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) 1106 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) 1107 DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) 1108 DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) 1109 DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) 1110 DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) 1111 DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) 1112 DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) 1113 DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) 1114 DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) 1115 DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) 1116 DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) 1117 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 1118 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 1119 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 1120 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 1121 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 1122 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 1123 DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) 1124 DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) 1125 DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) 1126 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 1127 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 1128 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 1129 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 1130 DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) 1131 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 1132 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 1133 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 1134 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 1135 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 1136 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 1137 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 1138 DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) 1139 DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) 1140 DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) 1141 DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) 1142 DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) 1143 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) 1144 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 1145 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 1146 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 1147 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 1148 DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) 1149 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 1150 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 1151 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 1152 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 1153 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 1154 DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) 1155 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) 1156 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) 1157 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) 1158 DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) 1159 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 1160 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 1161 DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) 1162 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 1163 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 1164 DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) 1165 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 1166 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 1167 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 1168 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 1169 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 1170 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 1171 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 1172 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 1173 DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) 1174 DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) 1175 DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) 1176 DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) 1177 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 1178 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 1179 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 1180 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 1181 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 1182 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 1183 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 1184 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 1185 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 1186 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 1187 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 1188 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 1189 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 1190 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 1191 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 1192 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 1193 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 1194 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 1195 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 1196 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 1197 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 1198 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 1199 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 1200 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 1201 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 1202 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 1203 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 1204 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 1205 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 1206 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 1207 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 1208 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 1209 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 1210 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 1211 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 1212 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 1213 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 1214 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 1215 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 1216 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 1217 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 1218 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 1219 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 1220 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 1221 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 1222 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 1223 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 1224 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) 1225 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 1226 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 1227 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 1228 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 1229 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 1230 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) 1231 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 1232 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 1233 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 1234 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 1235 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 1236 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) 1237 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 1238 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 1239 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 1240 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 1241 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 1242 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) 1243 #endif 1244 #ifdef DECLARE_CSR 1245 DECLARE_CSR(fflags, CSR_FFLAGS) 1246 DECLARE_CSR(frm, CSR_FRM) 1247 DECLARE_CSR(fcsr, CSR_FCSR) 1248 DECLARE_CSR(cycle, CSR_CYCLE) 1249 DECLARE_CSR(time, CSR_TIME) 1250 DECLARE_CSR(instret, CSR_INSTRET) 1251 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) 1252 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) 1253 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) 1254 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) 1255 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) 1256 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) 1257 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) 1258 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) 1259 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) 1260 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) 1261 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) 1262 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) 1263 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) 1264 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) 1265 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) 1266 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) 1267 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) 1268 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) 1269 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) 1270 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) 1271 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) 1272 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) 1273 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) 1274 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) 1275 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) 1276 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) 1277 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) 1278 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) 1279 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) 1280 DECLARE_CSR(sstatus, CSR_SSTATUS) 1281 DECLARE_CSR(sie, CSR_SIE) 1282 DECLARE_CSR(stvec, CSR_STVEC) 1283 DECLARE_CSR(scounteren, CSR_SCOUNTEREN) 1284 DECLARE_CSR(sscratch, CSR_SSCRATCH) 1285 DECLARE_CSR(sepc, CSR_SEPC) 1286 DECLARE_CSR(scause, CSR_SCAUSE) 1287 DECLARE_CSR(stval, CSR_STVAL) 1288 DECLARE_CSR(sip, CSR_SIP) 1289 DECLARE_CSR(satp, CSR_SATP) 1290 DECLARE_CSR(mstatus, CSR_MSTATUS) 1291 DECLARE_CSR(misa, CSR_MISA) 1292 DECLARE_CSR(medeleg, CSR_MEDELEG) 1293 DECLARE_CSR(mideleg, CSR_MIDELEG) 1294 DECLARE_CSR(mie, CSR_MIE) 1295 DECLARE_CSR(mtvec, CSR_MTVEC) 1296 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) 1297 DECLARE_CSR(menvcfg, CSR_MENVCFG) 1298 DECLARE_CSR(menvcfgh, CSR_MENVCFGH) 1299 DECLARE_CSR(mscratch, CSR_MSCRATCH) 1300 DECLARE_CSR(mepc, CSR_MEPC) 1301 DECLARE_CSR(mcause, CSR_MCAUSE) 1302 DECLARE_CSR(mtval, CSR_MTVAL) 1303 DECLARE_CSR(mip, CSR_MIP) 1304 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) 1305 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) 1306 DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) 1307 DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) 1308 DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) 1309 DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) 1310 DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) 1311 DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) 1312 DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) 1313 DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) 1314 DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) 1315 DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) 1316 DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) 1317 DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) 1318 DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) 1319 DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) 1320 DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) 1321 DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) 1322 DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) 1323 DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) 1324 DECLARE_CSR(tselect, CSR_TSELECT) 1325 DECLARE_CSR(tdata1, CSR_TDATA1) 1326 DECLARE_CSR(tdata2, CSR_TDATA2) 1327 DECLARE_CSR(tdata3, CSR_TDATA3) 1328 DECLARE_CSR(dcsr, CSR_DCSR) 1329 DECLARE_CSR(dpc, CSR_DPC) 1330 DECLARE_CSR(dscratch, CSR_DSCRATCH) 1331 DECLARE_CSR(mcycle, CSR_MCYCLE) 1332 DECLARE_CSR(minstret, CSR_MINSTRET) 1333 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) 1334 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) 1335 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) 1336 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) 1337 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) 1338 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) 1339 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) 1340 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) 1341 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) 1342 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) 1343 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) 1344 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) 1345 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) 1346 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) 1347 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) 1348 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) 1349 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) 1350 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) 1351 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) 1352 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) 1353 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) 1354 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) 1355 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) 1356 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) 1357 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) 1358 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) 1359 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) 1360 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) 1361 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) 1362 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) 1363 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) 1364 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) 1365 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) 1366 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) 1367 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) 1368 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) 1369 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) 1370 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) 1371 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) 1372 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) 1373 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) 1374 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) 1375 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) 1376 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) 1377 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) 1378 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) 1379 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) 1380 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) 1381 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) 1382 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) 1383 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) 1384 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) 1385 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) 1386 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) 1387 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) 1388 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) 1389 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) 1390 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) 1391 DECLARE_CSR(mvendorid, CSR_MVENDORID) 1392 DECLARE_CSR(marchid, CSR_MARCHID) 1393 DECLARE_CSR(mimpid, CSR_MIMPID) 1394 DECLARE_CSR(mhartid, CSR_MHARTID) 1395 DECLARE_CSR(cycleh, CSR_CYCLEH) 1396 DECLARE_CSR(timeh, CSR_TIMEH) 1397 DECLARE_CSR(instreth, CSR_INSTRETH) 1398 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) 1399 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) 1400 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) 1401 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) 1402 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) 1403 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) 1404 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) 1405 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) 1406 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) 1407 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) 1408 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) 1409 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) 1410 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) 1411 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) 1412 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) 1413 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) 1414 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) 1415 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) 1416 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) 1417 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) 1418 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) 1419 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) 1420 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) 1421 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) 1422 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) 1423 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) 1424 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) 1425 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) 1426 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) 1427 DECLARE_CSR(mcycleh, CSR_MCYCLEH) 1428 DECLARE_CSR(minstreth, CSR_MINSTRETH) 1429 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) 1430 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) 1431 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) 1432 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) 1433 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) 1434 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) 1435 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) 1436 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) 1437 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) 1438 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) 1439 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) 1440 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) 1441 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) 1442 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) 1443 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) 1444 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) 1445 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) 1446 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) 1447 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) 1448 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) 1449 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) 1450 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) 1451 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) 1452 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) 1453 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) 1454 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) 1455 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) 1456 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) 1457 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) 1458 #endif 1459 #ifdef DECLARE_CAUSE 1460 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) 1461 DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) 1462 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) 1463 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) 1464 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) 1465 DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) 1466 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) 1467 DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) 1468 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) 1469 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) 1470 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) 1471 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) 1472 DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) 1473 DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) 1474 DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) 1475 #endif 1476