1 /* 2 * Copyright (c) 2008-2014 Travis Geiselbrecht 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files 6 * (the "Software"), to deal in the Software without restriction, 7 * including without limitation the rights to use, copy, modify, merge, 8 * publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, 10 * subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __ARCH_OPS_H 24 #define __ARCH_OPS_H 25 26 #ifndef ASSEMBLY 27 28 #include <sys/types.h> 29 #include <stddef.h> 30 #include <stdbool.h> 31 #include <compiler.h> 32 33 __BEGIN_CDECLS 34 35 /* fast routines that most arches will implement inline */ 36 static void arch_enable_ints(void); 37 static void arch_disable_ints(void); 38 static bool arch_ints_disabled(void); 39 static bool arch_in_int_handler(void); 40 41 static int atomic_swap(volatile int *ptr, int val); 42 static int atomic_add(volatile int *ptr, int val); 43 static int atomic_and(volatile int *ptr, int val); 44 static int atomic_or(volatile int *ptr, int val); 45 46 static uint32_t arch_cycle_count(void); 47 48 static uint arch_curr_cpu_num(void); 49 50 /* Use to align structures on cache lines to avoid cpu aliasing. */ 51 #define __CPU_ALIGN __ALIGNED(CACHE_LINE) 52 53 #endif // !ASSEMBLY 54 #define ICACHE 1 55 #define DCACHE 2 56 #define UCACHE (ICACHE|DCACHE) 57 #ifndef ASSEMBLY 58 59 void arch_disable_cache(uint flags); 60 void arch_enable_cache(uint flags); 61 62 void arch_clean_cache_range(addr_t start, size_t len); 63 void arch_clean_invalidate_cache_range(addr_t start, size_t len); 64 void arch_invalidate_cache_range(addr_t start, size_t len); 65 void arch_sync_cache_range(addr_t start, size_t len); 66 67 void arch_idle(void); 68 69 /* Zero the specified memory as well as the corresponding tags */ 70 void arch_clear_pages_and_tags(vaddr_t addr, size_t size); 71 72 /** 73 * arch_tagging_enabled - indicate if memory tags can be read and written 74 * 75 * Return: true if tags can be written and read, false if not 76 */ 77 bool arch_tagging_enabled(void); 78 79 /** 80 * arch_bti_supported - indicates if branch target identification is supported. 81 * 82 * Return: true if BTI is supported, false if not 83 */ 84 bool arch_bti_supported(void); 85 86 /** 87 * arch_pac_address_supported - indicates if PAC for addresses is supported. 88 * 89 * Return: true if PAC is supported, false if not 90 */ 91 bool arch_pac_address_supported(void); 92 93 /** 94 * arch_pac_exception_supported - indicates if AUT* & RETA* failures generate faults. 95 * 96 * Return: true if FPAC is supported, false if not 97 */ 98 bool arch_pac_exception_supported(void); 99 100 /** 101 * arch_sve_supported - indicates if Scalable Vector Extension (SVE) is supported. 102 * 103 * Return: true if SVE is supported, false if not 104 */ 105 bool arch_sve_supported(void); 106 107 /* 108 * arch_enable_sve - Enables Scalable Vector Extension (SVE). 109 * 110 * Return: Value of CPACR_EL1 before any change was made. 111 */ 112 uint64_t arch_enable_sve(void); 113 114 /* 115 * arch_disable_sve - Disables Scalable Vector Extension (SVE). 116 * 117 * Return: Value of CPACR_EL1 before any change was made. 118 */ 119 uint64_t arch_disable_sve(void); 120 121 __END_CDECLS 122 123 #endif // !ASSEMBLY 124 125 #include <arch/arch_ops.h> 126 127 #endif 128