1// Based on cmd/internal/obj/ppc64/asm9.go. 2// 3// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4// Portions Copyright © 1995-1997 C H Forsyth ([email protected]) 5// Portions Copyright © 1997-1999 Vita Nuova Limited 6// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7// Portions Copyright © 2004,2006 Bruce Ellis 8// Portions Copyright © 2005-2007 C H Forsyth ([email protected]) 9// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10// Portions Copyright © 2009 The Go Authors. All rights reserved. 11// 12// Permission is hereby granted, free of charge, to any person obtaining a copy 13// of this software and associated documentation files (the "Software"), to deal 14// in the Software without restriction, including without limitation the rights 15// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16// copies of the Software, and to permit persons to whom the Software is 17// furnished to do so, subject to the following conditions: 18// 19// The above copyright notice and this permission notice shall be included in 20// all copies or substantial portions of the Software. 21// 22// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28// THE SOFTWARE. 29 30package s390x 31 32import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "fmt" 36 "log" 37 "math" 38 "sort" 39) 40 41// ctxtz holds state while assembling a single function. 42// Each function gets a fresh ctxtz. 43// This allows for multiple functions to be safely concurrently assembled. 44type ctxtz struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51} 52 53// instruction layout. 54const ( 55 funcAlign = 16 56) 57 58type Optab struct { 59 as obj.As // opcode 60 i uint8 // handler index 61 a1 uint8 // From 62 a2 uint8 // Reg 63 a3 uint8 // RestArgs[0] 64 a4 uint8 // RestArgs[1] 65 a5 uint8 // RestArgs[2] 66 a6 uint8 // To 67} 68 69var optab = []Optab{ 70 // zero-length instructions 71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE}, 72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE}, 73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON}, 74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR}, 75 {i: 0, as: obj.ANOP}, 76 {i: 0, as: obj.ANOP, a1: C_SAUTO}, 77 78 // move register 79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG}, 80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG}, 81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG}, 82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG}, 83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG}, 84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG}, 85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG}, 86 87 // load constant 88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG}, 89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG}, 90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG}, 91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG}, 92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG}, 93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG}, 94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG}, 95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG}, 96 97 // store constant 98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO}, 99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO}, 100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO}, 101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO}, 102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO}, 103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO}, 104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO}, 105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO}, 106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO}, 107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO}, 108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG}, 109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG}, 110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG}, 111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG}, 112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG}, 113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG}, 114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG}, 115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG}, 116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG}, 117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG}, 118 119 // store 120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO}, 121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO}, 122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO}, 123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO}, 124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO}, 125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO}, 126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO}, 127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG}, 128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG}, 129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG}, 130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG}, 131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG}, 132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG}, 133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG}, 134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR}, 135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR}, 136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR}, 137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR}, 138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR}, 139 140 // load 141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG}, 142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG}, 143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG}, 144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG}, 145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG}, 146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG}, 147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG}, 148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG}, 149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG}, 150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG}, 151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG}, 152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG}, 153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG}, 154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG}, 155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG}, 156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG}, 157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG}, 158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG}, 159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG}, 160 161 // interlocked load and op 162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 163 164 // integer arithmetic 165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG}, 166 {i: 2, as: AADD, a1: C_REG, a6: C_REG}, 167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG}, 168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG}, 169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG}, 170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG}, 171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG}, 172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG}, 173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG}, 174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG}, 175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG}, 176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG}, 177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG}, 178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG}, 179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG}, 180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG}, 181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG}, 182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG}, 183 {i: 47, as: ANEG, a6: C_REG}, 184 185 // integer logical 186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG}, 187 {i: 6, as: AAND, a1: C_REG, a6: C_REG}, 188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG}, 189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG}, 190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG}, 191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG}, 192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG}, 193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG}, 194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG}, 195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG}, 196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG}, 197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG}, 198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG}, 199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG}, 200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG}, 201 202 // compare and swap 203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG}, 204 205 // floating point 206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG}, 207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG}, 208 {i: 33, as: AFABS, a6: C_FREG}, 209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG}, 211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG}, 212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG}, 213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG}, 214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO}, 215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG}, 216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR}, 217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG}, 218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG}, 219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG}, 220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG}, 221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG}, 222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG}, 223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG}, 225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON}, 226 227 // load symbol address (plus offset) 228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG}, 229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG}, 230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG}, 231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG}, 232 233 // system call 234 {i: 5, as: ASYSCALL}, 235 {i: 77, as: ASYSCALL, a1: C_SCON}, 236 237 // branch 238 {i: 16, as: ABEQ, a6: C_SBRA}, 239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA}, 240 {i: 11, as: ABR, a6: C_LBRA}, 241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA}, 242 {i: 18, as: ABR, a6: C_REG}, 243 {i: 18, as: ABR, a1: C_REG, a6: C_REG}, 244 {i: 15, as: ABR, a6: C_ZOREG}, 245 {i: 15, as: ABC, a6: C_ZOREG}, 246 247 // compare and branch 248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA}, 254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA}, 255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA}, 256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA}, 258 259 // branch on count 260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA}, 261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA}, 262 263 // move on condition 264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG}, 265 266 // load on condition 267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG}, 268 269 // find leftmost one 270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG}, 271 272 // population count 273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG}, 274 275 // compare 276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG}, 277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON}, 278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG}, 279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON}, 280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG}, 281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG}, 282 283 // test under mask 284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON}, 285 286 // insert program mask 287 {i: 92, as: AIPM, a1: C_REG}, 288 289 // set program mask 290 {i: 76, as: ASPM, a1: C_REG}, 291 292 // 32-bit access registers 293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG}, 294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG}, 295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG}, 296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG}, 297 298 // macros 299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG}, 300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO}, 301 302 // load/store multiple 303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO}, 305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG}, 306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG}, 307 308 // bytes 309 {i: 40, as: ABYTE, a1: C_SCON}, 310 {i: 40, as: AWORD, a1: C_LCON}, 311 {i: 31, as: ADWORD, a1: C_LCON}, 312 {i: 31, as: ADWORD, a1: C_DCON}, 313 314 // fast synchronization 315 {i: 80, as: ASYNC}, 316 317 // store clock 318 {i: 88, as: ASTCK, a6: C_SAUTO}, 319 {i: 88, as: ASTCK, a6: C_SOREG}, 320 321 // storage and storage 322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG}, 323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO}, 324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO}, 325 326 // address 327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG}, 328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG}, 329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG}, 330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG}, 331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG}, 332 333 // undefined (deliberate illegal instruction) 334 {i: 78, as: obj.AUNDEF}, 335 336 // Break point instruction(0x0001 opcode) 337 {i: 73, as: ABRRK}, 338 339 // 2 byte no-operation 340 {i: 66, as: ANOPH}, 341 342 // crypto instructions 343 344 // KM 345 {i: 124, as: AKM, a1: C_REG, a6: C_REG}, 346 347 // KDSA 348 {i: 125, as: AKDSA, a1: C_REG, a6: C_REG}, 349 350 // KMA 351 {i: 126, as: AKMA, a1: C_REG, a2: C_REG, a6: C_REG}, 352 353 // vector instructions 354 355 // VRX store 356 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG}, 357 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO}, 358 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 359 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 360 361 // VRX load 362 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG}, 363 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG}, 364 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 365 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 366 367 // VRV scatter 368 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 369 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 370 371 // VRV gather 372 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 373 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 374 375 // VRS element shift/rotate and load gr to/from vr element 376 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 377 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG}, 378 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG}, 379 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG}, 380 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG}, 381 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG}, 382 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG}, 383 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG}, 384 385 // VRS store multiple 386 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG}, 387 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO}, 388 389 // VRS load multiple 390 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG}, 391 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG}, 392 393 // VRS store with length 394 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG}, 395 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO}, 396 397 // VRS load with length 398 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG}, 399 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG}, 400 401 // VRI-a 402 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG}, 403 {i: 109, as: AVZERO, a6: C_VREG}, 404 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG}, 405 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG}, 406 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG}, 407 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 408 409 // VRI-b generate mask 410 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 411 412 // VRI-c replicate 413 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG}, 414 415 // VRI-d element rotate and insert under mask and 416 // shift left double by byte 417 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 418 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 419 420 // VRI-d fp test data class immediate 421 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 422 423 // VRR-a load reg 424 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG}, 425 426 // VRR-a compare 427 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG}, 428 429 // VRR-b 430 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 431 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 432 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 433 434 // VRR-c 435 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 436 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG}, 437 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG}, 438 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 439 440 // VRR-c shifts 441 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 442 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG}, 443 444 // VRR-d 445 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 446 447 // VRR-e 448 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 449 450 // VRR-f 451 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG}, 452} 453 454var oprange [ALAST & obj.AMask][]Optab 455 456var xcmp [C_NCLASS][C_NCLASS]bool 457 458func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 459 if ctxt.Retpoline { 460 ctxt.Diag("-spectre=ret not supported on s390x") 461 ctxt.Retpoline = false // don't keep printing 462 } 463 464 p := cursym.Func().Text 465 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 466 return 467 } 468 469 if oprange[AORW&obj.AMask] == nil { 470 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 471 } 472 473 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 474 475 buffer := make([]byte, 0) 476 changed := true 477 loop := 0 478 nrelocs0 := len(c.cursym.R) 479 for changed { 480 if loop > 100 { 481 c.ctxt.Diag("stuck in spanz loop") 482 break 483 } 484 changed = false 485 buffer = buffer[:0] 486 for i := range c.cursym.R[nrelocs0:] { 487 c.cursym.R[nrelocs0+i] = obj.Reloc{} 488 } 489 c.cursym.R = c.cursym.R[:nrelocs0] // preserve marker relocations generated by the compiler 490 for p := c.cursym.Func().Text; p != nil; p = p.Link { 491 pc := int64(len(buffer)) 492 if pc != p.Pc { 493 changed = true 494 } 495 p.Pc = pc 496 c.pc = p.Pc 497 c.asmout(p, &buffer) 498 if pc == int64(len(buffer)) { 499 switch p.As { 500 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 501 // ok 502 default: 503 c.ctxt.Diag("zero-width instruction\n%v", p) 504 } 505 } 506 } 507 loop++ 508 } 509 510 c.cursym.Size = int64(len(buffer)) 511 if c.cursym.Size%funcAlign != 0 { 512 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 513 } 514 c.cursym.Grow(c.cursym.Size) 515 copy(c.cursym.P, buffer) 516 517 // Mark nonpreemptible instruction sequences. 518 // We use REGTMP as a scratch register during call injection, 519 // so instruction sequences that use REGTMP are unsafe to 520 // preempt asynchronously. 521 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil) 522} 523 524// Return whether p is an unsafe point. 525func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool { 526 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP { 527 return true 528 } 529 for _, a := range p.RestArgs { 530 if a.Reg == REGTMP { 531 return true 532 } 533 } 534 return p.Mark&USETMP != 0 535} 536 537func isint32(v int64) bool { 538 return int64(int32(v)) == v 539} 540 541func isuint32(v uint64) bool { 542 return uint64(uint32(v)) == v 543} 544 545func (c *ctxtz) aclass(a *obj.Addr) int { 546 switch a.Type { 547 case obj.TYPE_NONE: 548 return C_NONE 549 550 case obj.TYPE_REG: 551 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 552 return C_REG 553 } 554 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 555 return C_FREG 556 } 557 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 558 return C_AREG 559 } 560 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 561 return C_VREG 562 } 563 return C_GOK 564 565 case obj.TYPE_MEM: 566 switch a.Name { 567 case obj.NAME_EXTERN, 568 obj.NAME_STATIC: 569 if a.Sym == nil { 570 // must have a symbol 571 break 572 } 573 c.instoffset = a.Offset 574 if a.Sym.Type == objabi.STLSBSS { 575 if c.ctxt.Flag_shared { 576 return C_TLS_IE // initial exec model 577 } 578 return C_TLS_LE // local exec model 579 } 580 return C_ADDR 581 582 case obj.NAME_GOTREF: 583 return C_GOTADDR 584 585 case obj.NAME_AUTO: 586 if a.Reg == REGSP { 587 // unset base register for better printing, since 588 // a.Offset is still relative to pseudo-SP. 589 a.Reg = obj.REG_NONE 590 } 591 c.instoffset = int64(c.autosize) + a.Offset 592 if c.instoffset >= -BIG && c.instoffset < BIG { 593 return C_SAUTO 594 } 595 return C_LAUTO 596 597 case obj.NAME_PARAM: 598 if a.Reg == REGSP { 599 // unset base register for better printing, since 600 // a.Offset is still relative to pseudo-FP. 601 a.Reg = obj.REG_NONE 602 } 603 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize 604 if c.instoffset >= -BIG && c.instoffset < BIG { 605 return C_SAUTO 606 } 607 return C_LAUTO 608 609 case obj.NAME_NONE: 610 c.instoffset = a.Offset 611 if c.instoffset == 0 { 612 return C_ZOREG 613 } 614 if c.instoffset >= -BIG && c.instoffset < BIG { 615 return C_SOREG 616 } 617 return C_LOREG 618 } 619 620 return C_GOK 621 622 case obj.TYPE_TEXTSIZE: 623 return C_TEXTSIZE 624 625 case obj.TYPE_FCONST: 626 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 627 return C_ZCON 628 } 629 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 630 631 case obj.TYPE_CONST, 632 obj.TYPE_ADDR: 633 switch a.Name { 634 case obj.NAME_NONE: 635 c.instoffset = a.Offset 636 if a.Reg != 0 { 637 if -BIG <= c.instoffset && c.instoffset <= BIG { 638 return C_SACON 639 } 640 if isint32(c.instoffset) { 641 return C_LACON 642 } 643 return C_DACON 644 } 645 646 case obj.NAME_EXTERN, 647 obj.NAME_STATIC: 648 s := a.Sym 649 if s == nil { 650 return C_GOK 651 } 652 c.instoffset = a.Offset 653 654 return C_SYMADDR 655 656 case obj.NAME_AUTO: 657 if a.Reg == REGSP { 658 // unset base register for better printing, since 659 // a.Offset is still relative to pseudo-SP. 660 a.Reg = obj.REG_NONE 661 } 662 c.instoffset = int64(c.autosize) + a.Offset 663 if c.instoffset >= -BIG && c.instoffset < BIG { 664 return C_SACON 665 } 666 return C_LACON 667 668 case obj.NAME_PARAM: 669 if a.Reg == REGSP { 670 // unset base register for better printing, since 671 // a.Offset is still relative to pseudo-FP. 672 a.Reg = obj.REG_NONE 673 } 674 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize 675 if c.instoffset >= -BIG && c.instoffset < BIG { 676 return C_SACON 677 } 678 return C_LACON 679 680 default: 681 return C_GOK 682 } 683 684 if c.instoffset == 0 { 685 return C_ZCON 686 } 687 if c.instoffset >= 0 { 688 if c.instoffset <= 0x7fff { 689 return C_SCON 690 } 691 if c.instoffset <= 0xffff { 692 return C_ANDCON 693 } 694 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && ((instoffset & (1<<31)) == 0) */ 695 return C_UCON 696 } 697 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 698 return C_LCON 699 } 700 return C_DCON 701 } 702 703 if c.instoffset >= -0x8000 { 704 return C_ADDCON 705 } 706 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 707 return C_UCON 708 } 709 if isint32(c.instoffset) { 710 return C_LCON 711 } 712 return C_DCON 713 714 case obj.TYPE_BRANCH: 715 return C_SBRA 716 } 717 718 return C_GOK 719} 720 721func (c *ctxtz) oplook(p *obj.Prog) *Optab { 722 // Return cached optab entry if available. 723 if p.Optab != 0 { 724 return &optab[p.Optab-1] 725 } 726 if len(p.RestArgs) > 3 { 727 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs)) 728 return nil 729 } 730 731 // Initialize classes for all arguments. 732 p.From.Class = int8(c.aclass(&p.From) + 1) 733 p.To.Class = int8(c.aclass(&p.To) + 1) 734 for i := range p.RestArgs { 735 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1) 736 } 737 738 // Mirrors the argument list in Optab. 739 args := [...]int8{ 740 p.From.Class - 1, 741 C_NONE, // p.Reg 742 C_NONE, // p.RestArgs[0] 743 C_NONE, // p.RestArgs[1] 744 C_NONE, // p.RestArgs[2] 745 p.To.Class - 1, 746 } 747 // Fill in argument class for p.Reg. 748 switch { 749 case REG_R0 <= p.Reg && p.Reg <= REG_R15: 750 args[1] = C_REG 751 case REG_V0 <= p.Reg && p.Reg <= REG_V31: 752 args[1] = C_VREG 753 case REG_F0 <= p.Reg && p.Reg <= REG_F15: 754 args[1] = C_FREG 755 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15: 756 args[1] = C_AREG 757 } 758 // Fill in argument classes for p.RestArgs. 759 for i, a := range p.RestArgs { 760 args[2+i] = a.Class - 1 761 } 762 763 // Lookup op in optab. 764 ops := oprange[p.As&obj.AMask] 765 cmp := [len(args)]*[C_NCLASS]bool{} 766 for i := range cmp { 767 cmp[i] = &xcmp[args[i]] 768 } 769 for i := range ops { 770 op := &ops[i] 771 if cmp[0][op.a1] && cmp[1][op.a2] && 772 cmp[2][op.a3] && cmp[3][op.a4] && 773 cmp[4][op.a5] && cmp[5][op.a6] { 774 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 775 return op 776 } 777 } 778 779 // Cannot find a case; abort. 780 s := "" 781 for _, a := range args { 782 s += fmt.Sprintf(" %v", DRconv(int(a))) 783 } 784 c.ctxt.Diag("illegal combination %v%v\n", p.As, s) 785 c.ctxt.Diag("prog: %v\n", p) 786 return nil 787} 788 789func cmp(a int, b int) bool { 790 if a == b { 791 return true 792 } 793 switch a { 794 case C_DCON: 795 if b == C_LCON { 796 return true 797 } 798 fallthrough 799 case C_LCON: 800 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 801 return true 802 } 803 804 case C_ADDCON: 805 if b == C_ZCON || b == C_SCON { 806 return true 807 } 808 809 case C_ANDCON: 810 if b == C_ZCON || b == C_SCON { 811 return true 812 } 813 814 case C_UCON: 815 if b == C_ZCON || b == C_SCON { 816 return true 817 } 818 819 case C_SCON: 820 if b == C_ZCON { 821 return true 822 } 823 824 case C_LACON: 825 if b == C_SACON { 826 return true 827 } 828 829 case C_LBRA: 830 if b == C_SBRA { 831 return true 832 } 833 834 case C_LAUTO: 835 if b == C_SAUTO { 836 return true 837 } 838 839 case C_LOREG: 840 if b == C_ZOREG || b == C_SOREG { 841 return true 842 } 843 844 case C_SOREG: 845 if b == C_ZOREG { 846 return true 847 } 848 849 case C_ANY: 850 return true 851 } 852 853 return false 854} 855 856type ocmp []Optab 857 858func (x ocmp) Len() int { 859 return len(x) 860} 861 862func (x ocmp) Swap(i, j int) { 863 x[i], x[j] = x[j], x[i] 864} 865 866func (x ocmp) Less(i, j int) bool { 867 p1 := &x[i] 868 p2 := &x[j] 869 n := int(p1.as) - int(p2.as) 870 if n != 0 { 871 return n < 0 872 } 873 n = int(p1.a1) - int(p2.a1) 874 if n != 0 { 875 return n < 0 876 } 877 n = int(p1.a2) - int(p2.a2) 878 if n != 0 { 879 return n < 0 880 } 881 n = int(p1.a3) - int(p2.a3) 882 if n != 0 { 883 return n < 0 884 } 885 n = int(p1.a4) - int(p2.a4) 886 if n != 0 { 887 return n < 0 888 } 889 return false 890} 891func opset(a, b obj.As) { 892 oprange[a&obj.AMask] = oprange[b&obj.AMask] 893} 894 895func buildop(ctxt *obj.Link) { 896 if oprange[AORW&obj.AMask] != nil { 897 // Already initialized; stop now. 898 // This happens in the cmd/asm tests, 899 // each of which re-initializes the arch. 900 return 901 } 902 903 for i := 0; i < C_NCLASS; i++ { 904 for n := 0; n < C_NCLASS; n++ { 905 if cmp(n, i) { 906 xcmp[i][n] = true 907 } 908 } 909 } 910 sort.Sort(ocmp(optab)) 911 for i := 0; i < len(optab); i++ { 912 r := optab[i].as 913 start := i 914 for ; i+1 < len(optab); i++ { 915 if optab[i+1].as != r { 916 break 917 } 918 } 919 oprange[r&obj.AMask] = optab[start : i+1] 920 921 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 922 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 923 switch r { 924 case AADD: 925 opset(AADDC, r) 926 opset(AADDW, r) 927 opset(AADDE, r) 928 opset(AMULLD, r) 929 opset(AMULLW, r) 930 case ADIVW: 931 opset(ADIVD, r) 932 opset(ADIVDU, r) 933 opset(ADIVWU, r) 934 opset(AMODD, r) 935 opset(AMODDU, r) 936 opset(AMODW, r) 937 opset(AMODWU, r) 938 case AMULHD: 939 opset(AMULHDU, r) 940 case AMOVBZ: 941 opset(AMOVH, r) 942 opset(AMOVHZ, r) 943 case ALA: 944 opset(ALAY, r) 945 case AMVC: 946 opset(AMVCIN, r) 947 opset(ACLC, r) 948 opset(AXC, r) 949 opset(AOC, r) 950 opset(ANC, r) 951 case ASTCK: 952 opset(ASTCKC, r) 953 opset(ASTCKE, r) 954 opset(ASTCKF, r) 955 case ALAAG: 956 opset(ALAA, r) 957 opset(ALAAL, r) 958 opset(ALAALG, r) 959 opset(ALAN, r) 960 opset(ALANG, r) 961 opset(ALAX, r) 962 opset(ALAXG, r) 963 opset(ALAO, r) 964 opset(ALAOG, r) 965 case ASTMG: 966 opset(ASTMY, r) 967 case ALMG: 968 opset(ALMY, r) 969 case ABEQ: 970 opset(ABGE, r) 971 opset(ABGT, r) 972 opset(ABLE, r) 973 opset(ABLT, r) 974 opset(ABNE, r) 975 opset(ABVC, r) 976 opset(ABVS, r) 977 opset(ABLEU, r) 978 opset(ABLTU, r) 979 case ABR: 980 opset(ABL, r) 981 case ABC: 982 opset(ABCL, r) 983 case AFABS: 984 opset(AFNABS, r) 985 opset(ALPDFR, r) 986 opset(ALNDFR, r) 987 opset(AFNEG, r) 988 opset(AFNEGS, r) 989 opset(ALEDBR, r) 990 opset(ALDEBR, r) 991 opset(AFSQRT, r) 992 opset(AFSQRTS, r) 993 case AFADD: 994 opset(AFADDS, r) 995 opset(AFDIV, r) 996 opset(AFDIVS, r) 997 opset(AFSUB, r) 998 opset(AFSUBS, r) 999 case AFMADD: 1000 opset(AFMADDS, r) 1001 opset(AFMSUB, r) 1002 opset(AFMSUBS, r) 1003 case AFMUL: 1004 opset(AFMULS, r) 1005 case AFCMPO: 1006 opset(AFCMPU, r) 1007 opset(ACEBR, r) 1008 case AAND: 1009 opset(AOR, r) 1010 opset(AXOR, r) 1011 case AANDW: 1012 opset(AORW, r) 1013 opset(AXORW, r) 1014 case ASLD: 1015 opset(ASRD, r) 1016 opset(ASLW, r) 1017 opset(ASRW, r) 1018 opset(ASRAD, r) 1019 opset(ASRAW, r) 1020 opset(ARLL, r) 1021 opset(ARLLG, r) 1022 case ARNSBG: 1023 opset(ARXSBG, r) 1024 opset(AROSBG, r) 1025 opset(ARNSBGT, r) 1026 opset(ARXSBGT, r) 1027 opset(AROSBGT, r) 1028 opset(ARISBG, r) 1029 opset(ARISBGN, r) 1030 opset(ARISBGZ, r) 1031 opset(ARISBGNZ, r) 1032 opset(ARISBHG, r) 1033 opset(ARISBLG, r) 1034 opset(ARISBHGZ, r) 1035 opset(ARISBLGZ, r) 1036 case ACSG: 1037 opset(ACS, r) 1038 case ASUB: 1039 opset(ASUBC, r) 1040 opset(ASUBE, r) 1041 opset(ASUBW, r) 1042 case ANEG: 1043 opset(ANEGW, r) 1044 case AFMOVD: 1045 opset(AFMOVS, r) 1046 case AMOVDBR: 1047 opset(AMOVWBR, r) 1048 case ACMP: 1049 opset(ACMPW, r) 1050 case ACMPU: 1051 opset(ACMPWU, r) 1052 case ATMHH: 1053 opset(ATMHL, r) 1054 opset(ATMLH, r) 1055 opset(ATMLL, r) 1056 case ACEFBRA: 1057 opset(ACDFBRA, r) 1058 opset(ACEGBRA, r) 1059 opset(ACDGBRA, r) 1060 opset(ACELFBR, r) 1061 opset(ACDLFBR, r) 1062 opset(ACELGBR, r) 1063 opset(ACDLGBR, r) 1064 case ACFEBRA: 1065 opset(ACFDBRA, r) 1066 opset(ACGEBRA, r) 1067 opset(ACGDBRA, r) 1068 opset(ACLFEBR, r) 1069 opset(ACLFDBR, r) 1070 opset(ACLGEBR, r) 1071 opset(ACLGDBR, r) 1072 case AFIEBR: 1073 opset(AFIDBR, r) 1074 case ACMPBEQ: 1075 opset(ACMPBGE, r) 1076 opset(ACMPBGT, r) 1077 opset(ACMPBLE, r) 1078 opset(ACMPBLT, r) 1079 opset(ACMPBNE, r) 1080 case ACMPUBEQ: 1081 opset(ACMPUBGE, r) 1082 opset(ACMPUBGT, r) 1083 opset(ACMPUBLE, r) 1084 opset(ACMPUBLT, r) 1085 opset(ACMPUBNE, r) 1086 case ACGRJ: 1087 opset(ACRJ, r) 1088 case ACLGRJ: 1089 opset(ACLRJ, r) 1090 case ACGIJ: 1091 opset(ACIJ, r) 1092 case ACLGIJ: 1093 opset(ACLIJ, r) 1094 case AMOVDEQ: 1095 opset(AMOVDGE, r) 1096 opset(AMOVDGT, r) 1097 opset(AMOVDLE, r) 1098 opset(AMOVDLT, r) 1099 opset(AMOVDNE, r) 1100 case ALOCGR: 1101 opset(ALOCR, r) 1102 case ALTDBR: 1103 opset(ALTEBR, r) 1104 case ATCDB: 1105 opset(ATCEB, r) 1106 case AVL: 1107 opset(AVLLEZB, r) 1108 opset(AVLLEZH, r) 1109 opset(AVLLEZF, r) 1110 opset(AVLLEZG, r) 1111 opset(AVLREPB, r) 1112 opset(AVLREPH, r) 1113 opset(AVLREPF, r) 1114 opset(AVLREPG, r) 1115 case AVLEG: 1116 opset(AVLBB, r) 1117 opset(AVLEB, r) 1118 opset(AVLEH, r) 1119 opset(AVLEF, r) 1120 opset(AVLEG, r) 1121 opset(AVLREP, r) 1122 case AVSTEG: 1123 opset(AVSTEB, r) 1124 opset(AVSTEH, r) 1125 opset(AVSTEF, r) 1126 case AVSCEG: 1127 opset(AVSCEF, r) 1128 case AVGEG: 1129 opset(AVGEF, r) 1130 case AVESLG: 1131 opset(AVESLB, r) 1132 opset(AVESLH, r) 1133 opset(AVESLF, r) 1134 opset(AVERLLB, r) 1135 opset(AVERLLH, r) 1136 opset(AVERLLF, r) 1137 opset(AVERLLG, r) 1138 opset(AVESRAB, r) 1139 opset(AVESRAH, r) 1140 opset(AVESRAF, r) 1141 opset(AVESRAG, r) 1142 opset(AVESRLB, r) 1143 opset(AVESRLH, r) 1144 opset(AVESRLF, r) 1145 opset(AVESRLG, r) 1146 case AVLGVG: 1147 opset(AVLGVB, r) 1148 opset(AVLGVH, r) 1149 opset(AVLGVF, r) 1150 case AVLVGG: 1151 opset(AVLVGB, r) 1152 opset(AVLVGH, r) 1153 opset(AVLVGF, r) 1154 case AVZERO: 1155 opset(AVONE, r) 1156 case AVREPIG: 1157 opset(AVREPIB, r) 1158 opset(AVREPIH, r) 1159 opset(AVREPIF, r) 1160 case AVLEIG: 1161 opset(AVLEIB, r) 1162 opset(AVLEIH, r) 1163 opset(AVLEIF, r) 1164 case AVGMG: 1165 opset(AVGMB, r) 1166 opset(AVGMH, r) 1167 opset(AVGMF, r) 1168 case AVREPG: 1169 opset(AVREPB, r) 1170 opset(AVREPH, r) 1171 opset(AVREPF, r) 1172 case AVERIMG: 1173 opset(AVERIMB, r) 1174 opset(AVERIMH, r) 1175 opset(AVERIMF, r) 1176 case AVFTCIDB: 1177 opset(AWFTCIDB, r) 1178 case AVLR: 1179 opset(AVUPHB, r) 1180 opset(AVUPHH, r) 1181 opset(AVUPHF, r) 1182 opset(AVUPLHB, r) 1183 opset(AVUPLHH, r) 1184 opset(AVUPLHF, r) 1185 opset(AVUPLB, r) 1186 opset(AVUPLHW, r) 1187 opset(AVUPLF, r) 1188 opset(AVUPLLB, r) 1189 opset(AVUPLLH, r) 1190 opset(AVUPLLF, r) 1191 opset(AVCLZB, r) 1192 opset(AVCLZH, r) 1193 opset(AVCLZF, r) 1194 opset(AVCLZG, r) 1195 opset(AVCTZB, r) 1196 opset(AVCTZH, r) 1197 opset(AVCTZF, r) 1198 opset(AVCTZG, r) 1199 opset(AVLDEB, r) 1200 opset(AWLDEB, r) 1201 opset(AVFLCDB, r) 1202 opset(AWFLCDB, r) 1203 opset(AVFLNDB, r) 1204 opset(AWFLNDB, r) 1205 opset(AVFLPDB, r) 1206 opset(AWFLPDB, r) 1207 opset(AVFSQDB, r) 1208 opset(AWFSQDB, r) 1209 opset(AVISTRB, r) 1210 opset(AVISTRH, r) 1211 opset(AVISTRF, r) 1212 opset(AVISTRBS, r) 1213 opset(AVISTRHS, r) 1214 opset(AVISTRFS, r) 1215 opset(AVLCB, r) 1216 opset(AVLCH, r) 1217 opset(AVLCF, r) 1218 opset(AVLCG, r) 1219 opset(AVLPB, r) 1220 opset(AVLPH, r) 1221 opset(AVLPF, r) 1222 opset(AVLPG, r) 1223 opset(AVPOPCT, r) 1224 opset(AVSEGB, r) 1225 opset(AVSEGH, r) 1226 opset(AVSEGF, r) 1227 case AVECG: 1228 opset(AVECB, r) 1229 opset(AVECH, r) 1230 opset(AVECF, r) 1231 opset(AVECLB, r) 1232 opset(AVECLH, r) 1233 opset(AVECLF, r) 1234 opset(AVECLG, r) 1235 opset(AWFCDB, r) 1236 opset(AWFKDB, r) 1237 case AVCEQG: 1238 opset(AVCEQB, r) 1239 opset(AVCEQH, r) 1240 opset(AVCEQF, r) 1241 opset(AVCEQBS, r) 1242 opset(AVCEQHS, r) 1243 opset(AVCEQFS, r) 1244 opset(AVCEQGS, r) 1245 opset(AVCHB, r) 1246 opset(AVCHH, r) 1247 opset(AVCHF, r) 1248 opset(AVCHG, r) 1249 opset(AVCHBS, r) 1250 opset(AVCHHS, r) 1251 opset(AVCHFS, r) 1252 opset(AVCHGS, r) 1253 opset(AVCHLB, r) 1254 opset(AVCHLH, r) 1255 opset(AVCHLF, r) 1256 opset(AVCHLG, r) 1257 opset(AVCHLBS, r) 1258 opset(AVCHLHS, r) 1259 opset(AVCHLFS, r) 1260 opset(AVCHLGS, r) 1261 case AVFAEF: 1262 opset(AVFAEB, r) 1263 opset(AVFAEH, r) 1264 opset(AVFAEBS, r) 1265 opset(AVFAEHS, r) 1266 opset(AVFAEFS, r) 1267 opset(AVFAEZB, r) 1268 opset(AVFAEZH, r) 1269 opset(AVFAEZF, r) 1270 opset(AVFAEZBS, r) 1271 opset(AVFAEZHS, r) 1272 opset(AVFAEZFS, r) 1273 opset(AVFEEB, r) 1274 opset(AVFEEH, r) 1275 opset(AVFEEF, r) 1276 opset(AVFEEBS, r) 1277 opset(AVFEEHS, r) 1278 opset(AVFEEFS, r) 1279 opset(AVFEEZB, r) 1280 opset(AVFEEZH, r) 1281 opset(AVFEEZF, r) 1282 opset(AVFEEZBS, r) 1283 opset(AVFEEZHS, r) 1284 opset(AVFEEZFS, r) 1285 opset(AVFENEB, r) 1286 opset(AVFENEH, r) 1287 opset(AVFENEF, r) 1288 opset(AVFENEBS, r) 1289 opset(AVFENEHS, r) 1290 opset(AVFENEFS, r) 1291 opset(AVFENEZB, r) 1292 opset(AVFENEZH, r) 1293 opset(AVFENEZF, r) 1294 opset(AVFENEZBS, r) 1295 opset(AVFENEZHS, r) 1296 opset(AVFENEZFS, r) 1297 case AVPKSG: 1298 opset(AVPKSH, r) 1299 opset(AVPKSF, r) 1300 opset(AVPKSHS, r) 1301 opset(AVPKSFS, r) 1302 opset(AVPKSGS, r) 1303 opset(AVPKLSH, r) 1304 opset(AVPKLSF, r) 1305 opset(AVPKLSG, r) 1306 opset(AVPKLSHS, r) 1307 opset(AVPKLSFS, r) 1308 opset(AVPKLSGS, r) 1309 case AVAQ: 1310 opset(AVAB, r) 1311 opset(AVAH, r) 1312 opset(AVAF, r) 1313 opset(AVAG, r) 1314 opset(AVACCB, r) 1315 opset(AVACCH, r) 1316 opset(AVACCF, r) 1317 opset(AVACCG, r) 1318 opset(AVACCQ, r) 1319 opset(AVN, r) 1320 opset(AVNC, r) 1321 opset(AVAVGB, r) 1322 opset(AVAVGH, r) 1323 opset(AVAVGF, r) 1324 opset(AVAVGG, r) 1325 opset(AVAVGLB, r) 1326 opset(AVAVGLH, r) 1327 opset(AVAVGLF, r) 1328 opset(AVAVGLG, r) 1329 opset(AVCKSM, r) 1330 opset(AVX, r) 1331 opset(AVFADB, r) 1332 opset(AWFADB, r) 1333 opset(AVFCEDB, r) 1334 opset(AVFCEDBS, r) 1335 opset(AWFCEDB, r) 1336 opset(AWFCEDBS, r) 1337 opset(AVFCHDB, r) 1338 opset(AVFCHDBS, r) 1339 opset(AWFCHDB, r) 1340 opset(AWFCHDBS, r) 1341 opset(AVFCHEDB, r) 1342 opset(AVFCHEDBS, r) 1343 opset(AWFCHEDB, r) 1344 opset(AWFCHEDBS, r) 1345 opset(AVFMDB, r) 1346 opset(AWFMDB, r) 1347 opset(AVGFMB, r) 1348 opset(AVGFMH, r) 1349 opset(AVGFMF, r) 1350 opset(AVGFMG, r) 1351 opset(AVMXB, r) 1352 opset(AVMXH, r) 1353 opset(AVMXF, r) 1354 opset(AVMXG, r) 1355 opset(AVMXLB, r) 1356 opset(AVMXLH, r) 1357 opset(AVMXLF, r) 1358 opset(AVMXLG, r) 1359 opset(AVMNB, r) 1360 opset(AVMNH, r) 1361 opset(AVMNF, r) 1362 opset(AVMNG, r) 1363 opset(AVMNLB, r) 1364 opset(AVMNLH, r) 1365 opset(AVMNLF, r) 1366 opset(AVMNLG, r) 1367 opset(AVMRHB, r) 1368 opset(AVMRHH, r) 1369 opset(AVMRHF, r) 1370 opset(AVMRHG, r) 1371 opset(AVMRLB, r) 1372 opset(AVMRLH, r) 1373 opset(AVMRLF, r) 1374 opset(AVMRLG, r) 1375 opset(AVMEB, r) 1376 opset(AVMEH, r) 1377 opset(AVMEF, r) 1378 opset(AVMLEB, r) 1379 opset(AVMLEH, r) 1380 opset(AVMLEF, r) 1381 opset(AVMOB, r) 1382 opset(AVMOH, r) 1383 opset(AVMOF, r) 1384 opset(AVMLOB, r) 1385 opset(AVMLOH, r) 1386 opset(AVMLOF, r) 1387 opset(AVMHB, r) 1388 opset(AVMHH, r) 1389 opset(AVMHF, r) 1390 opset(AVMLHB, r) 1391 opset(AVMLHH, r) 1392 opset(AVMLHF, r) 1393 opset(AVMLH, r) 1394 opset(AVMLHW, r) 1395 opset(AVMLF, r) 1396 opset(AVNO, r) 1397 opset(AVO, r) 1398 opset(AVPKH, r) 1399 opset(AVPKF, r) 1400 opset(AVPKG, r) 1401 opset(AVSUMGH, r) 1402 opset(AVSUMGF, r) 1403 opset(AVSUMQF, r) 1404 opset(AVSUMQG, r) 1405 opset(AVSUMB, r) 1406 opset(AVSUMH, r) 1407 case AVERLLVG: 1408 opset(AVERLLVB, r) 1409 opset(AVERLLVH, r) 1410 opset(AVERLLVF, r) 1411 opset(AVESLVB, r) 1412 opset(AVESLVH, r) 1413 opset(AVESLVF, r) 1414 opset(AVESLVG, r) 1415 opset(AVESRAVB, r) 1416 opset(AVESRAVH, r) 1417 opset(AVESRAVF, r) 1418 opset(AVESRAVG, r) 1419 opset(AVESRLVB, r) 1420 opset(AVESRLVH, r) 1421 opset(AVESRLVF, r) 1422 opset(AVESRLVG, r) 1423 opset(AVFDDB, r) 1424 opset(AWFDDB, r) 1425 opset(AVFSDB, r) 1426 opset(AWFSDB, r) 1427 opset(AVSL, r) 1428 opset(AVSLB, r) 1429 opset(AVSRA, r) 1430 opset(AVSRAB, r) 1431 opset(AVSRL, r) 1432 opset(AVSRLB, r) 1433 opset(AVSB, r) 1434 opset(AVSH, r) 1435 opset(AVSF, r) 1436 opset(AVSG, r) 1437 opset(AVSQ, r) 1438 opset(AVSCBIB, r) 1439 opset(AVSCBIH, r) 1440 opset(AVSCBIF, r) 1441 opset(AVSCBIG, r) 1442 opset(AVSCBIQ, r) 1443 case AVACQ: 1444 opset(AVACCCQ, r) 1445 opset(AVGFMAB, r) 1446 opset(AVGFMAH, r) 1447 opset(AVGFMAF, r) 1448 opset(AVGFMAG, r) 1449 opset(AVMALB, r) 1450 opset(AVMALHW, r) 1451 opset(AVMALF, r) 1452 opset(AVMAHB, r) 1453 opset(AVMAHH, r) 1454 opset(AVMAHF, r) 1455 opset(AVMALHB, r) 1456 opset(AVMALHH, r) 1457 opset(AVMALHF, r) 1458 opset(AVMAEB, r) 1459 opset(AVMAEH, r) 1460 opset(AVMAEF, r) 1461 opset(AVMALEB, r) 1462 opset(AVMALEH, r) 1463 opset(AVMALEF, r) 1464 opset(AVMAOB, r) 1465 opset(AVMAOH, r) 1466 opset(AVMAOF, r) 1467 opset(AVMALOB, r) 1468 opset(AVMALOH, r) 1469 opset(AVMALOF, r) 1470 opset(AVSTRCB, r) 1471 opset(AVSTRCH, r) 1472 opset(AVSTRCF, r) 1473 opset(AVSTRCBS, r) 1474 opset(AVSTRCHS, r) 1475 opset(AVSTRCFS, r) 1476 opset(AVSTRCZB, r) 1477 opset(AVSTRCZH, r) 1478 opset(AVSTRCZF, r) 1479 opset(AVSTRCZBS, r) 1480 opset(AVSTRCZHS, r) 1481 opset(AVSTRCZFS, r) 1482 opset(AVSBCBIQ, r) 1483 opset(AVSBIQ, r) 1484 opset(AVMSLG, r) 1485 opset(AVMSLEG, r) 1486 opset(AVMSLOG, r) 1487 opset(AVMSLEOG, r) 1488 case AVSEL: 1489 opset(AVFMADB, r) 1490 opset(AWFMADB, r) 1491 opset(AVFMSDB, r) 1492 opset(AWFMSDB, r) 1493 opset(AVPERM, r) 1494 case AKM: 1495 opset(AKMC, r) 1496 opset(AKLMD, r) 1497 opset(AKIMD, r) 1498 case AKMA: 1499 opset(AKMCTR, r) 1500 } 1501 } 1502} 1503 1504const ( 1505 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1506 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1507 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1508 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1509 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1510 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1511 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1512 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1513 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1514 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1515 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1516 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1517 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1518 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1519 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1520 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1521 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1522 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1523 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1524 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1525 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1526 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1527 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1528 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1529 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1530 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1531 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1532 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1533 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1534 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1535 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1536 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1537 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1538 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1539 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1540 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1541 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1542 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1543 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1544 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1545 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1546 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1547 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1548 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1549 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1550 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1551 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1552 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1553 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1554 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1555 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1556 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1557 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1558 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1559 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1560 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1561 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1562 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1563 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1564 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1565 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1566 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1567 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1568 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1569 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1570 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1571 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1572 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1573 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1574 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1575 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1576 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1577 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1578 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1579 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1580 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1581 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1582 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1583 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1584 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1585 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1586 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1587 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1588 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1589 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1590 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1591 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1592 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1593 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1594 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1595 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1596 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1597 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1598 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1599 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1600 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1601 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1602 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1603 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1604 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1605 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1606 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1607 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1608 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1609 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1610 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1611 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1612 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1613 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1614 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1615 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1616 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1617 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1618 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1619 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1620 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1621 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1622 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1623 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1624 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1625 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1626 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1627 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1628 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1629 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1630 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1631 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1632 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1633 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1634 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1635 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1636 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1637 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1638 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1639 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1640 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1641 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1642 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1643 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1644 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1645 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1646 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1647 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1648 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1649 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1650 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1651 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1652 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1653 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1654 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1655 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1656 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1657 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1658 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1659 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1660 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1661 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1662 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1663 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1664 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1665 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1666 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1667 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1668 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1669 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1670 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1671 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1672 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1673 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1674 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1675 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1676 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1677 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1678 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1679 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1680 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1681 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1682 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1683 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1684 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1685 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1686 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1687 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1688 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1689 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1690 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1691 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1692 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1693 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1694 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1695 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1696 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1697 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1698 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1699 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1700 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1701 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1702 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1703 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1704 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1705 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1706 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1707 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1708 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1709 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1710 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1711 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1712 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1713 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1714 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1715 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1716 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1717 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1718 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1719 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1720 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1721 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1722 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1723 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1724 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1725 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1726 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1727 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1728 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1729 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1730 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1731 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1732 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1733 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1734 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1735 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1736 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1737 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1738 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1739 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1740 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1741 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1742 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1743 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1744 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1745 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1746 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1747 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1748 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1749 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1750 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1751 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1752 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1753 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1754 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1755 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1756 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1757 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1758 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1759 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1760 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1761 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1762 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1763 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1764 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1765 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1766 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1767 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1768 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1769 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1770 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1771 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1772 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1773 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1774 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1775 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1776 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1777 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1778 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1779 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1780 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1781 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1782 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1783 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1784 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1785 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1786 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1787 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1788 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1789 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1790 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1791 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1792 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1793 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1794 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1795 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1796 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1797 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1798 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1799 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1800 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1801 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1802 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1803 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1804 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1805 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1806 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1807 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1808 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1809 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1810 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1811 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1812 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1813 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1814 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1815 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1816 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1817 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1818 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1819 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1820 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1821 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1822 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1823 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1824 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1825 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1826 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1827 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1828 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1829 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1830 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1831 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1832 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1833 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1834 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1835 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1836 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1837 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1838 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1839 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1840 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1841 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1842 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1843 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1844 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1845 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1846 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1847 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1848 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1849 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1850 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1851 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1852 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1853 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1854 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1855 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1856 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1857 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1858 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1859 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1860 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1861 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1862 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1863 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1864 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1865 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1866 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1867 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1868 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1869 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1870 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1871 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1872 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1873 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1874 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1875 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1876 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1877 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1878 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1879 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1880 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1881 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1882 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1883 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1884 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1885 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1886 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1887 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1888 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1889 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1890 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1891 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1892 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1893 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1894 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1895 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1896 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1897 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1898 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1899 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1900 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1901 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1902 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1903 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1904 op_KMA uint32 = 0xB929 // FORMAT_RRF2 CIPHER MESSAGE WITH AUTHENTICATION 1905 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1906 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1907 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1908 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1909 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1910 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1911 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1912 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1913 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1914 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1915 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1916 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1917 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1918 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1919 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1920 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1921 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1922 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1923 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1924 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1925 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1926 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1927 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1928 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1929 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1930 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1931 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1932 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1933 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1934 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1935 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1936 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1937 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1938 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1939 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1940 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1941 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1942 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1943 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1944 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1945 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1946 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1947 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1948 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1949 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1950 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1951 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1952 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1953 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1954 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1955 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1956 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1957 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1958 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1959 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1960 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1961 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1962 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1963 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1964 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1965 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1966 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1967 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1968 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1969 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1970 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1971 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1972 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1973 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1974 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1975 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1976 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1977 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1978 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1979 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1980 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1981 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1982 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1983 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1984 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1985 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1986 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1987 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1988 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1989 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1990 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1991 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1992 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1993 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1994 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1995 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1996 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1997 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1998 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1999 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 2000 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 2001 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 2002 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 2003 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 2004 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 2005 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 2006 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 2007 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 2008 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 2009 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 2010 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 2011 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 2012 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 2013 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 2014 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 2015 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 2016 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 2017 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 2018 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 2019 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 2020 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 2021 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 2022 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 2023 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 2024 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 2025 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 2026 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 2027 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 2028 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 2029 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 2030 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 2031 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 2032 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 2033 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 2034 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 2035 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 2036 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 2037 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 2038 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 2039 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 2040 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 2041 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 2042 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 2043 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 2044 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 2045 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 2046 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 2047 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 2048 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 2049 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 2050 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 2051 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 2052 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 2053 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 2054 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 2055 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 2056 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 2057 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 2058 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 2059 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 2060 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 2061 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 2062 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 2063 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 2064 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 2065 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 2066 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 2067 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 2068 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 2069 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 2070 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 2071 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 2072 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 2073 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 2074 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 2075 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 2076 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 2077 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 2078 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 2079 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 2080 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 2081 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 2082 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 2083 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 2084 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 2085 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 2086 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 2087 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 2088 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 2089 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 2090 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 2091 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 2092 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 2093 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 2094 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 2095 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 2096 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 2097 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 2098 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 2099 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 2100 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 2101 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 2102 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 2103 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 2104 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2105 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2106 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2107 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2108 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2109 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2110 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 2111 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 2112 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 2113 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 2114 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2115 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 2116 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 2117 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2118 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 2119 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2120 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2121 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2122 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 2123 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 2124 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 2125 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 2126 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2127 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 2128 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 2129 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 2130 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 2131 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 2132 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 2133 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 2134 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 2135 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 2136 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 2137 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 2138 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 2139 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 2140 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 2141 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 2142 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 2143 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 2144 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 2145 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 2146 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 2147 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 2148 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 2149 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 2150 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 2151 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2152 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2153 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2154 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2155 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2156 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2157 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2158 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2159 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2160 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2161 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2162 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2163 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2164 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2165 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2166 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2167 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2168 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2169 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2170 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2171 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2172 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2173 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2174 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2175 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2176 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2177 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2178 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2179 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2180 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2181 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2182 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2183 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2184 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2185 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2186 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2187 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2188 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2189 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2190 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2191 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2192 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2193 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2194 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2195 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2196 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2197 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2198 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2199 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2200 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2201 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2202 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2203 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2204 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2205 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2206 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2207 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2208 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2209 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2210 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2211 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2212 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2213 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2214 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2215 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2216 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2217 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2218 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2219 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2220 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2221 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2222 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2223 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2224 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2225 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2226 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2227 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2228 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2229 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2230 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2231 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2232 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2233 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2234 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2235 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2236 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2237 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2238 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2239 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2240 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2241 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2242 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2243 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2244 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2245 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2246 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2247 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2248 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2249 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2250 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2251 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2252 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2253 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2254 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2255 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2256 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2257 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2258 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2259 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2260 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2261 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2262 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2263 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2264 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2265 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2266 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2267 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2268 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2269 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2270 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2271 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2272 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2273 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2274 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2275 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2276 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2277 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2278 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2279 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2280 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2281 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2282 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2283 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2284 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2285 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2286 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2287 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2288 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2289 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2290 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2291 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2292 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2293 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2294 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2295 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2296 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2297 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2298 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2299 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2300 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2301 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2302 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2303 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2304 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2305 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2306 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2307 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2308 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2309 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2310 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2311 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2312 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2313 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2314 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2315 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2316 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2317 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2318 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2319 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2320 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2321 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2322 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2323 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2324 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2325 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2326 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2327 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2328 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2329 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2330 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2331 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2332 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2333 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2334 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2335 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2336 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2337 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2338 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2339 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2340 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2341 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2342 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2343 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2344 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2345 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2346 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2347 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2348 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2349 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2350 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2351 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2352 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2353 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2354 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2355 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2356 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2357 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2358 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2359 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2360 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2361 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2362 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2363 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2364 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2365 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2366 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2367 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2368 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2369 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2370 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2371 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2372 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2373 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2374 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2375 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2376 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2377 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2378 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2379 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2380 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2381 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2382 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2383 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2384 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2385 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2386 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2387 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2388 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2389 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2390 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2391 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2392 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2393 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2394 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2395 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2396 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2397 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2398 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2399 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2400 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2401 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2402 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2403 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2404 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2405 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2406 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2407 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2408 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2409 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2410 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2411 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2412 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2413 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2414 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2415 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2416 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2417 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2418 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2419 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2420 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2421 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2422 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2423 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2424 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2425 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2426 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2427 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2428 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2429 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2430 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2431 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2432 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2433 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2434 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2435 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2436 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2437 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2438 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2439 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2440 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2441 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2442 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2443 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2444 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2445 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2446 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2447 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2448 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2449 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2450 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2451 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2452 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2453 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2454 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2455 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2456 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2457 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2458 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2459 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2460 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2461 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2462 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2463 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2464 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2465 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2466 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2467 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2468 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2469 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2470 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2471 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2472 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2473 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2474 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2475 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2476 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2477 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2478 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2479 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2480 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2481 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2482 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2483 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2484 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2485 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2486 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2487 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2488 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2489 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2490 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2491 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2492 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2493 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2494 op_BRRK uint32 = 0x0001 // FORMAT_E BREAKPOINT 2495 2496 // added in z13 2497 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2498 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2499 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2500 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2501 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2502 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2503 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2504 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2505 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2506 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2507 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2508 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2509 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2510 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2511 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2512 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2513 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2514 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2515 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2516 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2517 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2518 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2519 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2520 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2521 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2522 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2523 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2524 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2525 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2526 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2527 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2528 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2529 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2530 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2531 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2532 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2533 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2534 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2535 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2536 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2537 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2538 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2539 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2540 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2541 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2542 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2543 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2544 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2545 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2546 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2547 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2548 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2549 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2550 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2551 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2552 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2553 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2554 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2555 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2556 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2557 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2558 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2559 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2560 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2561 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2562 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2563 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2564 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2565 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2566 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2567 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2568 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2569 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2570 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2571 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2572 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2573 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2574 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2575 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2576 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2577 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2578 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2579 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2580 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2581 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2582 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2583 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2584 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2585 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2586 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2587 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2588 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2589 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2590 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2591 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2592 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2593 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2594 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2595 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2596 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2597 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2598 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2599 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2600 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2601 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2602 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2603 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2604 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2605 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2606 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2607 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2608 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2609 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2610 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2611 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2612 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2613 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2614 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2615 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2616 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2617 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2618 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2619 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2620 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2621 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2622 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2623 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2624 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2625 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2626 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2627 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2628 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2629 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2630 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2631 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2632 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2633 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2634 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2635 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2636 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2637 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2638 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2639 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2640 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2641 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2642 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2643 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2644 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2645 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2646 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2647 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2648 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2649 op_VMSL uint32 = 0xE7B8 // VRR-d VECTOR MULTIPLY SUM LOGICAL 2650 2651 // added in z15 2652 op_KDSA uint32 = 0xB93A // FORMAT_RRE COMPUTE DIGITAL SIGNATURE AUTHENTICATION (KDSA) 2653 2654) 2655 2656func oclass(a *obj.Addr) int { 2657 return int(a.Class) - 1 2658} 2659 2660// Add a relocation for the immediate in a RIL style instruction. 2661// The addend will be adjusted as required. 2662func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2663 if sym == nil { 2664 c.ctxt.Diag("require symbol to apply relocation") 2665 } 2666 offset := int64(2) // relocation offset from start of instruction 2667 rel := obj.Addrel(c.cursym) 2668 rel.Off = int32(c.pc + offset) 2669 rel.Siz = 4 2670 rel.Sym = sym 2671 rel.Add = add + offset + int64(rel.Siz) 2672 rel.Type = objabi.R_PCRELDBL 2673 return rel 2674} 2675 2676func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2677 if sym == nil { 2678 c.ctxt.Diag("require symbol to apply relocation") 2679 } 2680 offset += int64(2) // relocation offset from start of instruction 2681 rel := obj.Addrel(c.cursym) 2682 rel.Off = int32(c.pc + offset) 2683 rel.Siz = 4 2684 rel.Sym = sym 2685 rel.Add = add + offset + int64(rel.Siz) 2686 rel.Type = objabi.R_PCRELDBL 2687 return rel 2688} 2689 2690// Add a CALL relocation for the immediate in a RIL style instruction. 2691// The addend will be adjusted as required. 2692func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2693 if sym == nil { 2694 c.ctxt.Diag("require symbol to apply relocation") 2695 } 2696 offset := int64(2) // relocation offset from start of instruction 2697 rel := obj.Addrel(c.cursym) 2698 rel.Off = int32(c.pc + offset) 2699 rel.Siz = 4 2700 rel.Sym = sym 2701 rel.Add = add + offset + int64(rel.Siz) 2702 rel.Type = objabi.R_CALL 2703 return rel 2704} 2705 2706func (c *ctxtz) branchMask(p *obj.Prog) CCMask { 2707 switch p.As { 2708 case ABRC, ALOCR, ALOCGR, 2709 ACRJ, ACGRJ, ACIJ, ACGIJ, 2710 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ: 2711 return CCMask(p.From.Offset) 2712 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2713 return Equal 2714 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2715 return GreaterOrEqual 2716 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2717 return Greater 2718 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2719 return LessOrEqual 2720 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2721 return Less 2722 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2723 return NotEqual 2724 case ABLEU: // LE or unordered 2725 return NotGreater 2726 case ABLTU: // LT or unordered 2727 return LessOrUnordered 2728 case ABVC: 2729 return Never // needs extra instruction 2730 case ABVS: 2731 return Unordered 2732 } 2733 c.ctxt.Diag("unknown conditional branch %v", p.As) 2734 return Always 2735} 2736 2737func regtmp(p *obj.Prog) uint32 { 2738 p.Mark |= USETMP 2739 return REGTMP 2740} 2741 2742func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2743 o := c.oplook(p) 2744 2745 if o == nil { 2746 return 2747 } 2748 2749 // If REGTMP is used in generated code, we need to set USETMP on p.Mark. 2750 // So we use regtmp(p) for REGTMP. 2751 2752 switch o.i { 2753 default: 2754 c.ctxt.Diag("unknown index %d", o.i) 2755 2756 case 0: // PSEUDO OPS 2757 break 2758 2759 case 1: // mov reg reg 2760 switch p.As { 2761 default: 2762 c.ctxt.Diag("unhandled operation: %v", p.As) 2763 case AMOVD: 2764 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2765 // sign extend 2766 case AMOVW: 2767 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2768 case AMOVH: 2769 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2770 case AMOVB: 2771 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2772 // zero extend 2773 case AMOVWZ: 2774 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2775 case AMOVHZ: 2776 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2777 case AMOVBZ: 2778 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2779 // reverse bytes 2780 case AMOVDBR: 2781 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2782 case AMOVWBR: 2783 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2784 // floating point 2785 case AFMOVD, AFMOVS: 2786 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2787 } 2788 2789 case 2: // arithmetic op reg [reg] reg 2790 r := p.Reg 2791 if r == 0 { 2792 r = p.To.Reg 2793 } 2794 2795 var opcode uint32 2796 2797 switch p.As { 2798 default: 2799 c.ctxt.Diag("invalid opcode") 2800 case AADD: 2801 opcode = op_AGRK 2802 case AADDC: 2803 opcode = op_ALGRK 2804 case AADDE: 2805 opcode = op_ALCGR 2806 case AADDW: 2807 opcode = op_ARK 2808 case AMULLW: 2809 opcode = op_MSGFR 2810 case AMULLD: 2811 opcode = op_MSGR 2812 case ADIVW, AMODW: 2813 opcode = op_DSGFR 2814 case ADIVWU, AMODWU: 2815 opcode = op_DLR 2816 case ADIVD, AMODD: 2817 opcode = op_DSGR 2818 case ADIVDU, AMODDU: 2819 opcode = op_DLGR 2820 } 2821 2822 switch p.As { 2823 default: 2824 2825 case AADD, AADDC, AADDW: 2826 if p.As == AADDW && r == p.To.Reg { 2827 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2828 } else { 2829 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2830 } 2831 2832 case AADDE, AMULLW, AMULLD: 2833 if r == p.To.Reg { 2834 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2835 } else if p.From.Reg == p.To.Reg { 2836 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2837 } else { 2838 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2839 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2840 } 2841 2842 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2843 if p.As == ADIVWU || p.As == ADIVDU { 2844 zRI(op_LGHI, regtmp(p), 0, asm) 2845 } 2846 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2847 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2848 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2849 2850 case AMODW, AMODWU, AMODD, AMODDU: 2851 if p.As == AMODWU || p.As == AMODDU { 2852 zRI(op_LGHI, regtmp(p), 0, asm) 2853 } 2854 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2855 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2856 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2857 2858 } 2859 2860 case 3: // mov $constant reg 2861 v := c.vregoff(&p.From) 2862 switch p.As { 2863 case AMOVBZ: 2864 v = int64(uint8(v)) 2865 case AMOVHZ: 2866 v = int64(uint16(v)) 2867 case AMOVWZ: 2868 v = int64(uint32(v)) 2869 case AMOVB: 2870 v = int64(int8(v)) 2871 case AMOVH: 2872 v = int64(int16(v)) 2873 case AMOVW: 2874 v = int64(int32(v)) 2875 } 2876 if int64(int16(v)) == v { 2877 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2878 } else if v&0xffff0000 == v { 2879 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2880 } else if v&0xffff00000000 == v { 2881 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2882 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2883 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2884 } else if int64(int32(v)) == v { 2885 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2886 } else if int64(uint32(v)) == v { 2887 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2888 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2889 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2890 } else { 2891 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2892 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2893 } 2894 2895 case 4: // multiply high (a*b)>>64 2896 r := p.Reg 2897 if r == 0 { 2898 r = p.To.Reg 2899 } 2900 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2901 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm) 2902 switch p.As { 2903 case AMULHDU: 2904 // Unsigned: move result into correct register. 2905 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2906 case AMULHD: 2907 // Signed: need to convert result. 2908 // See Hacker's Delight 8-3. 2909 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2910 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2911 zRRE(op_SGR, regtmp(p), REGTMP2, asm) 2912 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2913 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2914 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm) 2915 } 2916 2917 case 5: // syscall 2918 zI(op_SVC, 0, asm) 2919 2920 case 6: // logical op reg [reg] reg 2921 var oprr, oprre, oprrf uint32 2922 switch p.As { 2923 case AAND: 2924 oprre = op_NGR 2925 oprrf = op_NGRK 2926 case AANDW: 2927 oprr = op_NR 2928 oprrf = op_NRK 2929 case AOR: 2930 oprre = op_OGR 2931 oprrf = op_OGRK 2932 case AORW: 2933 oprr = op_OR 2934 oprrf = op_ORK 2935 case AXOR: 2936 oprre = op_XGR 2937 oprrf = op_XGRK 2938 case AXORW: 2939 oprr = op_XR 2940 oprrf = op_XRK 2941 } 2942 if p.Reg == 0 { 2943 if oprr != 0 { 2944 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2945 } else { 2946 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2947 } 2948 } else { 2949 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2950 } 2951 2952 case 7: // shift/rotate reg [reg] reg 2953 d2 := c.vregoff(&p.From) 2954 b2 := p.From.Reg 2955 r3 := p.Reg 2956 if r3 == 0 { 2957 r3 = p.To.Reg 2958 } 2959 r1 := p.To.Reg 2960 var opcode uint32 2961 switch p.As { 2962 default: 2963 case ASLD: 2964 opcode = op_SLLG 2965 case ASRD: 2966 opcode = op_SRLG 2967 case ASLW: 2968 opcode = op_SLLK 2969 case ASRW: 2970 opcode = op_SRLK 2971 case ARLL: 2972 opcode = op_RLL 2973 case ARLLG: 2974 opcode = op_RLLG 2975 case ASRAW: 2976 opcode = op_SRAK 2977 case ASRAD: 2978 opcode = op_SRAG 2979 } 2980 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2981 2982 case 8: // find leftmost one 2983 if p.To.Reg&1 != 0 { 2984 c.ctxt.Diag("target must be an even-numbered register") 2985 } 2986 // FLOGR also writes a mask to p.To.Reg+1. 2987 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2988 2989 case 9: // population count 2990 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2991 2992 case 10: // subtract reg [reg] reg 2993 r := int(p.Reg) 2994 2995 switch p.As { 2996 default: 2997 case ASUB: 2998 if r == 0 { 2999 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3000 } else { 3001 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 3002 } 3003 case ASUBC: 3004 if r == 0 { 3005 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3006 } else { 3007 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 3008 } 3009 case ASUBE: 3010 if r == 0 { 3011 r = int(p.To.Reg) 3012 } 3013 if r == int(p.To.Reg) { 3014 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3015 } else if p.From.Reg == p.To.Reg { 3016 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm) 3017 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3018 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm) 3019 } else { 3020 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3021 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3022 } 3023 case ASUBW: 3024 if r == 0 { 3025 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3026 } else { 3027 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 3028 } 3029 } 3030 3031 case 11: // br/bl 3032 v := int32(0) 3033 3034 if p.To.Target() != nil { 3035 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3036 } 3037 3038 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 3039 zRI(op_BRC, 0xF, uint32(v), asm) 3040 } else { 3041 if p.As == ABL { 3042 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 3043 } else { 3044 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 3045 } 3046 if p.To.Sym != nil { 3047 c.addcallreloc(p.To.Sym, p.To.Offset) 3048 } 3049 } 3050 3051 case 12: 3052 r1 := p.To.Reg 3053 d2 := c.vregoff(&p.From) 3054 b2 := p.From.Reg 3055 if b2 == 0 { 3056 b2 = REGSP 3057 } 3058 x2 := p.From.Index 3059 if -DISP20/2 > d2 || d2 >= DISP20/2 { 3060 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3061 if x2 != 0 { 3062 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3063 } 3064 x2 = int16(regtmp(p)) 3065 d2 = 0 3066 } 3067 var opx, opxy uint32 3068 switch p.As { 3069 case AADD: 3070 opxy = op_AG 3071 case AADDC: 3072 opxy = op_ALG 3073 case AADDE: 3074 opxy = op_ALCG 3075 case AADDW: 3076 opx = op_A 3077 opxy = op_AY 3078 case AMULLW: 3079 opx = op_MS 3080 opxy = op_MSY 3081 case AMULLD: 3082 opxy = op_MSG 3083 case ASUB: 3084 opxy = op_SG 3085 case ASUBC: 3086 opxy = op_SLG 3087 case ASUBE: 3088 opxy = op_SLBG 3089 case ASUBW: 3090 opx = op_S 3091 opxy = op_SY 3092 case AAND: 3093 opxy = op_NG 3094 case AANDW: 3095 opx = op_N 3096 opxy = op_NY 3097 case AOR: 3098 opxy = op_OG 3099 case AORW: 3100 opx = op_O 3101 opxy = op_OY 3102 case AXOR: 3103 opxy = op_XG 3104 case AXORW: 3105 opx = op_X 3106 opxy = op_XY 3107 } 3108 if opx != 0 && 0 <= d2 && d2 < DISP12 { 3109 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3110 } else { 3111 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3112 } 3113 3114 case 13: // rotate, followed by operation 3115 r1 := p.To.Reg 3116 r2 := p.RestArgs[2].Reg 3117 i3 := uint8(p.From.Offset) // start 3118 i4 := uint8(p.RestArgs[0].Offset) // end 3119 i5 := uint8(p.RestArgs[1].Offset) // rotate amount 3120 switch p.As { 3121 case ARNSBGT, ARXSBGT, AROSBGT: 3122 i3 |= 0x80 // test-results 3123 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ: 3124 i4 |= 0x80 // zero-remaining-bits 3125 } 3126 var opcode uint32 3127 switch p.As { 3128 case ARNSBG, ARNSBGT: 3129 opcode = op_RNSBG 3130 case ARXSBG, ARXSBGT: 3131 opcode = op_RXSBG 3132 case AROSBG, AROSBGT: 3133 opcode = op_ROSBG 3134 case ARISBG, ARISBGZ: 3135 opcode = op_RISBG 3136 case ARISBGN, ARISBGNZ: 3137 opcode = op_RISBGN 3138 case ARISBHG, ARISBHGZ: 3139 opcode = op_RISBHG 3140 case ARISBLG, ARISBLGZ: 3141 opcode = op_RISBLG 3142 } 3143 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm) 3144 3145 case 15: // br/bl (reg) 3146 r := p.To.Reg 3147 if p.As == ABCL || p.As == ABL { 3148 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 3149 } else { 3150 zRR(op_BCR, uint32(Always), uint32(r), asm) 3151 } 3152 3153 case 16: // conditional branch 3154 v := int32(0) 3155 if p.To.Target() != nil { 3156 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3157 } 3158 mask := uint32(c.branchMask(p)) 3159 if p.To.Sym == nil && int32(int16(v)) == v { 3160 zRI(op_BRC, mask, uint32(v), asm) 3161 } else { 3162 zRIL(_c, op_BRCL, mask, uint32(v), asm) 3163 } 3164 if p.To.Sym != nil { 3165 c.addrilreloc(p.To.Sym, p.To.Offset) 3166 } 3167 3168 case 17: // move on condition 3169 m3 := uint32(c.branchMask(p)) 3170 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3171 3172 case 18: // br/bl reg 3173 if p.As == ABL { 3174 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 3175 } else { 3176 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm) 3177 } 3178 3179 case 19: // mov $sym+n(SB) reg 3180 d := c.vregoff(&p.From) 3181 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 3182 if d&1 != 0 { 3183 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 3184 d -= 1 3185 } 3186 c.addrilreloc(p.From.Sym, d) 3187 3188 case 21: // subtract $constant [reg] reg 3189 v := c.vregoff(&p.From) 3190 r := p.Reg 3191 if r == 0 { 3192 r = p.To.Reg 3193 } 3194 switch p.As { 3195 case ASUB: 3196 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm) 3197 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm) 3198 case ASUBC: 3199 if r != p.To.Reg { 3200 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3201 } 3202 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3203 case ASUBW: 3204 if r != p.To.Reg { 3205 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3206 } 3207 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3208 } 3209 3210 case 22: // add/multiply $constant [reg] reg 3211 v := c.vregoff(&p.From) 3212 r := p.Reg 3213 if r == 0 { 3214 r = p.To.Reg 3215 } 3216 var opri, opril, oprie uint32 3217 switch p.As { 3218 case AADD: 3219 opri = op_AGHI 3220 opril = op_AGFI 3221 oprie = op_AGHIK 3222 case AADDC: 3223 opril = op_ALGFI 3224 oprie = op_ALGHSIK 3225 case AADDW: 3226 opri = op_AHI 3227 opril = op_AFI 3228 oprie = op_AHIK 3229 case AMULLW: 3230 opri = op_MHI 3231 opril = op_MSFI 3232 case AMULLD: 3233 opri = op_MGHI 3234 opril = op_MSGFI 3235 } 3236 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3237 switch p.As { 3238 case AADD, AADDC, AMULLD: 3239 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3240 case AADDW, AMULLW: 3241 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3242 } 3243 r = p.To.Reg 3244 } 3245 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v { 3246 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3247 } else if oprie != 0 && int64(int16(v)) == v { 3248 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3249 } else { 3250 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3251 } 3252 3253 case 23: // 64-bit logical op $constant reg 3254 // TODO(mundaym): merge with case 24. 3255 v := c.vregoff(&p.From) 3256 switch p.As { 3257 default: 3258 c.ctxt.Diag("%v is not supported", p) 3259 case AAND: 3260 if v >= 0 { // needs zero extend 3261 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3262 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm) 3263 } else if int64(int16(v)) == v { 3264 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3265 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3266 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3267 } 3268 case AOR: 3269 if int64(uint32(v)) != v { // needs sign extend 3270 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3271 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm) 3272 } else if int64(uint16(v)) == v { 3273 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3274 } else { 3275 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3276 } 3277 case AXOR: 3278 if int64(uint32(v)) != v { // needs sign extend 3279 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3280 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm) 3281 } else { 3282 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3283 } 3284 } 3285 3286 case 24: // 32-bit logical op $constant reg 3287 v := c.vregoff(&p.From) 3288 switch p.As { 3289 case AANDW: 3290 if uint32(v&0xffff0000) == 0xffff0000 { 3291 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3292 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3293 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3294 } else { 3295 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3296 } 3297 case AORW: 3298 if uint32(v&0xffff0000) == 0 { 3299 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3300 } else if uint32(v&0x0000ffff) == 0 { 3301 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3302 } else { 3303 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3304 } 3305 case AXORW: 3306 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3307 } 3308 3309 case 25: // load on condition (register) 3310 m3 := uint32(c.branchMask(p)) 3311 var opcode uint32 3312 switch p.As { 3313 case ALOCR: 3314 opcode = op_LOCR 3315 case ALOCGR: 3316 opcode = op_LOCGR 3317 } 3318 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3319 3320 case 26: // MOVD $offset(base)(index), reg 3321 v := c.regoff(&p.From) 3322 r := p.From.Reg 3323 if r == 0 { 3324 r = REGSP 3325 } 3326 i := p.From.Index 3327 if v >= 0 && v < DISP12 { 3328 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3329 } else if v >= -DISP20/2 && v < DISP20/2 { 3330 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3331 } else { 3332 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3333 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm) 3334 } 3335 3336 case 31: // dword 3337 wd := uint64(c.vregoff(&p.From)) 3338 *asm = append(*asm, 3339 uint8(wd>>56), 3340 uint8(wd>>48), 3341 uint8(wd>>40), 3342 uint8(wd>>32), 3343 uint8(wd>>24), 3344 uint8(wd>>16), 3345 uint8(wd>>8), 3346 uint8(wd)) 3347 3348 case 32: // float op freg freg 3349 var opcode uint32 3350 switch p.As { 3351 default: 3352 c.ctxt.Diag("invalid opcode") 3353 case AFADD: 3354 opcode = op_ADBR 3355 case AFADDS: 3356 opcode = op_AEBR 3357 case AFDIV: 3358 opcode = op_DDBR 3359 case AFDIVS: 3360 opcode = op_DEBR 3361 case AFMUL: 3362 opcode = op_MDBR 3363 case AFMULS: 3364 opcode = op_MEEBR 3365 case AFSUB: 3366 opcode = op_SDBR 3367 case AFSUBS: 3368 opcode = op_SEBR 3369 } 3370 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3371 3372 case 33: // float op [freg] freg 3373 r := p.From.Reg 3374 if oclass(&p.From) == C_NONE { 3375 r = p.To.Reg 3376 } 3377 var opcode uint32 3378 switch p.As { 3379 default: 3380 case AFABS: 3381 opcode = op_LPDBR 3382 case AFNABS: 3383 opcode = op_LNDBR 3384 case ALPDFR: 3385 opcode = op_LPDFR 3386 case ALNDFR: 3387 opcode = op_LNDFR 3388 case AFNEG: 3389 opcode = op_LCDFR 3390 case AFNEGS: 3391 opcode = op_LCEBR 3392 case ALEDBR: 3393 opcode = op_LEDBR 3394 case ALDEBR: 3395 opcode = op_LDEBR 3396 case AFSQRT: 3397 opcode = op_SQDBR 3398 case AFSQRTS: 3399 opcode = op_SQEBR 3400 } 3401 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3402 3403 case 34: // float multiply-add freg freg freg 3404 var opcode uint32 3405 switch p.As { 3406 default: 3407 c.ctxt.Diag("invalid opcode") 3408 case AFMADD: 3409 opcode = op_MADBR 3410 case AFMADDS: 3411 opcode = op_MAEBR 3412 case AFMSUB: 3413 opcode = op_MSDBR 3414 case AFMSUBS: 3415 opcode = op_MSEBR 3416 } 3417 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3418 3419 case 35: // mov reg mem (no relocation) 3420 d2 := c.regoff(&p.To) 3421 b2 := p.To.Reg 3422 if b2 == 0 { 3423 b2 = REGSP 3424 } 3425 x2 := p.To.Index 3426 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3427 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3428 if x2 != 0 { 3429 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3430 } 3431 x2 = int16(regtmp(p)) 3432 d2 = 0 3433 } 3434 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3435 if op, ok := c.zopstore12(p.As); ok && isU12(d2) { 3436 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3437 } else { 3438 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3439 } 3440 3441 case 36: // mov mem reg (no relocation) 3442 d2 := c.regoff(&p.From) 3443 b2 := p.From.Reg 3444 if b2 == 0 { 3445 b2 = REGSP 3446 } 3447 x2 := p.From.Index 3448 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3449 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3450 if x2 != 0 { 3451 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3452 } 3453 x2 = int16(regtmp(p)) 3454 d2 = 0 3455 } 3456 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3457 if op, ok := c.zopload12(p.As); ok && isU12(d2) { 3458 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3459 } else { 3460 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3461 } 3462 3463 case 40: // word/byte 3464 wd := uint32(c.regoff(&p.From)) 3465 if p.As == AWORD { //WORD 3466 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3467 } else { //BYTE 3468 *asm = append(*asm, uint8(wd)) 3469 } 3470 3471 case 41: // branch on count 3472 r1 := p.From.Reg 3473 ri2 := (p.To.Target().Pc - p.Pc) >> 1 3474 if int64(int16(ri2)) != ri2 { 3475 c.ctxt.Diag("branch target too far away") 3476 } 3477 var opcode uint32 3478 switch p.As { 3479 case ABRCT: 3480 opcode = op_BRCT 3481 case ABRCTG: 3482 opcode = op_BRCTG 3483 } 3484 zRI(opcode, uint32(r1), uint32(ri2), asm) 3485 3486 case 47: // negate [reg] reg 3487 r := p.From.Reg 3488 if r == 0 { 3489 r = p.To.Reg 3490 } 3491 switch p.As { 3492 case ANEG: 3493 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3494 case ANEGW: 3495 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3496 } 3497 3498 case 48: // floating-point round to integer 3499 m3 := c.vregoff(&p.From) 3500 if 0 > m3 || m3 > 7 { 3501 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3502 } 3503 var opcode uint32 3504 switch p.As { 3505 case AFIEBR: 3506 opcode = op_FIEBR 3507 case AFIDBR: 3508 opcode = op_FIDBR 3509 } 3510 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3511 3512 case 49: // copysign 3513 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3514 3515 case 50: // load and test 3516 var opcode uint32 3517 switch p.As { 3518 case ALTEBR: 3519 opcode = op_LTEBR 3520 case ALTDBR: 3521 opcode = op_LTDBR 3522 } 3523 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3524 3525 case 51: // test data class (immediate only) 3526 var opcode uint32 3527 switch p.As { 3528 case ATCEB: 3529 opcode = op_TCEB 3530 case ATCDB: 3531 opcode = op_TCDB 3532 } 3533 d2 := c.regoff(&p.To) 3534 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm) 3535 3536 case 62: // equivalent of Mul64 in math/bits 3537 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3538 3539 case 66: 3540 zRR(op_BCR, uint32(Never), 0, asm) 3541 3542 case 67: // fmov $0 freg 3543 var opcode uint32 3544 switch p.As { 3545 case AFMOVS: 3546 opcode = op_LZER 3547 case AFMOVD: 3548 opcode = op_LZDR 3549 } 3550 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3551 3552 case 68: // movw areg reg 3553 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3554 3555 case 69: // movw reg areg 3556 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3557 3558 case 70: // cmp reg reg 3559 if p.As == ACMPW || p.As == ACMPWU { 3560 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3561 } else { 3562 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3563 } 3564 3565 case 71: // cmp reg $constant 3566 v := c.vregoff(&p.To) 3567 switch p.As { 3568 case ACMP, ACMPW: 3569 if int64(int32(v)) != v { 3570 c.ctxt.Diag("%v overflows an int32", v) 3571 } 3572 case ACMPU, ACMPWU: 3573 if int64(uint32(v)) != v { 3574 c.ctxt.Diag("%v overflows a uint32", v) 3575 } 3576 } 3577 if p.As == ACMP && int64(int16(v)) == v { 3578 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3579 } else if p.As == ACMPW && int64(int16(v)) == v { 3580 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3581 } else { 3582 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3583 } 3584 3585 case 72: // mov $constant mem 3586 v := c.regoff(&p.From) 3587 d := c.regoff(&p.To) 3588 r := p.To.Reg 3589 if p.To.Index != 0 { 3590 c.ctxt.Diag("cannot use index register") 3591 } 3592 if r == 0 { 3593 r = REGSP 3594 } 3595 var opcode uint32 3596 switch p.As { 3597 case AMOVD: 3598 opcode = op_MVGHI 3599 case AMOVW, AMOVWZ: 3600 opcode = op_MVHI 3601 case AMOVH, AMOVHZ: 3602 opcode = op_MVHHI 3603 case AMOVB, AMOVBZ: 3604 opcode = op_MVI 3605 } 3606 if d < 0 || d >= DISP12 { 3607 if r == int16(regtmp(p)) { 3608 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3609 } 3610 if d >= -DISP20/2 && d < DISP20/2 { 3611 if opcode == op_MVI { 3612 opcode = op_MVIY 3613 } else { 3614 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm) 3615 r = int16(regtmp(p)) 3616 d = 0 3617 } 3618 } else { 3619 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm) 3620 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm) 3621 r = int16(regtmp(p)) 3622 d = 0 3623 } 3624 } 3625 switch opcode { 3626 case op_MVI: 3627 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3628 case op_MVIY: 3629 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3630 default: 3631 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3632 } 3633 3634 case 73: //Illegal opcode with SIGTRAP Exception 3635 zE(op_BRRK, asm) 3636 3637 case 74: // mov reg addr (including relocation) 3638 i2 := c.regoff(&p.To) 3639 switch p.As { 3640 case AMOVD: 3641 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3642 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3643 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3644 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3645 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3646 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3647 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3648 adj := uint32(0) // adjustment needed for odd addresses 3649 if i2&1 != 0 { 3650 i2 -= 1 3651 adj = 1 3652 } 3653 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm) 3654 case AFMOVD: 3655 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3656 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3657 case AFMOVS: 3658 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3659 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3660 } 3661 c.addrilreloc(p.To.Sym, int64(i2)) 3662 3663 case 75: // mov addr reg (including relocation) 3664 i2 := c.regoff(&p.From) 3665 switch p.As { 3666 case AMOVD: 3667 if i2&1 != 0 { 3668 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3669 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm) 3670 i2 -= 1 3671 } else { 3672 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3673 } 3674 case AMOVW: 3675 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3676 case AMOVWZ: 3677 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3678 case AMOVH: 3679 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3680 case AMOVHZ: 3681 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3682 case AMOVB, AMOVBZ: 3683 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3684 adj := uint32(0) // adjustment needed for odd addresses 3685 if i2&1 != 0 { 3686 i2 -= 1 3687 adj = 1 3688 } 3689 switch p.As { 3690 case AMOVB: 3691 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3692 case AMOVBZ: 3693 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3694 } 3695 case AFMOVD: 3696 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3697 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3698 case AFMOVS: 3699 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3700 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3701 } 3702 c.addrilreloc(p.From.Sym, int64(i2)) 3703 3704 case 76: // set program mask 3705 zRR(op_SPM, uint32(p.From.Reg), 0, asm) 3706 3707 case 77: // syscall $constant 3708 if p.From.Offset > 255 || p.From.Offset < 1 { 3709 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3710 zE(op_TRAP2, asm) // trap always 3711 } else { 3712 zI(op_SVC, uint32(p.From.Offset), asm) 3713 } 3714 3715 case 78: // undef 3716 // "An instruction consisting entirely of binary 0s is guaranteed 3717 // always to be an illegal instruction." 3718 *asm = append(*asm, 0, 0, 0, 0) 3719 3720 case 79: // compare and swap reg reg reg 3721 v := c.regoff(&p.To) 3722 if v < 0 { 3723 v = 0 3724 } 3725 if p.As == ACS { 3726 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3727 } else if p.As == ACSG { 3728 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3729 } 3730 3731 case 80: // sync 3732 zRR(op_BCR, 14, 0, asm) // fast-BCR-serialization 3733 3734 case 81: // float to fixed and fixed to float moves (no conversion) 3735 switch p.As { 3736 case ALDGR: 3737 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3738 case ALGDR: 3739 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3740 } 3741 3742 case 82: // fixed to float conversion 3743 var opcode uint32 3744 switch p.As { 3745 default: 3746 log.Fatalf("unexpected opcode %v", p.As) 3747 case ACEFBRA: 3748 opcode = op_CEFBRA 3749 case ACDFBRA: 3750 opcode = op_CDFBRA 3751 case ACEGBRA: 3752 opcode = op_CEGBRA 3753 case ACDGBRA: 3754 opcode = op_CDGBRA 3755 case ACELFBR: 3756 opcode = op_CELFBR 3757 case ACDLFBR: 3758 opcode = op_CDLFBR 3759 case ACELGBR: 3760 opcode = op_CELGBR 3761 case ACDLGBR: 3762 opcode = op_CDLGBR 3763 } 3764 // set immediate operand M3 to 0 to use the default BFP rounding mode 3765 // (usually round to nearest, ties to even) 3766 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3767 // M4 is reserved and must be 0 3768 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3769 3770 case 83: // float to fixed conversion 3771 var opcode uint32 3772 switch p.As { 3773 default: 3774 log.Fatalf("unexpected opcode %v", p.As) 3775 case ACFEBRA: 3776 opcode = op_CFEBRA 3777 case ACFDBRA: 3778 opcode = op_CFDBRA 3779 case ACGEBRA: 3780 opcode = op_CGEBRA 3781 case ACGDBRA: 3782 opcode = op_CGDBRA 3783 case ACLFEBR: 3784 opcode = op_CLFEBR 3785 case ACLFDBR: 3786 opcode = op_CLFDBR 3787 case ACLGEBR: 3788 opcode = op_CLGEBR 3789 case ACLGDBR: 3790 opcode = op_CLGDBR 3791 } 3792 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3793 // M4 is reserved and must be 0 3794 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3795 3796 case 84: // storage-and-storage operations $length mem mem 3797 l := c.regoff(&p.From) 3798 if l < 1 || l > 256 { 3799 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3800 } 3801 if p.GetFrom3().Index != 0 || p.To.Index != 0 { 3802 c.ctxt.Diag("cannot use index reg") 3803 } 3804 b1 := p.To.Reg 3805 b2 := p.GetFrom3().Reg 3806 if b1 == 0 { 3807 b1 = REGSP 3808 } 3809 if b2 == 0 { 3810 b2 = REGSP 3811 } 3812 d1 := c.regoff(&p.To) 3813 d2 := c.regoff(p.GetFrom3()) 3814 if d1 < 0 || d1 >= DISP12 { 3815 if b2 == int16(regtmp(p)) { 3816 c.ctxt.Diag("regtmp(p) conflict") 3817 } 3818 if b1 != int16(regtmp(p)) { 3819 zRRE(op_LGR, regtmp(p), uint32(b1), asm) 3820 } 3821 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm) 3822 if d1 == d2 && b1 == b2 { 3823 d2 = 0 3824 b2 = int16(regtmp(p)) 3825 } 3826 d1 = 0 3827 b1 = int16(regtmp(p)) 3828 } 3829 if d2 < 0 || d2 >= DISP12 { 3830 if b1 == REGTMP2 { 3831 c.ctxt.Diag("REGTMP2 conflict") 3832 } 3833 if b2 != REGTMP2 { 3834 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3835 } 3836 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3837 d2 = 0 3838 b2 = REGTMP2 3839 } 3840 var opcode uint32 3841 switch p.As { 3842 default: 3843 c.ctxt.Diag("unexpected opcode %v", p.As) 3844 case AMVC: 3845 opcode = op_MVC 3846 case AMVCIN: 3847 opcode = op_MVCIN 3848 case ACLC: 3849 opcode = op_CLC 3850 // swap operand order for CLC so that it matches CMP 3851 b1, b2 = b2, b1 3852 d1, d2 = d2, d1 3853 case AXC: 3854 opcode = op_XC 3855 case AOC: 3856 opcode = op_OC 3857 case ANC: 3858 opcode = op_NC 3859 } 3860 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3861 3862 case 85: // load address relative long 3863 v := c.regoff(&p.From) 3864 if p.From.Sym == nil { 3865 if (v & 1) != 0 { 3866 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3867 } 3868 } else { 3869 c.addrilreloc(p.From.Sym, int64(v)) 3870 v = 0 3871 } 3872 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3873 3874 case 86: // load address 3875 d := c.vregoff(&p.From) 3876 x := p.From.Index 3877 b := p.From.Reg 3878 if b == 0 { 3879 b = REGSP 3880 } 3881 switch p.As { 3882 case ALA: 3883 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3884 case ALAY: 3885 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3886 } 3887 3888 case 87: // execute relative long 3889 v := c.vregoff(&p.From) 3890 if p.From.Sym == nil { 3891 if v&1 != 0 { 3892 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3893 } 3894 } else { 3895 c.addrilreloc(p.From.Sym, v) 3896 v = 0 3897 } 3898 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3899 3900 case 88: // store clock 3901 var opcode uint32 3902 switch p.As { 3903 case ASTCK: 3904 opcode = op_STCK 3905 case ASTCKC: 3906 opcode = op_STCKC 3907 case ASTCKE: 3908 opcode = op_STCKE 3909 case ASTCKF: 3910 opcode = op_STCKF 3911 } 3912 v := c.vregoff(&p.To) 3913 r := p.To.Reg 3914 if r == 0 { 3915 r = REGSP 3916 } 3917 zS(opcode, uint32(r), uint32(v), asm) 3918 3919 case 89: // compare and branch reg reg 3920 var v int32 3921 if p.To.Target() != nil { 3922 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3923 } 3924 3925 // Some instructions take a mask as the first argument. 3926 r1, r2 := p.From.Reg, p.Reg 3927 if p.From.Type == obj.TYPE_CONST { 3928 r1, r2 = p.Reg, p.RestArgs[0].Reg 3929 } 3930 m3 := uint32(c.branchMask(p)) 3931 3932 var opcode uint32 3933 switch p.As { 3934 case ACRJ: 3935 // COMPARE AND BRANCH RELATIVE (32) 3936 opcode = op_CRJ 3937 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3938 // COMPARE AND BRANCH RELATIVE (64) 3939 opcode = op_CGRJ 3940 case ACLRJ: 3941 // COMPARE LOGICAL AND BRANCH RELATIVE (32) 3942 opcode = op_CLRJ 3943 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3944 // COMPARE LOGICAL AND BRANCH RELATIVE (64) 3945 opcode = op_CLGRJ 3946 } 3947 3948 if int32(int16(v)) != v { 3949 // The branch is too far for one instruction so crack 3950 // `CMPBEQ x, y, target` into: 3951 // 3952 // CMPBNE x, y, 2(PC) 3953 // BR target 3954 // 3955 // Note that the instruction sequence MUST NOT clobber 3956 // the condition code. 3957 m3 ^= 0xe // invert 3-bit mask 3958 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm) 3959 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 3960 } else { 3961 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm) 3962 } 3963 3964 case 90: // compare and branch reg $constant 3965 var v int32 3966 if p.To.Target() != nil { 3967 v = int32((p.To.Target().Pc - p.Pc) >> 1) 3968 } 3969 3970 // Some instructions take a mask as the first argument. 3971 r1, i2 := p.From.Reg, p.RestArgs[0].Offset 3972 if p.From.Type == obj.TYPE_CONST { 3973 r1 = p.Reg 3974 } 3975 m3 := uint32(c.branchMask(p)) 3976 3977 var opcode uint32 3978 switch p.As { 3979 case ACIJ: 3980 opcode = op_CIJ 3981 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3982 opcode = op_CGIJ 3983 case ACLIJ: 3984 opcode = op_CLIJ 3985 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3986 opcode = op_CLGIJ 3987 } 3988 if int32(int16(v)) != v { 3989 // The branch is too far for one instruction so crack 3990 // `CMPBEQ x, $0, target` into: 3991 // 3992 // CMPBNE x, $0, 2(PC) 3993 // BR target 3994 // 3995 // Note that the instruction sequence MUST NOT clobber 3996 // the condition code. 3997 m3 ^= 0xe // invert 3-bit mask 3998 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm) 3999 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 4000 } else { 4001 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm) 4002 } 4003 4004 case 91: // test under mask (immediate) 4005 var opcode uint32 4006 switch p.As { 4007 case ATMHH: 4008 opcode = op_TMHH 4009 case ATMHL: 4010 opcode = op_TMHL 4011 case ATMLH: 4012 opcode = op_TMLH 4013 case ATMLL: 4014 opcode = op_TMLL 4015 } 4016 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm) 4017 4018 case 92: // insert program mask 4019 zRRE(op_IPM, uint32(p.From.Reg), 0, asm) 4020 4021 case 93: // GOT lookup 4022 v := c.vregoff(&p.To) 4023 if v != 0 { 4024 c.ctxt.Diag("invalid offset against GOT slot %v", p) 4025 } 4026 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 4027 rel := obj.Addrel(c.cursym) 4028 rel.Off = int32(c.pc + 2) 4029 rel.Siz = 4 4030 rel.Sym = p.From.Sym 4031 rel.Type = objabi.R_GOTPCREL 4032 rel.Add = 2 + int64(rel.Siz) 4033 4034 case 94: // TLS local exec model 4035 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm) 4036 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 4037 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 4038 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 4039 rel := obj.Addrel(c.cursym) 4040 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 4041 rel.Siz = 8 4042 rel.Sym = p.From.Sym 4043 rel.Type = objabi.R_TLS_LE 4044 rel.Add = 0 4045 4046 case 95: // TLS initial exec model 4047 // Assembly | Relocation symbol | Done Here? 4048 // -------------------------------------------------------------- 4049 // ear %r11, %a0 | | 4050 // sllg %r11, %r11, 32 | | 4051 // ear %r11, %a1 | | 4052 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 4053 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 4054 // la %r10, 0(%r10, %r11) | | 4055 // -------------------------------------------------------------- 4056 4057 // R_390_TLS_IEENT 4058 zRIL(_b, op_LARL, regtmp(p), 0, asm) 4059 ieent := obj.Addrel(c.cursym) 4060 ieent.Off = int32(c.pc + 2) 4061 ieent.Siz = 4 4062 ieent.Sym = p.From.Sym 4063 ieent.Type = objabi.R_TLS_IE 4064 ieent.Add = 2 + int64(ieent.Siz) 4065 4066 // R_390_TLS_LOAD 4067 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 4068 // TODO(mundaym): add R_390_TLS_LOAD relocation here 4069 // not strictly required but might allow the linker to optimize 4070 4071 case 96: // clear macro 4072 length := c.vregoff(&p.From) 4073 offset := c.vregoff(&p.To) 4074 reg := p.To.Reg 4075 if reg == 0 { 4076 reg = REGSP 4077 } 4078 if length <= 0 { 4079 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 4080 } 4081 for length > 0 { 4082 if offset < 0 || offset >= DISP12 { 4083 if offset >= -DISP20/2 && offset < DISP20/2 { 4084 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm) 4085 } else { 4086 if reg != int16(regtmp(p)) { 4087 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4088 } 4089 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4090 } 4091 reg = int16(regtmp(p)) 4092 offset = 0 4093 } 4094 size := length 4095 if size > 256 { 4096 size = 256 4097 } 4098 4099 switch size { 4100 case 1: 4101 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 4102 case 2: 4103 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 4104 case 4: 4105 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 4106 case 8: 4107 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 4108 default: 4109 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 4110 } 4111 4112 length -= size 4113 offset += size 4114 } 4115 4116 case 97: // store multiple 4117 rstart := p.From.Reg 4118 rend := p.Reg 4119 offset := c.regoff(&p.To) 4120 reg := p.To.Reg 4121 if reg == 0 { 4122 reg = REGSP 4123 } 4124 if offset < -DISP20/2 || offset >= DISP20/2 { 4125 if reg != int16(regtmp(p)) { 4126 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4127 } 4128 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4129 reg = int16(regtmp(p)) 4130 offset = 0 4131 } 4132 switch p.As { 4133 case ASTMY: 4134 if offset >= 0 && offset < DISP12 { 4135 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4136 } else { 4137 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4138 } 4139 case ASTMG: 4140 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4141 } 4142 4143 case 98: // load multiple 4144 rstart := p.Reg 4145 rend := p.To.Reg 4146 offset := c.regoff(&p.From) 4147 reg := p.From.Reg 4148 if reg == 0 { 4149 reg = REGSP 4150 } 4151 if offset < -DISP20/2 || offset >= DISP20/2 { 4152 if reg != int16(regtmp(p)) { 4153 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4154 } 4155 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4156 reg = int16(regtmp(p)) 4157 offset = 0 4158 } 4159 switch p.As { 4160 case ALMY: 4161 if offset >= 0 && offset < DISP12 { 4162 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4163 } else { 4164 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4165 } 4166 case ALMG: 4167 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4168 } 4169 4170 case 99: // interlocked load and op 4171 if p.To.Index != 0 { 4172 c.ctxt.Diag("cannot use indexed address") 4173 } 4174 offset := c.regoff(&p.To) 4175 if offset < -DISP20/2 || offset >= DISP20/2 { 4176 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 4177 } 4178 var opcode uint32 4179 switch p.As { 4180 case ALAA: 4181 opcode = op_LAA 4182 case ALAAG: 4183 opcode = op_LAAG 4184 case ALAAL: 4185 opcode = op_LAAL 4186 case ALAALG: 4187 opcode = op_LAALG 4188 case ALAN: 4189 opcode = op_LAN 4190 case ALANG: 4191 opcode = op_LANG 4192 case ALAX: 4193 opcode = op_LAX 4194 case ALAXG: 4195 opcode = op_LAXG 4196 case ALAO: 4197 opcode = op_LAO 4198 case ALAOG: 4199 opcode = op_LAOG 4200 } 4201 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 4202 4203 case 100: // VRX STORE 4204 op, m3, _ := vop(p.As) 4205 v1 := p.From.Reg 4206 if p.Reg != 0 { 4207 m3 = uint32(c.vregoff(&p.From)) 4208 v1 = p.Reg 4209 } 4210 b2 := p.To.Reg 4211 if b2 == 0 { 4212 b2 = REGSP 4213 } 4214 d2 := uint32(c.vregoff(&p.To)) 4215 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4216 4217 case 101: // VRX LOAD 4218 op, m3, _ := vop(p.As) 4219 src := &p.From 4220 if p.GetFrom3() != nil { 4221 m3 = uint32(c.vregoff(&p.From)) 4222 src = p.GetFrom3() 4223 } 4224 b2 := src.Reg 4225 if b2 == 0 { 4226 b2 = REGSP 4227 } 4228 d2 := uint32(c.vregoff(src)) 4229 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 4230 4231 case 102: // VRV SCATTER 4232 op, _, _ := vop(p.As) 4233 m3 := uint32(c.vregoff(&p.From)) 4234 b2 := p.To.Reg 4235 if b2 == 0 { 4236 b2 = REGSP 4237 } 4238 d2 := uint32(c.vregoff(&p.To)) 4239 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4240 4241 case 103: // VRV GATHER 4242 op, _, _ := vop(p.As) 4243 m3 := uint32(c.vregoff(&p.From)) 4244 b2 := p.GetFrom3().Reg 4245 if b2 == 0 { 4246 b2 = REGSP 4247 } 4248 d2 := uint32(c.vregoff(p.GetFrom3())) 4249 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm) 4250 4251 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 4252 op, m4, _ := vop(p.As) 4253 fr := p.Reg 4254 if fr == 0 { 4255 fr = p.To.Reg 4256 } 4257 bits := uint32(c.vregoff(&p.From)) 4258 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 4259 4260 case 105: // VRS STORE MULTIPLE 4261 op, _, _ := vop(p.As) 4262 offset := uint32(c.vregoff(&p.To)) 4263 reg := p.To.Reg 4264 if reg == 0 { 4265 reg = REGSP 4266 } 4267 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 4268 4269 case 106: // VRS LOAD MULTIPLE 4270 op, _, _ := vop(p.As) 4271 offset := uint32(c.vregoff(&p.From)) 4272 reg := p.From.Reg 4273 if reg == 0 { 4274 reg = REGSP 4275 } 4276 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 4277 4278 case 107: // VRS STORE WITH LENGTH 4279 op, _, _ := vop(p.As) 4280 offset := uint32(c.vregoff(&p.To)) 4281 reg := p.To.Reg 4282 if reg == 0 { 4283 reg = REGSP 4284 } 4285 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4286 4287 case 108: // VRS LOAD WITH LENGTH 4288 op, _, _ := vop(p.As) 4289 offset := uint32(c.vregoff(p.GetFrom3())) 4290 reg := p.GetFrom3().Reg 4291 if reg == 0 { 4292 reg = REGSP 4293 } 4294 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4295 4296 case 109: // VRI-a 4297 op, m3, _ := vop(p.As) 4298 i2 := uint32(c.vregoff(&p.From)) 4299 if p.GetFrom3() != nil { 4300 m3 = uint32(c.vregoff(&p.From)) 4301 i2 = uint32(c.vregoff(p.GetFrom3())) 4302 } 4303 switch p.As { 4304 case AVZERO: 4305 i2 = 0 4306 case AVONE: 4307 i2 = 0xffff 4308 } 4309 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 4310 4311 case 110: 4312 op, m4, _ := vop(p.As) 4313 i2 := uint32(c.vregoff(&p.From)) 4314 i3 := uint32(c.vregoff(p.GetFrom3())) 4315 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4316 4317 case 111: 4318 op, m4, _ := vop(p.As) 4319 i2 := uint32(c.vregoff(&p.From)) 4320 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4321 4322 case 112: 4323 op, m5, _ := vop(p.As) 4324 i4 := uint32(c.vregoff(&p.From)) 4325 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm) 4326 4327 case 113: 4328 op, m4, _ := vop(p.As) 4329 m5 := singleElementMask(p.As) 4330 i3 := uint32(c.vregoff(&p.From)) 4331 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4332 4333 case 114: // VRR-a 4334 op, m3, m5 := vop(p.As) 4335 m4 := singleElementMask(p.As) 4336 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4337 4338 case 115: // VRR-a COMPARE 4339 op, m3, m5 := vop(p.As) 4340 m4 := singleElementMask(p.As) 4341 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4342 4343 case 117: // VRR-b 4344 op, m4, m5 := vop(p.As) 4345 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4346 4347 case 118: // VRR-c 4348 op, m4, m6 := vop(p.As) 4349 m5 := singleElementMask(p.As) 4350 v3 := p.Reg 4351 if v3 == 0 { 4352 v3 = p.To.Reg 4353 } 4354 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4355 4356 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4357 op, m4, m6 := vop(p.As) 4358 m5 := singleElementMask(p.As) 4359 v2 := p.Reg 4360 if v2 == 0 { 4361 v2 = p.To.Reg 4362 } 4363 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4364 4365 case 120: // VRR-d 4366 op, m6, _ := vop(p.As) 4367 m5 := singleElementMask(p.As) 4368 v1 := uint32(p.To.Reg) 4369 v2 := uint32(p.From.Reg) 4370 v3 := uint32(p.Reg) 4371 v4 := uint32(p.GetFrom3().Reg) 4372 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4373 4374 case 121: // VRR-e 4375 op, m6, _ := vop(p.As) 4376 m5 := singleElementMask(p.As) 4377 v1 := uint32(p.To.Reg) 4378 v2 := uint32(p.From.Reg) 4379 v3 := uint32(p.Reg) 4380 v4 := uint32(p.GetFrom3().Reg) 4381 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4382 4383 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4384 op, _, _ := vop(p.As) 4385 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4386 4387 case 123: // VPDI $m4, V2, V3, V1 4388 op, _, _ := vop(p.As) 4389 m4 := c.regoff(&p.From) 4390 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm) 4391 4392 case 124: 4393 var opcode uint32 4394 switch p.As { 4395 default: 4396 c.ctxt.Diag("unexpected opcode %v", p.As) 4397 case AKM, AKMC, AKLMD: 4398 if p.From.Reg == REG_R0 { 4399 c.ctxt.Diag("input must not be R0 in %v", p) 4400 } 4401 if p.From.Reg&1 != 0 { 4402 c.ctxt.Diag("input must be even register in %v", p) 4403 } 4404 if p.To.Reg == REG_R0 { 4405 c.ctxt.Diag("second argument must not be R0 in %v", p) 4406 } 4407 if p.To.Reg&1 != 0 { 4408 c.ctxt.Diag("second argument must be even register in %v", p) 4409 } 4410 if p.As == AKM { 4411 opcode = op_KM 4412 } else if p.As == AKMC { 4413 opcode = op_KMC 4414 } else { 4415 opcode = op_KLMD 4416 } 4417 case AKIMD: 4418 if p.To.Reg == REG_R0 { 4419 c.ctxt.Diag("second argument must not be R0 in %v", p) 4420 } 4421 if p.To.Reg&1 != 0 { 4422 c.ctxt.Diag("second argument must be even register in %v", p) 4423 } 4424 opcode = op_KIMD 4425 } 4426 zRRE(opcode, uint32(p.From.Reg), uint32(p.To.Reg), asm) 4427 4428 case 125: // KDSA sign and verify 4429 if p.To.Reg == REG_R0 { 4430 c.ctxt.Diag("second argument must not be R0 in %v", p) 4431 } 4432 if p.To.Reg&1 != 0 { 4433 c.ctxt.Diag("second argument must be an even register in %v", p) 4434 } 4435 zRRE(op_KDSA, uint32(p.From.Reg), uint32(p.To.Reg), asm) 4436 4437 case 126: // KMA and KMCTR - CIPHER MESSAGE WITH AUTHENTICATION; CIPHER MESSAGE WITH COUNTER 4438 var opcode uint32 4439 switch p.As { 4440 default: 4441 c.ctxt.Diag("unexpected opcode %v", p.As) 4442 case AKMA, AKMCTR: 4443 if p.From.Reg == REG_R0 { 4444 c.ctxt.Diag("input argument must not be R0 in %v", p) 4445 } 4446 if p.From.Reg&1 != 0 { 4447 c.ctxt.Diag("input argument must be even register in %v", p) 4448 } 4449 if p.To.Reg == REG_R0 { 4450 c.ctxt.Diag("output argument must not be R0 in %v", p) 4451 } 4452 if p.To.Reg&1 != 0 { 4453 c.ctxt.Diag("output argument must be an even register in %v", p) 4454 } 4455 if p.Reg == REG_R0 { 4456 c.ctxt.Diag("third argument must not be R0 in %v", p) 4457 } 4458 if p.Reg&1 != 0 { 4459 c.ctxt.Diag("third argument must be even register in %v", p) 4460 } 4461 if p.As == AKMA { 4462 opcode = op_KMA 4463 } else if p.As == AKMCTR { 4464 opcode = op_KMCTR 4465 } 4466 } 4467 zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm) 4468 } 4469} 4470 4471func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4472 c.instoffset = 0 4473 if a != nil { 4474 c.aclass(a) 4475 } 4476 return c.instoffset 4477} 4478 4479func (c *ctxtz) regoff(a *obj.Addr) int32 { 4480 return int32(c.vregoff(a)) 4481} 4482 4483// find if the displacement is within 12 bit. 4484func isU12(displacement int32) bool { 4485 return displacement >= 0 && displacement < DISP12 4486} 4487 4488// zopload12 returns the RX op with 12 bit displacement for the given load. 4489func (c *ctxtz) zopload12(a obj.As) (uint32, bool) { 4490 switch a { 4491 case AFMOVD: 4492 return op_LD, true 4493 case AFMOVS: 4494 return op_LE, true 4495 } 4496 return 0, false 4497} 4498 4499// zopload returns the RXY op for the given load. 4500func (c *ctxtz) zopload(a obj.As) uint32 { 4501 switch a { 4502 // fixed point load 4503 case AMOVD: 4504 return op_LG 4505 case AMOVW: 4506 return op_LGF 4507 case AMOVWZ: 4508 return op_LLGF 4509 case AMOVH: 4510 return op_LGH 4511 case AMOVHZ: 4512 return op_LLGH 4513 case AMOVB: 4514 return op_LGB 4515 case AMOVBZ: 4516 return op_LLGC 4517 4518 // floating point load 4519 case AFMOVD: 4520 return op_LDY 4521 case AFMOVS: 4522 return op_LEY 4523 4524 // byte reversed load 4525 case AMOVDBR: 4526 return op_LRVG 4527 case AMOVWBR: 4528 return op_LRV 4529 case AMOVHBR: 4530 return op_LRVH 4531 } 4532 4533 c.ctxt.Diag("unknown store opcode %v", a) 4534 return 0 4535} 4536 4537// zopstore12 returns the RX op with 12 bit displacement for the given store. 4538func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) { 4539 switch a { 4540 case AFMOVD: 4541 return op_STD, true 4542 case AFMOVS: 4543 return op_STE, true 4544 case AMOVW, AMOVWZ: 4545 return op_ST, true 4546 case AMOVH, AMOVHZ: 4547 return op_STH, true 4548 case AMOVB, AMOVBZ: 4549 return op_STC, true 4550 } 4551 return 0, false 4552} 4553 4554// zopstore returns the RXY op for the given store. 4555func (c *ctxtz) zopstore(a obj.As) uint32 { 4556 switch a { 4557 // fixed point store 4558 case AMOVD: 4559 return op_STG 4560 case AMOVW, AMOVWZ: 4561 return op_STY 4562 case AMOVH, AMOVHZ: 4563 return op_STHY 4564 case AMOVB, AMOVBZ: 4565 return op_STCY 4566 4567 // floating point store 4568 case AFMOVD: 4569 return op_STDY 4570 case AFMOVS: 4571 return op_STEY 4572 4573 // byte reversed store 4574 case AMOVDBR: 4575 return op_STRVG 4576 case AMOVWBR: 4577 return op_STRV 4578 case AMOVHBR: 4579 return op_STRVH 4580 } 4581 4582 c.ctxt.Diag("unknown store opcode %v", a) 4583 return 0 4584} 4585 4586// zoprre returns the RRE op for the given a. 4587func (c *ctxtz) zoprre(a obj.As) uint32 { 4588 switch a { 4589 case ACMP: 4590 return op_CGR 4591 case ACMPU: 4592 return op_CLGR 4593 case AFCMPO: //ordered 4594 return op_KDBR 4595 case AFCMPU: //unordered 4596 return op_CDBR 4597 case ACEBR: 4598 return op_CEBR 4599 } 4600 c.ctxt.Diag("unknown rre opcode %v", a) 4601 return 0 4602} 4603 4604// zoprr returns the RR op for the given a. 4605func (c *ctxtz) zoprr(a obj.As) uint32 { 4606 switch a { 4607 case ACMPW: 4608 return op_CR 4609 case ACMPWU: 4610 return op_CLR 4611 } 4612 c.ctxt.Diag("unknown rr opcode %v", a) 4613 return 0 4614} 4615 4616// zopril returns the RIL op for the given a. 4617func (c *ctxtz) zopril(a obj.As) uint32 { 4618 switch a { 4619 case ACMP: 4620 return op_CGFI 4621 case ACMPU: 4622 return op_CLGFI 4623 case ACMPW: 4624 return op_CFI 4625 case ACMPWU: 4626 return op_CLFI 4627 } 4628 c.ctxt.Diag("unknown ril opcode %v", a) 4629 return 0 4630} 4631 4632// z instructions sizes 4633const ( 4634 sizeE = 2 4635 sizeI = 2 4636 sizeIE = 4 4637 sizeMII = 6 4638 sizeRI = 4 4639 sizeRI1 = 4 4640 sizeRI2 = 4 4641 sizeRI3 = 4 4642 sizeRIE = 6 4643 sizeRIE1 = 6 4644 sizeRIE2 = 6 4645 sizeRIE3 = 6 4646 sizeRIE4 = 6 4647 sizeRIE5 = 6 4648 sizeRIE6 = 6 4649 sizeRIL = 6 4650 sizeRIL1 = 6 4651 sizeRIL2 = 6 4652 sizeRIL3 = 6 4653 sizeRIS = 6 4654 sizeRR = 2 4655 sizeRRD = 4 4656 sizeRRE = 4 4657 sizeRRF = 4 4658 sizeRRF1 = 4 4659 sizeRRF2 = 4 4660 sizeRRF3 = 4 4661 sizeRRF4 = 4 4662 sizeRRF5 = 4 4663 sizeRRR = 2 4664 sizeRRS = 6 4665 sizeRS = 4 4666 sizeRS1 = 4 4667 sizeRS2 = 4 4668 sizeRSI = 4 4669 sizeRSL = 6 4670 sizeRSY = 6 4671 sizeRSY1 = 6 4672 sizeRSY2 = 6 4673 sizeRX = 4 4674 sizeRX1 = 4 4675 sizeRX2 = 4 4676 sizeRXE = 6 4677 sizeRXF = 6 4678 sizeRXY = 6 4679 sizeRXY1 = 6 4680 sizeRXY2 = 6 4681 sizeS = 4 4682 sizeSI = 4 4683 sizeSIL = 6 4684 sizeSIY = 6 4685 sizeSMI = 6 4686 sizeSS = 6 4687 sizeSS1 = 6 4688 sizeSS2 = 6 4689 sizeSS3 = 6 4690 sizeSS4 = 6 4691 sizeSS5 = 6 4692 sizeSS6 = 6 4693 sizeSSE = 6 4694 sizeSSF = 6 4695) 4696 4697// instruction format variations 4698type form int 4699 4700const ( 4701 _a form = iota 4702 _b 4703 _c 4704 _d 4705 _e 4706 _f 4707) 4708 4709func zE(op uint32, asm *[]byte) { 4710 *asm = append(*asm, uint8(op>>8), uint8(op)) 4711} 4712 4713func zI(op, i1 uint32, asm *[]byte) { 4714 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4715} 4716 4717func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4718 *asm = append(*asm, 4719 uint8(op>>8), 4720 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4721 uint8(ri2), 4722 uint8(ri3>>16), 4723 uint8(ri3>>8), 4724 uint8(ri3)) 4725} 4726 4727func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4728 *asm = append(*asm, 4729 uint8(op>>8), 4730 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4731 uint8(i2_ri2>>8), 4732 uint8(i2_ri2)) 4733} 4734 4735// Expected argument values for the instruction formats. 4736// 4737// Format a1 a2 a3 a4 a5 a6 a7 4738// ------------------------------------ 4739// a r1, 0, i2, 0, 0, m3, 0 4740// b r1, r2, ri4, 0, 0, m3, 0 4741// c r1, m3, ri4, 0, 0, 0, i2 4742// d r1, r3, i2, 0, 0, 0, 0 4743// e r1, r3, ri2, 0, 0, 0, 0 4744// f r1, r2, 0, i3, i4, 0, i5 4745// g r1, m3, i2, 0, 0, 0, 0 4746func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4747 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4748 4749 switch f { 4750 default: 4751 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4752 case _f: 4753 *asm = append(*asm, uint8(i3), uint8(i4)) 4754 } 4755 4756 switch f { 4757 case _a, _b: 4758 *asm = append(*asm, uint8(m3)<<4) 4759 default: 4760 *asm = append(*asm, uint8(i2_i5)) 4761 } 4762 4763 *asm = append(*asm, uint8(op)) 4764} 4765 4766func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4767 if f == _a || f == _b { 4768 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4769 } 4770 *asm = append(*asm, 4771 uint8(op>>8), 4772 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4773 uint8(i2_ri2>>24), 4774 uint8(i2_ri2>>16), 4775 uint8(i2_ri2>>8), 4776 uint8(i2_ri2)) 4777} 4778 4779func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4780 *asm = append(*asm, 4781 uint8(op>>8), 4782 (uint8(r1)<<4)|uint8(m3&0x0F), 4783 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4784 uint8(d4), 4785 uint8(i2), 4786 uint8(op)) 4787} 4788 4789func zRR(op, r1, r2 uint32, asm *[]byte) { 4790 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4791} 4792 4793func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4794 *asm = append(*asm, 4795 uint8(op>>8), 4796 uint8(op), 4797 uint8(r1)<<4, 4798 (uint8(r3)<<4)|uint8(r2&0x0F)) 4799} 4800 4801func zRRE(op, r1, r2 uint32, asm *[]byte) { 4802 *asm = append(*asm, 4803 uint8(op>>8), 4804 uint8(op), 4805 0, 4806 (uint8(r1)<<4)|uint8(r2&0x0F)) 4807} 4808 4809func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4810 *asm = append(*asm, 4811 uint8(op>>8), 4812 uint8(op), 4813 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4814 (uint8(r1)<<4)|uint8(r2&0x0F)) 4815} 4816 4817func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4818 *asm = append(*asm, 4819 uint8(op>>8), 4820 (uint8(r1)<<4)|uint8(r2&0x0F), 4821 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4822 uint8(d4), 4823 uint8(m3)<<4, 4824 uint8(op)) 4825} 4826 4827func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4828 *asm = append(*asm, 4829 uint8(op>>8), 4830 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4831 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4832 uint8(d2)) 4833} 4834 4835func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4836 *asm = append(*asm, 4837 uint8(op>>8), 4838 (uint8(r1)<<4)|uint8(r3&0x0F), 4839 uint8(ri2>>8), 4840 uint8(ri2)) 4841} 4842 4843func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4844 *asm = append(*asm, 4845 uint8(op>>8), 4846 uint8(l1), 4847 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4848 uint8(d2), 4849 uint8(op)) 4850} 4851 4852func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4853 dl2 := uint16(d2) & 0x0FFF 4854 *asm = append(*asm, 4855 uint8(op>>8), 4856 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4857 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4858 uint8(dl2), 4859 uint8(d2>>12), 4860 uint8(op)) 4861} 4862 4863func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4864 *asm = append(*asm, 4865 uint8(op>>8), 4866 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4867 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4868 uint8(d2)) 4869} 4870 4871func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4872 *asm = append(*asm, 4873 uint8(op>>8), 4874 (uint8(r1)<<4)|uint8(x2&0x0F), 4875 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4876 uint8(d2), 4877 uint8(m3)<<4, 4878 uint8(op)) 4879} 4880 4881func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4882 *asm = append(*asm, 4883 uint8(op>>8), 4884 (uint8(r3)<<4)|uint8(x2&0x0F), 4885 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4886 uint8(d2), 4887 uint8(m1)<<4, 4888 uint8(op)) 4889} 4890 4891func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4892 dl2 := uint16(d2) & 0x0FFF 4893 *asm = append(*asm, 4894 uint8(op>>8), 4895 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4896 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4897 uint8(dl2), 4898 uint8(d2>>12), 4899 uint8(op)) 4900} 4901 4902func zS(op, b2, d2 uint32, asm *[]byte) { 4903 *asm = append(*asm, 4904 uint8(op>>8), 4905 uint8(op), 4906 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4907 uint8(d2)) 4908} 4909 4910func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4911 *asm = append(*asm, 4912 uint8(op>>8), 4913 uint8(i2), 4914 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4915 uint8(d1)) 4916} 4917 4918func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4919 *asm = append(*asm, 4920 uint8(op>>8), 4921 uint8(op), 4922 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4923 uint8(d1), 4924 uint8(i2>>8), 4925 uint8(i2)) 4926} 4927 4928func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4929 dl1 := uint16(d1) & 0x0FFF 4930 *asm = append(*asm, 4931 uint8(op>>8), 4932 uint8(i2), 4933 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4934 uint8(dl1), 4935 uint8(d1>>12), 4936 uint8(op)) 4937} 4938 4939func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4940 *asm = append(*asm, 4941 uint8(op>>8), 4942 uint8(m1)<<4, 4943 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4944 uint8(d3), 4945 uint8(ri2>>8), 4946 uint8(ri2)) 4947} 4948 4949// Expected argument values for the instruction formats. 4950// 4951// Format a1 a2 a3 a4 a5 a6 4952// ------------------------------- 4953// a l1, 0, b1, d1, b2, d2 4954// b l1, l2, b1, d1, b2, d2 4955// c l1, i3, b1, d1, b2, d2 4956// d r1, r3, b1, d1, b2, d2 4957// e r1, r3, b2, d2, b4, d4 4958// f 0, l2, b1, d1, b2, d2 4959func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4960 *asm = append(*asm, uint8(op>>8)) 4961 4962 switch f { 4963 case _a: 4964 *asm = append(*asm, uint8(l1_r1)) 4965 case _b, _c, _d, _e: 4966 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4967 case _f: 4968 *asm = append(*asm, uint8(l2_i3_r3)) 4969 } 4970 4971 *asm = append(*asm, 4972 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4973 uint8(d1_d2), 4974 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4975 uint8(d2_d4)) 4976} 4977 4978func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4979 *asm = append(*asm, 4980 uint8(op>>8), 4981 uint8(op), 4982 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4983 uint8(d1), 4984 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4985 uint8(d2)) 4986} 4987 4988func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4989 *asm = append(*asm, 4990 uint8(op>>8), 4991 (uint8(r3)<<4)|(uint8(op)&0x0F), 4992 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4993 uint8(d1), 4994 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4995 uint8(d2)) 4996} 4997 4998func rxb(va, vb, vc, vd uint32) uint8 { 4999 mask := uint8(0) 5000 if va >= REG_V16 && va <= REG_V31 { 5001 mask |= 0x8 5002 } 5003 if vb >= REG_V16 && vb <= REG_V31 { 5004 mask |= 0x4 5005 } 5006 if vc >= REG_V16 && vc <= REG_V31 { 5007 mask |= 0x2 5008 } 5009 if vd >= REG_V16 && vd <= REG_V31 { 5010 mask |= 0x1 5011 } 5012 return mask 5013} 5014 5015func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 5016 *asm = append(*asm, 5017 uint8(op>>8), 5018 (uint8(v1)<<4)|(uint8(x2)&0xf), 5019 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 5020 uint8(d2), 5021 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 5022 uint8(op)) 5023} 5024 5025func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 5026 *asm = append(*asm, 5027 uint8(op>>8), 5028 (uint8(v1)<<4)|(uint8(v2)&0xf), 5029 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 5030 uint8(d2), 5031 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 5032 uint8(op)) 5033} 5034 5035func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 5036 *asm = append(*asm, 5037 uint8(op>>8), 5038 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 5039 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 5040 uint8(d2), 5041 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 5042 uint8(op)) 5043} 5044 5045func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 5046 *asm = append(*asm, 5047 uint8(op>>8), 5048 (uint8(v1)<<4)|(uint8(v2)&0xf), 5049 0, 5050 (uint8(m5)<<4)|(uint8(m4)&0xf), 5051 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 5052 uint8(op)) 5053} 5054 5055func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 5056 *asm = append(*asm, 5057 uint8(op>>8), 5058 (uint8(v1)<<4)|(uint8(v2)&0xf), 5059 uint8(v3)<<4, 5060 uint8(m5)<<4, 5061 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 5062 uint8(op)) 5063} 5064 5065func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 5066 *asm = append(*asm, 5067 uint8(op>>8), 5068 (uint8(v1)<<4)|(uint8(v2)&0xf), 5069 uint8(v3)<<4, 5070 (uint8(m6)<<4)|(uint8(m5)&0xf), 5071 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 5072 uint8(op)) 5073} 5074 5075func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 5076 *asm = append(*asm, 5077 uint8(op>>8), 5078 (uint8(v1)<<4)|(uint8(v2)&0xf), 5079 (uint8(v3)<<4)|(uint8(m5)&0xf), 5080 uint8(m6)<<4, 5081 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 5082 uint8(op)) 5083} 5084 5085func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 5086 *asm = append(*asm, 5087 uint8(op>>8), 5088 (uint8(v1)<<4)|(uint8(v2)&0xf), 5089 (uint8(v3)<<4)|(uint8(m6)&0xf), 5090 uint8(m5), 5091 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 5092 uint8(op)) 5093} 5094 5095func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 5096 *asm = append(*asm, 5097 uint8(op>>8), 5098 (uint8(v1)<<4)|(uint8(r2)&0xf), 5099 uint8(r3)<<4, 5100 0, 5101 rxb(v1, 0, 0, 0), 5102 uint8(op)) 5103} 5104 5105func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 5106 *asm = append(*asm, 5107 uint8(op>>8), 5108 uint8(v1)<<4, 5109 uint8(i2>>8), 5110 uint8(i2), 5111 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 5112 uint8(op)) 5113} 5114 5115func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 5116 *asm = append(*asm, 5117 uint8(op>>8), 5118 uint8(v1)<<4, 5119 uint8(i2), 5120 uint8(i3), 5121 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 5122 uint8(op)) 5123} 5124 5125func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 5126 *asm = append(*asm, 5127 uint8(op>>8), 5128 (uint8(v1)<<4)|(uint8(v3)&0xf), 5129 uint8(i2>>8), 5130 uint8(i2), 5131 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 5132 uint8(op)) 5133} 5134 5135func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 5136 *asm = append(*asm, 5137 uint8(op>>8), 5138 (uint8(v1)<<4)|(uint8(v2)&0xf), 5139 uint8(v3)<<4, 5140 uint8(i4), 5141 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 5142 uint8(op)) 5143} 5144 5145func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 5146 *asm = append(*asm, 5147 uint8(op>>8), 5148 (uint8(v1)<<4)|(uint8(v2)&0xf), 5149 uint8(i3>>4), 5150 (uint8(i3)<<4)|(uint8(m5)&0xf), 5151 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 5152 uint8(op)) 5153} 5154