1 /* 2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef _cl_fermi_compute_b_h_ 24 #define _cl_fermi_compute_b_h_ 25 26 /* AUTO GENERATED FILE -- DO NOT EDIT */ 27 /* Command: ../../class/bin/sw_header.pl fermi_compute_b */ 28 29 #include "nvtypes.h" 30 31 #define FERMI_COMPUTE_B 0x91C0 32 33 #define NV91C0_SET_OBJECT 0x0000 34 #define NV91C0_SET_OBJECT_CLASS_ID 15:0 35 #define NV91C0_SET_OBJECT_ENGINE_ID 20:16 36 37 #define NV91C0_NO_OPERATION 0x0100 38 #define NV91C0_NO_OPERATION_V 31:0 39 40 #define NV91C0_SET_NOTIFY_A 0x0104 41 #define NV91C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 42 43 #define NV91C0_SET_NOTIFY_B 0x0108 44 #define NV91C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 45 46 #define NV91C0_NOTIFY 0x010c 47 #define NV91C0_NOTIFY_TYPE 31:0 48 #define NV91C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 49 #define NV91C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 50 51 #define NV91C0_WAIT_FOR_IDLE 0x0110 52 #define NV91C0_WAIT_FOR_IDLE_V 31:0 53 54 #define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 55 #define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 56 57 #define NV91C0_LOAD_MME_INSTRUCTION_RAM 0x0118 58 #define NV91C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 59 60 #define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c 61 #define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 62 63 #define NV91C0_LOAD_MME_START_ADDRESS_RAM 0x0120 64 #define NV91C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 65 66 #define NV91C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 67 #define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 68 #define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 69 #define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 70 #define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 71 #define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 72 73 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 74 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 75 76 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 77 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 78 79 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 80 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 81 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 82 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 83 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 84 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 85 #define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 86 87 #define NV91C0_SEND_GO_IDLE 0x013c 88 #define NV91C0_SEND_GO_IDLE_V 31:0 89 90 #define NV91C0_PM_TRIGGER 0x0140 91 #define NV91C0_PM_TRIGGER_V 31:0 92 93 #define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 94 #define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 95 96 #define NV91C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 97 #define NV91C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 98 99 #define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE 0x0204 100 #define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V 23:0 101 102 #define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE 0x0208 103 #define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V 23:0 104 105 #define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE 0x020c 106 #define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V 20:0 107 108 #define NV91C0_SET_BINDING_CONTROL_TEXTURE 0x0210 109 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 110 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 111 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 112 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 113 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 114 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 115 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 116 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 117 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 118 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 119 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 120 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 121 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 122 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 123 #define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 124 125 #define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 126 #define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 127 128 #define NV91C0_INVALIDATE_SHADER_CACHES 0x021c 129 #define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 130 #define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 131 #define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 132 #define NV91C0_INVALIDATE_SHADER_CACHES_DATA 4:4 133 #define NV91C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 134 #define NV91C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 135 #define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 136 #define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 137 #define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 138 #define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 139 #define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 140 #define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 141 #define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 142 #define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 143 #define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 144 #define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 145 #define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 146 #define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 147 148 #define NV91C0_BIND_TEXTURE_SAMPLER 0x0228 149 #define NV91C0_BIND_TEXTURE_SAMPLER_VALID 0:0 150 #define NV91C0_BIND_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 151 #define NV91C0_BIND_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 152 #define NV91C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 153 #define NV91C0_BIND_TEXTURE_SAMPLER_INDEX 24:12 154 155 #define NV91C0_BIND_TEXTURE_HEADER 0x022c 156 #define NV91C0_BIND_TEXTURE_HEADER_VALID 0:0 157 #define NV91C0_BIND_TEXTURE_HEADER_VALID_FALSE 0x00000000 158 #define NV91C0_BIND_TEXTURE_HEADER_VALID_TRUE 0x00000001 159 #define NV91C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT 8:1 160 #define NV91C0_BIND_TEXTURE_HEADER_INDEX 30:9 161 162 #define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER 0x0230 163 #define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID 0:0 164 #define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 165 #define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 166 #define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 167 #define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 168 169 #define NV91C0_BIND_EXTRA_TEXTURE_HEADER 0x0234 170 #define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID 0:0 171 #define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 172 #define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 173 #define NV91C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 174 #define NV91C0_BIND_EXTRA_TEXTURE_HEADER_INDEX 30:9 175 176 #define NV91C0_SET_CTA_RASTER_SIZE_A 0x0238 177 #define NV91C0_SET_CTA_RASTER_SIZE_A_WIDTH 15:0 178 #define NV91C0_SET_CTA_RASTER_SIZE_A_HEIGHT 31:16 179 180 #define NV91C0_SET_CTA_RASTER_SIZE_B 0x023c 181 #define NV91C0_SET_CTA_RASTER_SIZE_B_DEPTH 15:0 182 #define NV91C0_SET_CTA_RASTER_SIZE_B_WIDTH_UPPER 31:16 183 184 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 185 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 186 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 187 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 188 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 189 190 #define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE 0x024c 191 #define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE_V 17:0 192 193 #define NV91C0_SET_CTA_THREAD_COUNT 0x0250 194 #define NV91C0_SET_CTA_THREAD_COUNT_V 15:0 195 196 #define NV91C0_SET_CTA_BARRIER_COUNT 0x0254 197 #define NV91C0_SET_CTA_BARRIER_COUNT_V 7:0 198 199 #define NV91C0_TEST_FOR_COMPUTE 0x028c 200 #define NV91C0_TEST_FOR_COMPUTE_V 31:0 201 202 #define NV91C0_BEGIN_GRID 0x029c 203 #define NV91C0_BEGIN_GRID_V 0:0 204 205 #define NV91C0_SET_WORK_DISTRIBUTION 0x02a0 206 #define NV91C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE 16:13 207 #define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE 4:4 208 #define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE 0x00000000 209 #define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE 0x00000001 210 #define NV91C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS 12:5 211 212 #define NV91C0_SET_CTA_REGISTER_COUNT 0x02c0 213 #define NV91C0_SET_CTA_REGISTER_COUNT_V 7:0 214 215 #define NV91C0_SET_GA_TO_VA_MAPPING_MODE 0x02c4 216 #define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V 0:0 217 #define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 218 #define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 219 220 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 221 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 222 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 223 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 224 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 225 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 226 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 227 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 228 #define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 229 230 #define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS 0x02e0 231 #define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE 0:0 232 #define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_FALSE 0x00000000 233 #define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_TRUE 0x00000001 234 235 #define NV91C0_SET_L1_CONFIGURATION 0x0308 236 #define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 237 #define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 238 #define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 239 #define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 240 241 #define NV91C0_SET_RENDER_ENABLE_CONTROL 0x030c 242 #define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 243 #define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 244 #define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 245 246 #define NV91C0_WAIT_REF_COUNT 0x0360 247 #define NV91C0_WAIT_REF_COUNT_REF_CNT 11:8 248 #define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM 0:0 249 #define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE 0x00000000 250 #define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE 0x00000001 251 252 #define NV91C0_LAUNCH 0x0368 253 #define NV91C0_LAUNCHCTA_PARAM 31:0 254 255 #define NV91C0_SET_LAUNCH_ID 0x036c 256 #define NV91C0_SET_LAUNCH_ID_REF_CNT 3:0 257 258 #define NV91C0_SET_CTA_THREAD_DIMENSION_A 0x03ac 259 #define NV91C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 260 #define NV91C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 261 262 #define NV91C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 263 #define NV91C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 264 265 #define NV91C0_SET_CTA_PROGRAM_START 0x03b4 266 #define NV91C0_SET_CTA_PROGRAM_START_OFFSET 31:0 267 268 #define NV91C0_SET_FALCON00 0x0500 269 #define NV91C0_SET_FALCON00_V 31:0 270 271 #define NV91C0_SET_FALCON01 0x0504 272 #define NV91C0_SET_FALCON01_V 31:0 273 274 #define NV91C0_SET_FALCON02 0x0508 275 #define NV91C0_SET_FALCON02_V 31:0 276 277 #define NV91C0_SET_FALCON03 0x050c 278 #define NV91C0_SET_FALCON03_V 31:0 279 280 #define NV91C0_SET_FALCON04 0x0510 281 #define NV91C0_SET_FALCON04_V 31:0 282 283 #define NV91C0_SET_FALCON05 0x0514 284 #define NV91C0_SET_FALCON05_V 31:0 285 286 #define NV91C0_SET_FALCON06 0x0518 287 #define NV91C0_SET_FALCON06_V 31:0 288 289 #define NV91C0_SET_FALCON07 0x051c 290 #define NV91C0_SET_FALCON07_V 31:0 291 292 #define NV91C0_SET_FALCON08 0x0520 293 #define NV91C0_SET_FALCON08_V 31:0 294 295 #define NV91C0_SET_FALCON09 0x0524 296 #define NV91C0_SET_FALCON09_V 31:0 297 298 #define NV91C0_SET_FALCON10 0x0528 299 #define NV91C0_SET_FALCON10_V 31:0 300 301 #define NV91C0_SET_FALCON11 0x052c 302 #define NV91C0_SET_FALCON11_V 31:0 303 304 #define NV91C0_SET_FALCON12 0x0530 305 #define NV91C0_SET_FALCON12_V 31:0 306 307 #define NV91C0_SET_FALCON13 0x0534 308 #define NV91C0_SET_FALCON13_V 31:0 309 310 #define NV91C0_SET_FALCON14 0x0538 311 #define NV91C0_SET_FALCON14_V 31:0 312 313 #define NV91C0_SET_FALCON15 0x053c 314 #define NV91C0_SET_FALCON15_V 31:0 315 316 #define NV91C0_SET_FALCON16 0x0540 317 #define NV91C0_SET_FALCON16_V 31:0 318 319 #define NV91C0_SET_FALCON17 0x0544 320 #define NV91C0_SET_FALCON17_V 31:0 321 322 #define NV91C0_SET_FALCON18 0x0548 323 #define NV91C0_SET_FALCON18_V 31:0 324 325 #define NV91C0_SET_FALCON19 0x054c 326 #define NV91C0_SET_FALCON19_V 31:0 327 328 #define NV91C0_SET_FALCON20 0x0550 329 #define NV91C0_SET_FALCON20_V 31:0 330 331 #define NV91C0_SET_FALCON21 0x0554 332 #define NV91C0_SET_FALCON21_V 31:0 333 334 #define NV91C0_SET_FALCON22 0x0558 335 #define NV91C0_SET_FALCON22_V 31:0 336 337 #define NV91C0_SET_FALCON23 0x055c 338 #define NV91C0_SET_FALCON23_V 31:0 339 340 #define NV91C0_SET_FALCON24 0x0560 341 #define NV91C0_SET_FALCON24_V 31:0 342 343 #define NV91C0_SET_FALCON25 0x0564 344 #define NV91C0_SET_FALCON25_V 31:0 345 346 #define NV91C0_SET_FALCON26 0x0568 347 #define NV91C0_SET_FALCON26_V 31:0 348 349 #define NV91C0_SET_FALCON27 0x056c 350 #define NV91C0_SET_FALCON27_V 31:0 351 352 #define NV91C0_SET_FALCON28 0x0570 353 #define NV91C0_SET_FALCON28_V 31:0 354 355 #define NV91C0_SET_FALCON29 0x0574 356 #define NV91C0_SET_FALCON29_V 31:0 357 358 #define NV91C0_SET_FALCON30 0x0578 359 #define NV91C0_SET_FALCON30_V 31:0 360 361 #define NV91C0_SET_FALCON31 0x057c 362 #define NV91C0_SET_FALCON31_V 31:0 363 364 #define NV91C0_SET_MAX_SM_COUNT 0x0758 365 #define NV91C0_SET_MAX_SM_COUNT_V 8:0 366 367 #define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c 368 #define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 369 370 #define NV91C0_SET_GRID_PARAM 0x0780 371 #define NV91C0_SET_GRID_PARAM_V 31:0 372 373 #define NV91C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 374 #define NV91C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 375 376 #define NV91C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 377 #define NV91C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 378 379 #define NV91C0_SET_SHADER_LOCAL_MEMORY_C 0x0798 380 #define NV91C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 381 382 #define NV91C0_SET_SHADER_LOCAL_MEMORY_D 0x079c 383 #define NV91C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 384 385 #define NV91C0_SET_SHADER_LOCAL_MEMORY_E 0x07a0 386 #define NV91C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 387 388 #define NV91C0_END_GRID 0x0a04 389 #define NV91C0_END_GRID_V 0:0 390 391 #define NV91C0_SET_LAUNCH_SIZE 0x0a08 392 #define NV91C0_SET_LAUNCH_SIZE_V 31:0 393 394 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT 0x0d64 395 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA 3:0 396 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0 0x00000000 397 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1 0x00000001 398 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2 0x00000002 399 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4 0x00000003 400 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8 0x00000004 401 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16 0x00000005 402 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32 0x00000006 403 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64 0x00000007 404 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128 0x00000008 405 #define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK 0x0000000F 406 407 #define NV91C0_SET_SHADER_CACHE_CONTROL 0x0d94 408 #define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 409 #define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 410 #define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 411 412 #define NV91C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 413 #define NV91C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 414 415 #define NV91C0_SET_SPARE_NOOP12 0x0f44 416 #define NV91C0_SET_SPARE_NOOP12_V 31:0 417 418 #define NV91C0_SET_SPARE_NOOP13 0x0f48 419 #define NV91C0_SET_SPARE_NOOP13_V 31:0 420 421 #define NV91C0_SET_SPARE_NOOP14 0x0f4c 422 #define NV91C0_SET_SPARE_NOOP14_V 31:0 423 424 #define NV91C0_SET_SPARE_NOOP15 0x0f50 425 #define NV91C0_SET_SPARE_NOOP15_V 31:0 426 427 #define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 428 #define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 429 #define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 430 #define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 431 432 #define NV91C0_SET_SPARE_NOOP00 0x1040 433 #define NV91C0_SET_SPARE_NOOP00_V 31:0 434 435 #define NV91C0_SET_SPARE_NOOP01 0x1044 436 #define NV91C0_SET_SPARE_NOOP01_V 31:0 437 438 #define NV91C0_SET_SPARE_NOOP02 0x1048 439 #define NV91C0_SET_SPARE_NOOP02_V 31:0 440 441 #define NV91C0_SET_SPARE_NOOP03 0x104c 442 #define NV91C0_SET_SPARE_NOOP03_V 31:0 443 444 #define NV91C0_SET_SPARE_NOOP04 0x1050 445 #define NV91C0_SET_SPARE_NOOP04_V 31:0 446 447 #define NV91C0_SET_SPARE_NOOP05 0x1054 448 #define NV91C0_SET_SPARE_NOOP05_V 31:0 449 450 #define NV91C0_SET_SPARE_NOOP06 0x1058 451 #define NV91C0_SET_SPARE_NOOP06_V 31:0 452 453 #define NV91C0_SET_SPARE_NOOP07 0x105c 454 #define NV91C0_SET_SPARE_NOOP07_V 31:0 455 456 #define NV91C0_SET_SPARE_NOOP08 0x1060 457 #define NV91C0_SET_SPARE_NOOP08_V 31:0 458 459 #define NV91C0_SET_SPARE_NOOP09 0x1064 460 #define NV91C0_SET_SPARE_NOOP09_V 31:0 461 462 #define NV91C0_SET_SPARE_NOOP10 0x1068 463 #define NV91C0_SET_SPARE_NOOP10_V 31:0 464 465 #define NV91C0_SET_SPARE_NOOP11 0x106c 466 #define NV91C0_SET_SPARE_NOOP11_V 31:0 467 468 #define NV91C0_UNBIND_ALL 0x10f4 469 #define NV91C0_UNBIND_ALL_TEXTURE_HEADERS 0:0 470 #define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 471 #define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 472 #define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 473 #define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 474 #define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 475 #define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS 8:8 476 #define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 477 #define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 478 479 #define NV91C0_SET_SAMPLER_BINDING 0x1234 480 #define NV91C0_SET_SAMPLER_BINDING_V 0:0 481 #define NV91C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 482 #define NV91C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 483 484 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 485 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 486 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 487 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 488 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 489 490 #define NV91C0_SET_SHADER_SCHEDULING 0x12ac 491 #define NV91C0_SET_SHADER_SCHEDULING_MODE 0:0 492 #define NV91C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 493 #define NV91C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 494 495 #define NV91C0_INVALIDATE_SAMPLER_CACHE 0x1330 496 #define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 497 #define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 498 #define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 499 #define NV91C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 500 501 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 502 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 503 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 504 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 505 #define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 506 507 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 508 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 509 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 510 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 511 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 512 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 513 #define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 514 515 #define NV91C0_SET_GLOBAL_COLOR_KEY 0x1354 516 #define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 517 #define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 518 #define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 519 520 #define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 521 #define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 522 #define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 523 #define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 524 #define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 525 526 #define NV91C0_PERFMON_TRANSFER 0x1524 527 #define NV91C0_PERFMON_TRANSFER_V 31:0 528 529 #define NV91C0_SET_SHADER_EXCEPTIONS 0x1528 530 #define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 531 #define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 532 #define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 533 534 #define NV91C0_SET_RENDER_ENABLE_A 0x1550 535 #define NV91C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 536 537 #define NV91C0_SET_RENDER_ENABLE_B 0x1554 538 #define NV91C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 539 540 #define NV91C0_SET_RENDER_ENABLE_C 0x1558 541 #define NV91C0_SET_RENDER_ENABLE_C_MODE 2:0 542 #define NV91C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 543 #define NV91C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 544 #define NV91C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 545 #define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 546 #define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 547 548 #define NV91C0_SET_TEX_SAMPLER_POOL_A 0x155c 549 #define NV91C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 550 551 #define NV91C0_SET_TEX_SAMPLER_POOL_B 0x1560 552 #define NV91C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 553 554 #define NV91C0_SET_TEX_SAMPLER_POOL_C 0x1564 555 #define NV91C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 556 557 #define NV91C0_SET_TEX_HEADER_POOL_A 0x1574 558 #define NV91C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 559 560 #define NV91C0_SET_TEX_HEADER_POOL_B 0x1578 561 #define NV91C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 562 563 #define NV91C0_SET_TEX_HEADER_POOL_C 0x157c 564 #define NV91C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 565 566 #define NV91C0_SET_PROGRAM_REGION_A 0x1608 567 #define NV91C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 568 569 #define NV91C0_SET_PROGRAM_REGION_B 0x160c 570 #define NV91C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 571 572 #define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 573 #define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 574 #define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 575 #define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 576 #define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 577 #define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 578 579 #define NV91C0_SET_SHADER_CONTROL 0x1690 580 #define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 581 #define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 582 #define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 583 #define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 584 #define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 585 #define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 586 #define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 587 #define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 588 #define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 589 #define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 590 #define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 591 #define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 592 593 #define NV91C0_BIND_CONSTANT_BUFFER 0x1694 594 #define NV91C0_BIND_CONSTANT_BUFFER_VALID 0:0 595 #define NV91C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 596 #define NV91C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 597 #define NV91C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 12:8 598 599 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 600 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 601 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 602 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 603 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 604 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 605 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 606 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM 8:8 607 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE 0x00000000 608 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE 0x00000001 609 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 610 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 611 #define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 612 613 #define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 614 #define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 615 #define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 616 #define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 617 618 #define NV91C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 619 #define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 620 #define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 621 #define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 622 #define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 623 624 #define NV91C0_PIPE_NOP 0x1a2c 625 #define NV91C0_PIPE_NOP_V 31:0 626 627 #define NV91C0_SET_SPARE00 0x1a30 628 #define NV91C0_SET_SPARE00_V 31:0 629 630 #define NV91C0_SET_SPARE01 0x1a34 631 #define NV91C0_SET_SPARE01_V 31:0 632 633 #define NV91C0_SET_SPARE02 0x1a38 634 #define NV91C0_SET_SPARE02_V 31:0 635 636 #define NV91C0_SET_SPARE03 0x1a3c 637 #define NV91C0_SET_SPARE03_V 31:0 638 639 #define NV91C0_SET_REPORT_SEMAPHORE_A 0x1b00 640 #define NV91C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 641 642 #define NV91C0_SET_REPORT_SEMAPHORE_B 0x1b04 643 #define NV91C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 644 645 #define NV91C0_SET_REPORT_SEMAPHORE_C 0x1b08 646 #define NV91C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 647 648 #define NV91C0_SET_REPORT_SEMAPHORE_D 0x1b0c 649 #define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 650 #define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 651 #define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 652 #define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 653 #define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 654 #define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 655 #define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 656 #define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 657 #define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 658 #define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 659 #define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 660 #define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 661 662 #define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 663 #define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 664 665 #define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 666 #define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 667 668 #define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 669 #define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 670 671 #define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET 0x238c 672 #define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 673 674 #define NV91C0_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) 675 #define NV91C0_LOAD_CONSTANT_BUFFER_V 31:0 676 677 #define NV91C0_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) 678 #define NV91C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 679 680 #define NV91C0_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) 681 #define NV91C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 682 683 #define NV91C0_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) 684 #define NV91C0_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 685 686 #define NV91C0_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) 687 #define NV91C0_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 688 #define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 689 #define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 690 #define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 691 692 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) 693 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 694 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 695 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 696 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 697 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 698 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 699 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 700 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 701 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 702 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 703 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 704 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 705 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 706 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 707 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 708 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA 709 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB 710 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC 711 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD 712 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE 713 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF 714 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 715 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 716 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 717 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 718 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 719 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 720 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 721 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 722 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA 723 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB 724 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC 725 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD 726 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE 727 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF 728 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 729 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 730 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 731 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 732 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 733 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 734 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 735 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 736 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA 737 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB 738 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC 739 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED 740 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE 741 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF 742 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 743 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 744 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 745 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 746 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 747 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 748 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 749 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 750 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 751 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 752 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA 753 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB 754 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC 755 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD 756 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE 757 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF 758 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 759 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 760 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 761 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 762 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 763 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 764 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 765 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_B8G8R8A8 0x00000047 766 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 767 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 768 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 769 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 770 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 771 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 772 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A 773 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 774 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D 775 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E 776 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F 777 #define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT 25:17 778 779 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) 780 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 781 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 782 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 783 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 784 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 785 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 786 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 787 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 788 #define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 789 790 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) 791 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 792 793 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) 794 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 795 796 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) 797 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 798 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 799 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 800 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 801 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 802 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 803 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 804 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 805 806 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) 807 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 808 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 809 810 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc 811 #define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 812 813 #define NV91C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) 814 #define NV91C0_SET_MME_SHADOW_SCRATCH_V 31:0 815 816 #define NV91C0_CALL_MME_MACRO(j) (0x3800+(j)*8) 817 #define NV91C0_CALL_MME_MACRO_V 31:0 818 819 #define NV91C0_CALL_MME_DATA(j) (0x3804+(j)*8) 820 #define NV91C0_CALL_MME_DATA_V 31:0 821 822 #endif /* _cl_fermi_compute_b_h_ */ 823