1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef CMRTLIB_AGNOSTIC_SHARE_CM_L3_CACHE_CONFIG_H_ 24 #define CMRTLIB_AGNOSTIC_SHARE_CM_L3_CACHE_CONFIG_H_ 25 26 struct L3ConfigRegisterValues 27 { L3ConfigRegisterValuesL3ConfigRegisterValues28 L3ConfigRegisterValues(): configRegister0(0), 29 configRegister1(0), 30 configRegister2(0), 31 configRegister3(0) {} 32 L3ConfigRegisterValuesL3ConfigRegisterValues33 L3ConfigRegisterValues(uint32_t registerValue0, 34 uint32_t registerValue1, 35 uint32_t registerValue2, 36 uint32_t registerValue3): 37 configRegister0(registerValue0), 38 configRegister1(registerValue1), 39 configRegister2(registerValue2), 40 configRegister3(registerValue3) {} 41 42 uint32_t configRegister0; 43 uint32_t configRegister1; 44 uint32_t configRegister2; 45 uint32_t configRegister3; 46 }; 47 48 typedef enum _L3_SUGGEST_CONFIG 49 { 50 CM_L3_PLANE_DEFAULT = 0, 51 CM_L3_PLANE_1, 52 CM_L3_PLANE_2, 53 CM_L3_PLANE_3, 54 CM_L3_PLANE_4, 55 CM_L3_PLANE_5, 56 CM_L3_PLANE_6, 57 CM_L3_PLANE_7, 58 CM_L3_PLANE_8, 59 } L3_SUGGEST_CONFIG; 60 61 #endif // #ifndef CMRTLIB_AGNOSTIC_SHARE_CM_L3_CACHE_CONFIG_H_ 62