1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file cm_rt_g10.h 24 //! \brief Contains Definitions for CM on Gen 10 25 //! 26 27 #ifndef __CM_RT_G10_H__ 28 #define __CM_RT_G10_H__ 29 30 #include "cm_hw_vebox_cmd_g10.h" 31 32 #define CNL_L3_PLANE_DEFAULT CM_L3_PLANE_DEFAULT 33 #define CNL_L3_PLANE_1 CM_L3_PLANE_1 34 #define CNL_L3_PLANE_2 CM_L3_PLANE_2 35 #define CNL_L3_PLANE_3 CM_L3_PLANE_3 36 #define CNL_L3_PLANE_4 CM_L3_PLANE_4 37 #define CNL_L3_PLANE_5 CM_L3_PLANE_5 38 #define CNL_L3_PLANE_6 CM_L3_PLANE_6 39 #define CNL_L3_PLANE_7 CM_L3_PLANE_7 40 #define CNL_L3_PLANE_8 CM_L3_PLANE_8 41 #define CNL_L3_CONFIG_COUNT 9 42 43 static const L3ConfigRegisterValues CNL_L3_PLANES[CNL_L3_CONFIG_COUNT] = 44 { // SLM URB Rest DC RO Sum (in KB) 45 {0, 0, 0, 0x80000080}, // 0 128 128 0 0 256 46 {0, 0, 0, 0x418080}, // 0 128 0 32 96 256 47 {0, 0, 0, 0x420060}, // 0 96 0 32 128 256 48 {0, 0, 0, 0x30040}, // 0 64 0 0 192 256 49 {0, 0, 0, 0xC0000040}, // 0 64 192 0 0 256 50 {0, 0, 0, 0x428040}, // 0 64 0 32 160 256 51 {0, 0, 0, 0xA0000021}, // 32 32 160 0 0 256 52 {0, 0, 0, 0x1008021}, // 32 32 0 128 32 256 53 {0, 0, 0, 0xC0000001} // 32 0 192 0 0 256 54 }; 55 56 typedef struct __CM_VEBOX_PARAM_G10 57 { 58 unsigned char padding1[4024]; 59 unsigned char padding2[3732]; 60 PVEBOX_GAMUT_STATE_G75 pGamutState; 61 unsigned char padding3[3936]; 62 PVEBOX_VERTEX_TABLE_G75 pVertexTable; 63 unsigned char padding4[2048]; 64 65 CmHwVeboxCmdG10::VEBOX_CAPTURE_PIPE_STATE_CMD *pCapturePipe; 66 CmHwVeboxCmdG10::VEBOX_DNDI_STATE_CMD *pDndiState; 67 CmHwVeboxCmdG10::VEBOX_IECP_STATE_CMD *pIecpState; 68 }CM_VEBOX_PARAM_G10, PCM_VEBOX_PARAM_G10; 69 70 #endif //__CM_RT_G10_H__ 71