1 /*
2 * Copyright (c) 2020-2022, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codec_hw_xe_lpm_plus_base.cpp
24 //! \brief Implements HW interface layer for Xe_LPM_plus+ used on all OSs.
25 //! \details Implements HW interface layer for CNL+ to be used on on all operating systems/DDIs, across CODECHAL components.
26 //! This module must not contain any OS dependent code.
27 //!
28
29 #include "codec_hw_xe_lpm_plus_base.h"
30 #include "mhw_vdbox_xe_lpm_plus_base.h"
31 #include "mhw_vdbox_huc_hwcmd_xe_lpm_plus.h"
32
33 // Currently initialized with dummy values, just as an example. Will be updated later.
34 const CODECHAL_SSEU_SETTING CodechalHwInterfaceXe_Lpm_Plus_Base::m_defaultSsEuLutXeLpmPlus[CODECHAL_NUM_MEDIA_STATES_XE_LPM_PLUS_BASE] =
35 {
36 // Slice Sub-Slice EU Rsvd(freq)
37 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_OLP
38 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_NORMAL
39 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_PERFORMANCE
40 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_QUALITY
41 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_DIST
42 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_SCALING
43 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_SCALING
44 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_SCALING
45 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_ME
46 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_ME
47 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_ME
48 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_INIT_RESET
49 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_UPDATE
50 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_BLOCK_COPY
51 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P1
52 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P2
53 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_CHROMA
54 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_LUMA
55 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MPU_FHB
56 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_TPU_FHB
57 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PA_COPY
58 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PL2_COPY
59 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_ADV
60 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_SCALING
61 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_PU_MODE_DECISION
62 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_SAD
63 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_MODE_DECISION
64 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU
65 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU_FMODE
66 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_B_INTRA_CHECK
67 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_MBENC
68 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_RESET_VLINE_STRIDE
69 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_PAK
70 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE
71 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ME_VDENC_STREAMIN
72 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_32x32
73 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_16x16
74 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_P
75 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_TX
76 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_RECON
77 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_RECON
78 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK
79 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK
80 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK
81 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_MC_PRED
82 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON
83 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON
84 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON
85 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON
86 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PREPROC
87 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_WP
88 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_I_MBENC
89 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_CSC_DS_COPY
90 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_4X_SCALING
91 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_LCU64_B_MBENC
92 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MB_BRC_UPDATE
93 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_STATIC_FRAME_DETECTION
94 { 1, 0, 8, 0 },
95 { 1, 0, 8, 0 },
96 { 1, 0, 8, 0 },
97 { 1, 0, 8, 0 },
98 { 2, 3, 8, 0 },
99 { 2, 3, 8, 0 },
100 { 2, 3, 8, 0 },
101 { 2, 3, 8, 0 },
102 };
103
CodechalHwInterfaceXe_Lpm_Plus_Base(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfacesNext * mhwInterfacesNext,bool disableScalability)104 CodechalHwInterfaceXe_Lpm_Plus_Base::CodechalHwInterfaceXe_Lpm_Plus_Base(
105 PMOS_INTERFACE osInterface,
106 CODECHAL_FUNCTION codecFunction,
107 MhwInterfacesNext *mhwInterfacesNext,
108 bool disableScalability)
109 : CodechalHwInterfaceNext(osInterface, codecFunction, mhwInterfacesNext, disableScalability)
110 {
111 CODEC_HW_FUNCTION_ENTER;
112
113 m_mediaSfcItf = std::make_shared<MediaSfcInterface>(m_osInterface);
114
115 InitCacheabilityControlSettings(codecFunction);
116
117 m_isVdencSuperSliceEnabled = true;
118
119 m_ssEuTable = m_defaultSsEuLutXeLpmPlus;
120 m_numMediaStates = CODECHAL_NUM_MEDIA_STATES_XE_LPM_PLUS_BASE;
121
122 // Set platform dependent parameters
123 m_sizeOfCmdBatchBufferEnd = m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
124 m_sizeOfCmdMediaReset = m_miItf->MHW_GETSIZE_F(MI_LOAD_REGISTER_IMM)() * 8;
125 m_vdencBrcImgStateBufferSize = m_vdencItf->MHW_GETSIZE_F(VDENC_AVC_IMG_STATE)()
126 + m_mfxItf->MHW_GETSIZE_F(MFX_AVC_IMG_STATE)()
127 + m_vdencItf->MHW_GETSIZE_F(VDENC_CMD3)()
128 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
129
130 m_vdencBatchBuffer1stGroupSize = m_hcpItf->MHW_GETSIZE_F(HCP_PIPE_MODE_SELECT)()
131 + m_miItf->MHW_GETSIZE_F(MFX_WAIT)() * 2
132 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
133
134 m_vdencBatchBuffer2ndGroupSize = m_vdencItf->MHW_GETSIZE_F(VDENC_CMD1)()
135 + m_hcpItf->MHW_GETSIZE_F(HCP_PIC_STATE)()
136 + m_vdencItf->MHW_GETSIZE_F(VDENC_CMD2)()
137 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
138
139 m_vdencReadBatchBufferSize =
140 m_vdenc2ndLevelBatchBufferSize = m_vdencBatchBuffer1stGroupSize
141 + m_vdencBatchBuffer2ndGroupSize
142 + ENCODE_HEVC_VDENC_NUM_MAX_SLICES * (2 * m_hcpItf->MHW_GETSIZE_F(HCP_WEIGHTOFFSET_STATE)()
143 + m_hcpItf->MHW_GETSIZE_F(HCP_SLICE_STATE)()
144 + (HEVC_MAX_NAL_UNIT_TYPE + 2) * m_hcpItf->MHW_GETSIZE_F(HCP_PAK_INSERT_OBJECT)()
145 + m_vdencItf->MHW_GETSIZE_F(VDENC_WEIGHTSOFFSETS_STATE)()
146 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)()
147 + 4 * ENCODE_VDENC_HEVC_PADDING_DW_SIZE);
148
149 m_HucStitchCmdBatchBufferSize = 7 * 4
150 + 14 * 4
151 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
152
153 // HCP_WEIGHTOFFSET_STATE_CMD cmds is planned to be added in near future
154 m_vdencBatchBufferPerSliceConstSize = m_hcpItf->MHW_GETSIZE_F(HCP_SLICE_STATE)()
155 + m_hcpItf->MHW_GETSIZE_F(HCP_PAK_INSERT_OBJECT)() // 1st PakInsertObject cmd is not always inserted for each slice, 2nd PakInsertObject cmd is always inserted for each slice
156 + m_vdencItf->MHW_GETSIZE_F(VDENC_WEIGHTSOFFSETS_STATE)()
157 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
158
159 // No kernel used on xe lpm plus
160 m_maxKernelLoadCmdSize = 0;
161
162 m_sizeOfCmdMediaObject = 0;
163 m_sizeOfCmdMediaStateFlush = 0;
164 }
165
SetRowstoreCachingOffsets(PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)166 MOS_STATUS CodechalHwInterfaceXe_Lpm_Plus_Base::SetRowstoreCachingOffsets(
167 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)
168 {
169 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
170
171 CODEC_HW_FUNCTION_ENTER;
172
173 CODEC_HW_CHK_STATUS_RETURN(CodechalHwInterfaceNext::SetRowstoreCachingOffsets(rowstoreParams));
174 if (GetMfxInterfaceNext())
175 {
176 CODEC_HW_CHK_STATUS_RETURN(GetMfxInterfaceNext()->GetRowstoreCachingAddrs(rowstoreParams));
177 }
178
179 return eStatus;
180 }
181
GetAvpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)182 MOS_STATUS CodechalHwInterfaceXe_Lpm_Plus_Base::GetAvpStateCommandSize(
183 uint32_t mode,
184 uint32_t *commandsSize,
185 uint32_t *patchListSize,
186 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
187 {
188 CODEC_HW_FUNCTION_ENTER;
189
190 //calculate AVP related commands size
191 uint32_t avpCommandsSize = 0;
192 uint32_t avpPatchListSize = 0;
193 uint32_t cpCmdsize = 0;
194 uint32_t cpPatchListSize = 0;
195
196 if (GetAvpInterfaceNext())
197 {
198 CODEC_HW_CHK_STATUS_RETURN(GetAvpInterfaceNext()->GetAvpStateCmdSize(
199 (uint32_t *)&avpCommandsSize,
200 (uint32_t *)&avpPatchListSize,
201 params));
202 }
203
204 if (m_cpInterface)
205 {
206 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
207 }
208
209 //Calc final command size
210 *commandsSize = avpCommandsSize + cpCmdsize;
211 *patchListSize = avpPatchListSize + cpPatchListSize;
212
213 return MOS_STATUS_SUCCESS;
214 }
215
GetAvpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)216 MOS_STATUS CodechalHwInterfaceXe_Lpm_Plus_Base::GetAvpPrimitiveCommandSize(
217 uint32_t mode,
218 uint32_t *commandsSize,
219 uint32_t *patchListSize)
220 {
221 CODEC_HW_FUNCTION_ENTER;
222
223 //calculate AVP related commands size
224 uint32_t avpCommandsSize = 0;
225 uint32_t avpPatchListSize = 0;
226 uint32_t cpCmdsize = 0;
227 uint32_t cpPatchListSize = 0;
228
229 if (GetAvpInterfaceNext())
230 {
231 MHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams;
232 CODEC_HW_CHK_STATUS_RETURN(GetAvpInterfaceNext()->GetAvpPrimitiveCmdSize(
233 (uint32_t*)&avpCommandsSize,
234 (uint32_t*)&avpPatchListSize,
235 &stateCmdSizeParams));
236 }
237
238 if (m_cpInterface)
239 {
240 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
241 }
242
243 //Calc final command size
244 *commandsSize = avpCommandsSize + cpCmdsize;
245 *patchListSize = avpPatchListSize + cpPatchListSize;
246
247 return MOS_STATUS_SUCCESS;
248 }
249
GetHcpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)250 MOS_STATUS CodechalHwInterfaceXe_Lpm_Plus_Base::GetHcpStateCommandSize(
251 uint32_t mode,
252 uint32_t * commandsSize,
253 uint32_t * patchListSize,
254 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
255 {
256 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
257
258 CODEC_HW_FUNCTION_ENTER;
259
260 uint32_t standard = CodecHal_GetStandardFromMode(mode);
261
262 uint32_t hcpCommandsSize = 0;
263 uint32_t hcpPatchListSize = 0;
264 uint32_t cpCmdsize = 0;
265 uint32_t cpPatchListSize = 0;
266
267 if (m_hcpItf && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
268 {
269 CODEC_HW_CHK_STATUS_RETURN(m_hcpItf->GetHcpStateCommandSize(
270 mode, &hcpCommandsSize, &hcpPatchListSize, params));
271
272 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
273 }
274
275 *commandsSize = hcpCommandsSize + cpCmdsize;
276 *patchListSize = hcpPatchListSize + cpPatchListSize;
277
278 return eStatus;
279 }
280
GetHcpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)281 MOS_STATUS CodechalHwInterfaceXe_Lpm_Plus_Base::GetHcpPrimitiveCommandSize(
282 uint32_t mode,
283 uint32_t *commandsSize,
284 uint32_t *patchListSize,
285 bool modeSpecific)
286 {
287 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
288
289 CODEC_HW_FUNCTION_ENTER;
290
291 uint32_t standard = CodecHal_GetStandardFromMode(mode);
292
293 uint32_t hcpCommandsSize = 0;
294 uint32_t hcpPatchListSize = 0;
295 uint32_t cpCmdsize = 0;
296 uint32_t cpPatchListSize = 0;
297
298 if (m_hcpItf && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
299 {
300 CODEC_HW_CHK_STATUS_RETURN(m_hcpItf->GetHcpPrimitiveCommandSize(
301 mode, &hcpCommandsSize, &hcpPatchListSize, modeSpecific ? true : false));
302
303 CODEC_HW_CHK_NULL_RETURN(m_cpInterface);
304 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
305 }
306
307 *commandsSize = hcpCommandsSize + cpCmdsize;
308 *patchListSize = hcpPatchListSize + cpPatchListSize;
309
310 return eStatus;
311 }
312
313
SendCondBbEndCmd(PMOS_RESOURCE resource,uint32_t offset,uint32_t compData,bool disableCompMask,bool enableEndCurrentBatchBuffLevel,uint32_t compareOperation,PMOS_COMMAND_BUFFER cmdBuffer)314 MOS_STATUS CodechalHwInterfaceXe_Lpm_Plus_Base::SendCondBbEndCmd(
315 PMOS_RESOURCE resource,
316 uint32_t offset,
317 uint32_t compData,
318 bool disableCompMask,
319 bool enableEndCurrentBatchBuffLevel,
320 uint32_t compareOperation,
321 PMOS_COMMAND_BUFFER cmdBuffer)
322 {
323 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
324
325 CODEC_HW_FUNCTION_ENTER;
326
327 if (!Mos_ResourceIsNull(&m_conditionalBbEndDummy))
328 {
329 auto &par = GetMiInterfaceNext()->GETPAR_MI_FLUSH_DW();
330 par = {};
331 par.postSyncOperation = 1;
332 par.pOsResource = &m_conditionalBbEndDummy;
333 par.dwDataDW1 = 0;
334 CODEC_HW_CHK_STATUS_RETURN(GetMiInterfaceNext()->ADDCMD_MI_FLUSH_DW(cmdBuffer));
335 }
336
337 auto &par = GetMiInterfaceNext()->GETPAR_MI_CONDITIONAL_BATCH_BUFFER_END();
338 par = {};
339 par.presSemaphoreBuffer = resource;
340 par.dwOffset = offset;
341 par.dwValue = compData;
342 par.bDisableCompareMask = disableCompMask;
343 par.dwParamsType = mhw::mi::MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS::ENHANCED_PARAMS;
344 if (enableEndCurrentBatchBuffLevel)
345 {
346 par.enableEndCurrentBatchBuffLevel = enableEndCurrentBatchBuffLevel;
347 par.compareOperation = compareOperation;
348 }
349 eStatus = GetMiInterfaceNext()->ADDCMD_MI_CONDITIONAL_BATCH_BUFFER_END(cmdBuffer);
350
351 return eStatus;
352 }
353
Initialize(CodechalSetting * settings)354 MOS_STATUS CodechalHwInterfaceXe_Lpm_Plus_Base::Initialize(
355 CodechalSetting *settings)
356 {
357 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
358
359 CODEC_HW_FUNCTION_ENTER;
360
361 CODEC_HW_CHK_STATUS_RETURN(CodechalHwInterfaceNext::Initialize(settings));
362
363 //Initialize renderHal
364 m_renderHal = (PRENDERHAL_INTERFACE)MOS_AllocAndZeroMemory(sizeof(RENDERHAL_INTERFACE));
365 CODEC_HW_CHK_NULL_RETURN(m_renderHal);
366 CODEC_HW_CHK_STATUS_RETURN(RenderHal_InitInterface(
367 m_renderHal,
368 &m_renderHalCpInterface,
369 m_osInterface));
370
371 RENDERHAL_SETTINGS RenderHalSettings;
372 RenderHalSettings.iMediaStates = 32;
373 CODEC_HW_CHK_STATUS_RETURN(m_renderHal->pfnInitialize(m_renderHal, &RenderHalSettings));
374
375 //set SSEU table
376 m_renderHal->sseuTable = m_ssEuTable;
377
378 return eStatus;
379 }
380
~CodechalHwInterfaceXe_Lpm_Plus_Base()381 CodechalHwInterfaceXe_Lpm_Plus_Base::~CodechalHwInterfaceXe_Lpm_Plus_Base()
382 {
383 if (m_renderHal != nullptr && m_renderHal->pfnDestroy != nullptr)
384 {
385 MOS_STATUS eStatus = m_renderHal->pfnDestroy(m_renderHal);
386 if (eStatus != MOS_STATUS_SUCCESS)
387 {
388 MHW_ASSERTMESSAGE("Failed to destroy RenderHal, eStatus:%d.\n", eStatus);
389 }
390
391 if (m_renderHalCpInterface)
392 {
393 MOS_Delete(m_renderHalCpInterface);
394 m_renderHalCpInterface = nullptr;
395 }
396
397 MOS_FreeMemory(m_renderHal);
398 m_renderHal = nullptr;
399 }
400 }
401