1 /* 2 * Copyright (c) 2017-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_vdenc_hevc_g12.h 24 //! \brief HEVC VDEnc encoder for GEN12 platform. 25 //! 26 27 #ifndef __CODECHAL_VDENC_HEVC_G12_H__ 28 #define __CODECHAL_VDENC_HEVC_G12_H__ 29 30 #include "codechal_vdenc_hevc.h" 31 #include "mhw_vdbox_g12_X.h" 32 #include "codechal_debug_encode_par_g12.h" 33 #include "codechal_encode_singlepipe_virtualengine.h" 34 #include "codechal_encode_scalability.h" 35 #ifdef _ENCODE_VDENC_RESERVED 36 #include "codechal_vdenc_hevc_g12_rsvd.h" 37 #endif 38 39 #define HUC_CMD_LIST_MODE 1 40 #define HUC_BATCH_BUFFER_END 0x05000000 41 #define VDBOX_HUC_PAK_INTEGRATION_KERNEL_DESCRIPTOR 15 42 #define CODECHAL_ENCODE_HEVC_VDENC_WP_DATA_BLOCK_NUMBER 6 43 44 struct CODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G12 45 { 46 uint32_t BRCFunc_U32; // 0: Init; 2: Reset, bit7 0: frame-based; 1: tile-based 47 uint32_t UserMaxFrame; // ProfileLevelMaxFrame_U32 48 uint32_t InitBufFull_U32; 49 uint32_t BufSize_U32; 50 uint32_t TargetBitrate_U32; 51 uint32_t MaxRate_U32; 52 uint32_t MinRate_U32; 53 uint32_t FrameRateM_U32; 54 uint32_t FrameRateD_U32; 55 uint32_t LumaLog2WeightDenom_U32; 56 uint32_t ChromaLog2WeightDenom_U32; 57 uint8_t BRCFlag : 7; // ACQP/ICQ=0, CBR=1, VBR=2, VCM=3, LOWDELAY=4 58 uint8_t SSCFlag : 1; // SSC: 0x80 59 uint8_t Reserved; 60 uint16_t GopP_U16; 61 uint16_t GopB_U16; 62 uint16_t FrameWidth_U16; 63 uint16_t FrameHeight_U16; 64 uint16_t GopB1_U16; 65 uint16_t GopB2_U16; 66 uint8_t MinQP_U8; 67 uint8_t MaxQP_U8; 68 uint8_t MaxBRCLevel_U8; 69 uint8_t LumaBitDepth_U8; 70 uint8_t ChromaBitDepth_U8; 71 uint8_t CuQpCtrl_U8; // 0=No CUQP; 1=CUQP for I-frame; 2=CUQP for P/B-frame 72 73 uint8_t RSVD0[4]; 74 int8_t DevThreshPB0_S8[8]; 75 int8_t DevThreshVBR0_S8[8]; 76 int8_t DevThreshI0_S8[8]; 77 int8_t InstRateThreshP0_S8[4]; 78 int8_t InstRateThreshB0_S8[4]; 79 int8_t InstRateThreshI0_S8[4]; 80 uint8_t LowDelayMode_U8; 81 uint8_t InitQPIP_U8; 82 uint8_t InitQPB_U8; // In CQP mode, InitQPB_U8= InitQPIP_U8 83 uint8_t QPDeltaThrForAdapt2Pass_U8; 84 uint8_t TopFrmSzThrForAdapt2Pass_U8; 85 uint8_t BotFrmSzThrForAdapt2Pass_U8; 86 uint8_t QPSelectForFirstPass_U8; 87 uint8_t MBHeaderCompensation_U8; 88 uint8_t OverShootCarryFlag_U8; 89 uint8_t OverShootSkipFramePct_U8; 90 uint8_t EstRateThreshP0_U8[7]; 91 uint8_t EstRateThreshB0_U8[7]; 92 93 uint8_t EstRateThreshI0_U8[7]; 94 uint8_t QPP_U8; 95 uint8_t StreamInSurfaceEnable_U8; // 0-disabled, 1-enabled 96 uint8_t StreamInROIEnable_U8; // 0-disabled, 1-enabled 97 uint8_t TimingBudget_Enable_U8; // 0-disabled, 1-enabled 98 uint8_t TopQPDeltaThrForAdapt2Pass_U8; // 2 99 uint8_t BotQPDeltaThrForAdapt2Pass_U8; // 1 100 uint8_t RESERVED; 101 uint8_t NetworkTraceEnable_U8; // 0-disabled, 1-enabled 102 uint8_t LowDelaySceneChangeXFrameSizeEnable_U8; // 0-disabled, 1-enabled 103 uint32_t ACQP_U32; // 1 104 uint32_t SlidingWindow_Size_U32; // 30 105 106 uint8_t SLIDINGWINDOW_MaxRateRatio; 107 uint8_t LookaheadDepth_U8; 108 int8_t CbQPOffset; 109 int8_t CrQPOffset; 110 111 uint32_t ProfileLevelMaxFramePB_U32; 112 113 // tile-based BRC 114 uint16_t SlideWindowRC; // Reserved now 115 uint16_t MaxLogCUSize; 116 117 uint16_t FrameWidthInLCU; 118 uint16_t FrameHeightInLCU; 119 120 uint8_t BRCPyramidEnable_U8; 121 uint8_t LongTermRefEnable_U8; 122 uint16_t LongTermRefInterval_U16; 123 uint8_t LongTermRefMsdk_U8; 124 uint8_t IsLowDelay_U8; 125 uint16_t RSVD3; 126 uint32_t RSVD1[4]; // 64 bytes aligned 127 }; 128 C_ASSERT(192 == sizeof(CODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G12)); 129 130 using PCODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G12 = CODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G12*; 131 132 struct CODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G12 133 { 134 uint32_t TARGETSIZE_U32; 135 uint32_t FrameID_U32; // frame number 136 uint32_t Ref_L0_FrameID_U32[8]; 137 uint32_t Ref_L1_FrameID_U32[8]; 138 uint16_t startGAdjFrame_U16[4]; // 10, 50, 100, 150 139 uint16_t TargetSliceSize_U16; 140 uint16_t SLB_Data_SizeInBytes; 141 uint16_t PIC_STATE_StartInBytes; // PIC_STATE starts in byte. 0xFFFF means not available in SLB 142 uint16_t CMD2_StartInBytes; 143 uint16_t CMD1_StartInBytes; 144 uint16_t PIPE_MODE_SELECT_StartInBytes; // PIPE Mode select starts in byte. 0xFFFF means not available in SLB 145 uint16_t Current_Data_Offset; // Data block offset of current picture from beginning of the data buffer (region 9) 146 uint16_t Ref_Data_Offset[5]; // Data block offset of ref pictures from beginning of the data buffer (region 9) 147 uint16_t MaxNumSliceAllowed_U16; 148 uint8_t OpMode_U8; // 1: frame-based BRC (including ACQP), 2: Weighted prediction, Weighted prediction should not be enabled in first pass. 149 // Same as other common flags, this is a bit operation. Each bit is zero for disabling and 1 for enabling. i.e. 01: BRC, 10: WP - never used; 11: BRC+WP, 4: tile-based BRC (frame level), 8: tile-based BRC (tile level) 150 uint8_t CurrentFrameType_U8; 151 uint8_t Num_Ref_L0_U8; 152 uint8_t Num_Ref_L1_U8; 153 uint8_t Num_Slices; 154 uint8_t CQP_QPValue_U8; // CQP QP value (needed for ICQ and ACQP) 155 uint8_t CQP_FracQP_U8; 156 uint8_t MaxNumPass_U8; // max number of BRC passes (SAO second pass is not included.) 157 uint8_t gRateRatioThreshold_U8[7]; 158 uint8_t startGAdjMult_U8[5]; 159 uint8_t startGAdjDiv_U8[5]; 160 uint8_t gRateRatioThresholdQP_U8[8]; 161 uint8_t SceneChgPrevIntraPctThreshold_U8; 162 uint8_t SceneChgCurIntraPctThreshold_U8; 163 uint8_t IPAverageCoeff_U8; 164 uint8_t CurrentPass_U8; 165 int8_t DeltaQPForMvZero_S8; 166 int8_t DeltaQPForMvZone0_S8; 167 int8_t DeltaQPForMvZone1_S8; 168 int8_t DeltaQPForMvZone2_S8; 169 int8_t DeltaQPForSadZone0_S8; 170 int8_t DeltaQPForSadZone1_S8; 171 int8_t DeltaQPForSadZone2_S8; 172 int8_t DeltaQPForSadZone3_S8; 173 int8_t DeltaQPForROI0_S8; 174 int8_t DeltaQPForROI1_S8; 175 int8_t DeltaQPForROI2_S8; 176 int8_t DeltaQPForROI3_S8; 177 int8_t LumaLog2WeightDenom_S8; // default: 6 178 int8_t ChromaLog2WeightDenom_S8; // default: 6 179 uint8_t DisabledFeature_U8; 180 uint8_t SlidingWindow_Enable_U8; // 0-disabled, 1-enabled 181 uint8_t LOG_LCU_Size_U8; // 6 182 uint16_t NetworkTraceEntry_U16; // default: 0 183 uint16_t LowDelaySceneChangeXFrameSize_U16; // default: 0 184 int8_t ReEncodePositiveQPDeltaThr_S8; // default: 4 185 int8_t ReEncodeNegativeQPDeltaThr_S8; // default: -10 186 187 // tile-based BRC 188 uint8_t MaxNumTileHuCCallMinus1; // maximal tile row 189 uint8_t TileHucCallIndex; 190 uint8_t TileHuCCallPassIndex; // Start from 1 191 uint8_t TileHuCCallPassMax; // Reserved now 192 uint16_t TileSizeInLCU; 193 194 uint32_t TxSizeInBitsPerFrame; 195 196 uint8_t StartTileIdx; 197 uint8_t EndTileIdx; 198 199 uint16_t NumFrameSkipped; 200 uint32_t SkipFrameSize; 201 202 uint32_t SliceHeaderSize; 203 uint8_t IsLongTermRef; 204 205 uint8_t EnableMotionAdaptive; 206 uint8_t EnableLookAhead; 207 uint8_t UPD_CQMEnabled_U8; // 0 indicates CQM is disabled for current frame; otherwise CQM is enabled 208 }; 209 C_ASSERT(192 == sizeof(CODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G12)); 210 211 using PCODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G12 = CODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G12*; 212 213 struct CODECHAL_VDENC_HEVC_HUC_BRC_CONSTANT_DATA_G12 214 { 215 uint16_t SADQPLambdaI[52]; 216 uint16_t SADQPLambdaP[52]; 217 uint16_t RDQPLambdaI[52]; 218 uint16_t RDQPLambdaP[52]; 219 uint16_t SLCSZ_THRDELTAI_U16[52]; 220 uint16_t SLCSZ_THRDELTAP_U16[52]; 221 uint8_t DistThreshldI[9]; 222 uint8_t DistThreshldP[9]; 223 uint8_t DistThreshldB[9]; 224 int8_t DistQPAdjTabI[81]; 225 int8_t DistQPAdjTabP[81]; 226 int8_t DistQPAdjTabB[81]; 227 int8_t FrmSzAdjTabI_S8[72]; 228 int8_t FrmSzAdjTabP_S8[72]; 229 int8_t FrmSzAdjTabB_S8[72]; 230 uint8_t FrmSzMaxTabI[9]; 231 uint8_t FrmSzMaxTabP[9]; 232 uint8_t FrmSzMaxTabB[9]; 233 uint8_t FrmSzMinTabI[9]; 234 uint8_t FrmSzMinTabP[9]; 235 uint8_t FrmSzMinTabB[9]; 236 int8_t QPAdjTabI[45]; 237 int8_t QPAdjTabP[45]; 238 int8_t QPAdjTabB[45]; 239 struct 240 { 241 uint8_t I_INTRA_64X64DC; // added later since I frame needs to be setup differently 242 uint8_t I_INTRA_32x32; 243 uint8_t I_INTRA_16x16; 244 uint8_t I_INTRA_8x8; 245 uint8_t I_INTRA_SADMPM; 246 uint8_t I_INTRA_RDEMPM; 247 uint8_t I_INTRA_NxN; 248 uint8_t INTRA_64X64DC; 249 uint8_t INTRA_32x32; 250 uint8_t INTRA_16x16; 251 uint8_t INTRA_8x8; 252 uint8_t INTRA_SADMPM; 253 uint8_t INTRA_RDEMPM; 254 uint8_t INTRA_NxN; 255 uint8_t INTER_32x32; 256 uint8_t INTER_32x16; 257 uint8_t INTER_16x16; 258 uint8_t INTER_16x8; 259 uint8_t INTER_8x8; 260 uint8_t REF_ID; 261 uint8_t MERGE_64X64; 262 uint8_t MERGE_32X32; 263 uint8_t MERGE_16x16; 264 uint8_t MERGE_8x8; 265 uint8_t SKIP_64X64; 266 uint8_t SKIP_32X32; 267 uint8_t SKIP_16x16; 268 uint8_t SKIP_8x8; 269 } ModeCosts[52]; 270 struct 271 { 272 // Unit in Bytes 273 uint16_t SizeOfCMDs; 274 uint16_t HcpWeightOffsetL0_StartInBytes; // HCP_WEIGHTOFFSET_L0 starts in bytes from beginning of the SLB. 0xFFFF means unavailable in SLB 275 uint16_t HcpWeightOffsetL1_StartInBytes; // HCP_WEIGHTOFFSET_L1 starts in bytes from beginning of the SLB. 0xFFFF means unavailable in SLB 276 uint16_t SliceState_StartInBytes; 277 uint16_t SliceHeaderPIO_StartInBytes; 278 uint16_t VdencWeightOffset_StartInBytes; 279 // Unit in Bits 280 uint16_t SliceHeader_SizeInBits; 281 uint16_t WeightTable_StartInBits; // number of bits from beginning of slice header for weight table first bit, 0xffff means not awailable 282 uint16_t WeightTable_EndInBits; // number of bits from beginning of slice header for weight table last bit, 0xffff means not awailable 283 } Slice[CODECHAL_VDENC_HEVC_MAX_SLICE_NUM]; 284 uint8_t PenaltyForIntraNonDC32x32PredMode[52]; 285 uint32_t UPD_TR_TargetSize_U32; //TR_BRC 286 uint32_t UPD_LA_TargetFulness_U32; //LOOK_AHEAD 287 uint8_t UPD_deltaQP; 288 uint8_t UPD_TCBRC_SCENARIO_U8; // Unite scenario is 1, other is 0 289 uint8_t UPD_ROM_CURRENT_U8; // ROM average of current frame 290 uint8_t UPD_ROM_ZERO_U8; // ROM zero percentage (255 is 100%) 291 }; 292 293 using PCODECHAL_VDENC_HEVC_HUC_BRC_CONSTANT_DATA_G12 = CODECHAL_VDENC_HEVC_HUC_BRC_CONSTANT_DATA_G12*; 294 295 //! 296 //! \struct HucPakStitchDmemVdencG12 297 //! \brief The struct of Huc Com Dmem 298 //! 299 struct HucPakStitchDmemVdencG12 300 { 301 uint32_t TileSizeRecord_offset[5]; // Tile Size Records, start offset in byte, 0xffffffff means unavailable 302 uint32_t VDENCSTAT_offset[5]; // needed for HEVC VDEnc, VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 303 uint32_t HEVC_PAKSTAT_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 304 uint32_t HEVC_Streamout_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 305 uint32_t VP9_PAK_STAT_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 306 uint32_t Vp9CounterBuffer_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 307 uint32_t LastTileBS_StartInBytes;// last tile in bitstream for region 4 and region 5 308 uint32_t SliceHeaderSizeinBits; // needed for HEVC dual pipe BRC 309 uint16_t TotalSizeInCommandBuffer; // Total size in bytes of valid data in the command buffer 310 uint16_t OffsetInCommandBuffer; // Byte offset of the to-be-updated Length (uint32_t) in the command buffer, 0xffff means unavailable 311 uint16_t PicWidthInPixel; // Picture width in pixel 312 uint16_t PicHeightInPixel; // Picture hieght in pixel 313 uint16_t TotalNumberOfPAKs; // [2..4] 314 uint16_t NumSlices[4]; // this is number of slices from each PAK 315 uint16_t NumTiles[4]; // this is number of tiles from each PAK 316 uint16_t PIC_STATE_StartInBytes;// offset for region 7 and region 8 317 uint8_t Codec; // 1: HEVC DP; 2: HEVC VDEnc; 3: VP9 VDEnc 318 uint8_t MAXPass; // Max number of BRC pass >=1 319 uint8_t CurrentPass; // Current BRC pass [1..MAXPass] 320 uint8_t MinCUSize; // Minimum CU size (3: 8x8, 4:16x16), HEVC only. 321 uint8_t CabacZeroWordFlag; // cabac zero flag, HEVC only 322 uint8_t bitdepth_luma; // luma bitdepth, HEVC only 323 uint8_t bitdepth_chroma; // chroma bitdepth, HEVC only 324 uint8_t ChromaFormatIdc; // chroma format idc, HEVC only 325 uint8_t currFrameBRClevel; // Hevc dual pipe only 326 uint8_t brcUnderFlowEnable; // Hevc dual pipe only 327 uint8_t StitchEnable;// enable stitch cmd for Hevc dual pipe 328 uint8_t reserved1; 329 uint16_t StitchCommandOffset; // offset in region 10 which is the second level batch buffer 330 uint16_t reserved2; 331 uint32_t BBEndforStitch; 332 uint8_t RSVD[16]; 333 }; 334 335 //! 336 //! \struct HucInputCmdG12 337 //! \brief The struct of Huc input command 338 //! 339 struct HucInputCmdVdencG12 340 { 341 uint8_t SelectionForIndData = 0; 342 uint8_t CmdMode = 0; 343 uint16_t LengthOfTable = 0; 344 345 uint32_t SrcBaseOffset = 0; 346 uint32_t DestBaseOffset = 0; 347 348 uint32_t Reserved[3] = { 0 }; 349 350 uint32_t CopySize = 0; // use this as indicator of size for copy base addr cmd. Since encode will not implement CopySize for copy cmd 351 352 uint32_t ReservedCounter[4] = {0}; 353 354 uint32_t SrcAddrBottom = 0; 355 uint32_t SrcAddrTop = 0; 356 uint32_t DestAddrBottom = 0; 357 uint32_t DestAddrTop = 0; 358 }; 359 360 //! 361 //! \struct HucCommandData 362 //! \brief The struct of Huc commands data 363 //! 364 struct HucCommandDataVdencG12 365 { 366 uint32_t TotalCommands; //!< Total Commands in the Data buffer 367 struct 368 { 369 uint16_t ID; //!< Command ID, defined and order must be same as that in DMEM 370 uint16_t SizeOfData; //!< data size in uint32_t 371 uint32_t data[40]; 372 } InputCOM[10]; 373 }; 374 375 struct CODECHAL_VDENC_HEVC_STREAMIN_STATE_G12 376 { 377 // DWORD 0 378 union { 379 struct { 380 uint32_t RoiCtrl : MOS_BITFIELD_RANGE(0, 7); 381 uint32_t MaxTuSize : MOS_BITFIELD_RANGE(8, 9); 382 uint32_t MaxCuSize : MOS_BITFIELD_RANGE(10, 11); 383 uint32_t NumImePredictors : MOS_BITFIELD_RANGE(12, 15); 384 uint32_t Reserved_0 : MOS_BITFIELD_RANGE(16, 20); 385 uint32_t ForceQPDelta : MOS_BITFIELD_BIT(21); 386 uint32_t PaletteDisable : MOS_BITFIELD_BIT(22); 387 uint32_t Reserved_1 : MOS_BITFIELD_BIT(23); 388 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE(24, 31); 389 }; 390 uint32_t Value; 391 } DW0; 392 393 // DWORD 1-4 394 union { 395 struct { 396 uint32_t ForceMvX : MOS_BITFIELD_RANGE(0, 15); 397 uint32_t ForceMvY : MOS_BITFIELD_RANGE(16, 31); 398 }; 399 uint32_t Value; 400 } DW1[4]; 401 402 // DWORD 5 403 union { 404 struct { 405 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31); 406 }; 407 uint32_t Value; 408 } DW5; 409 410 // DWORD 6 411 union { 412 struct { 413 uint32_t ForceRefIdx : MOS_BITFIELD_RANGE(0, 15); //4-bits per 16x16 block 414 uint32_t NumMergeCandidateCu8x8 : MOS_BITFIELD_RANGE(16, 19); 415 uint32_t NumMergeCandidateCu16x16 : MOS_BITFIELD_RANGE(20, 23); 416 uint32_t NumMergeCandidateCu32x32 : MOS_BITFIELD_RANGE(24, 27); 417 uint32_t NumMergeCandidateCu64x64 : MOS_BITFIELD_RANGE(28, 31); 418 }; 419 uint32_t Value; 420 } DW6; 421 422 // DWORD 7 423 union { 424 struct { 425 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); //4-bits per 16x16 block 426 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 427 uint32_t SegIDEnable : MOS_BITFIELD_RANGE(20, 20); 428 uint32_t Reserved : MOS_BITFIELD_RANGE(21, 22); 429 uint32_t ForceRefIdEnable : MOS_BITFIELD_RANGE(23, 23); 430 uint32_t ImePredictorSelect : MOS_BITFIELD_RANGE(24, 31); 431 }; 432 uint32_t Value; 433 } DW7; 434 435 // DWORD 8-11 436 union { 437 struct { 438 uint32_t ImePredictorMvX : MOS_BITFIELD_RANGE(0, 15); 439 uint32_t ImePredictorMvY : MOS_BITFIELD_RANGE(16, 31); 440 }; 441 uint32_t Value; 442 } DW8[4]; 443 444 // DWORD 12 445 union { 446 struct { 447 uint32_t ImePredictorRefIdx : MOS_BITFIELD_RANGE(0, 15); //4-bits per 16x16 block 448 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 449 }; 450 uint32_t Value; 451 } DW12; 452 453 // DWORD 13 454 union { 455 struct { 456 uint32_t PanicModeLCUThreshold : MOS_BITFIELD_RANGE(0, 15); 457 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 458 }; 459 uint32_t Value; 460 } DW13; 461 462 // DWORD 14 463 union { 464 struct { 465 uint32_t ForceQp_0 : MOS_BITFIELD_RANGE(0, 7); 466 uint32_t ForceQp_1 : MOS_BITFIELD_RANGE(8, 15); 467 uint32_t ForceQp_2 : MOS_BITFIELD_RANGE(16, 23); 468 uint32_t ForceQp_3 : MOS_BITFIELD_RANGE(24, 31); 469 }; 470 uint32_t Value; 471 } DW14; 472 473 // DWORD 15 474 union { 475 struct { 476 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31); 477 }; 478 uint32_t Value; 479 } DW15; 480 }; 481 C_ASSERT(SIZE32(CODECHAL_VDENC_HEVC_STREAMIN_STATE_G12) == 16); 482 483 using PCODECHAL_VDENC_HEVC_STREAMIN_STATE_G12 = CODECHAL_VDENC_HEVC_STREAMIN_STATE_G12*; 484 485 const uint32_t ME_CURBE_INIT_G12[48] = 486 { 487 0x00000000, 0x00200010, 0x00003939, 0x77a43000, 0x00000000, 0x28300000, 0x00000000, 0x00000000, 488 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 489 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 490 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 491 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 492 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff 493 }; 494 495 enum CODECHAL_BINDING_TABLE_OFFSET_HEVC_VP9_VDENC_KERNEL_G12 496 { 497 // VDEnc HME kernel 498 CODECHAL_VDENC_HME_BEGIN_G12 = 0, 499 CODECHAL_VDENC_HME_MV_DATA_SURFACE_CM_G12 = CODECHAL_VDENC_HME_BEGIN_G12, 500 CODECHAL_VDENC_16xME_MV_DATA_SURFACE_CM_G12, 501 CODECHAL_VDENC_32xME_MV_DATA_SURFACE_CM_G12 = CODECHAL_VDENC_16xME_MV_DATA_SURFACE_CM_G12, 502 CODECHAL_VDENC_HME_DISTORTION_SURFACE_CM_G12, 503 CODECHAL_VDENC_HME_BRC_DISTORTION_CM_G12, 504 CODECHAL_VDENC_HME_CURR_FOR_FWD_REF_CM_G12, 505 CODECHAL_VDENC_HME_FWD_REF_IDX0_CM_G12, 506 CODECHAL_VDENC_HME_RESERVED1_CM_G12, 507 CODECHAL_VDENC_HME_FWD_REF_IDX1_CM_G12, 508 CODECHAL_VDENC_HME_RESERVED2_CM_G12, 509 CODECHAL_VDENC_HME_FWD_REF_IDX2_CM_G12, 510 CODECHAL_VDENC_HME_RESERVED3_CM_G12, 511 CODECHAL_VDENC_HME_FWD_REF_IDX3_CM_G12, 512 CODECHAL_VDENC_HME_RESERVED4_CM_G12, 513 CODECHAL_VDENC_HME_FWD_REF_IDX4_CM_G12, 514 CODECHAL_VDENC_HME_RESERVED5_CM_G12, 515 CODECHAL_VDENC_HME_FWD_REF_IDX5_CM_G12, 516 CODECHAL_VDENC_HME_RESERVED6_CM_G12, 517 CODECHAL_VDENC_HME_FWD_REF_IDX6_CM_G12, 518 CODECHAL_VDENC_HME_RESERVED7_CM_G12, 519 CODECHAL_VDENC_HME_FWD_REF_IDX7_CM_G12, 520 CODECHAL_VDENC_HME_RESERVED8_CM_G12, 521 CODECHAL_VDENC_HME_CURR_FOR_BWD_REF_CM_G12, 522 CODECHAL_VDENC_HME_BWD_REF_IDX0_CM_G12, 523 CODECHAL_VDENC_HME_RESERVED9_CM_G12, 524 CODECHAL_VDENC_HME_BWD_REF_IDX1_CM_G12, 525 CODECHAL_VDENC_HME_RESERVED10_CM_G12, 526 CODECHAL_VDENC_HME_VDENC_STREAMIN_OUTPUT_CM_G12, 527 CODECHAL_VDENC_HME_VDENC_STREAMIN_INPUT_CM_G12, 528 CODECHAL_VDENC_HME_END_G12, 529 }; 530 531 enum SCC_IBC_CONTROL_IBC_G12 532 { 533 SCC_IBC_CONTROL_IBC_DISABLED_G12 = 0x0, 534 SCC_IBC_CONTROL_IBC_ONLY_LBC_G12 = 0x1, 535 SCC_IBC_CONTROL_IBC_ENABLED_TBCLBC_G12 = 0x3, 536 }; 537 538 struct MEDIA_OBJECT_HEVC_VP9_VDENC_ME_CURBE_G12 539 { 540 // DW0 541 union 542 { 543 struct 544 { 545 uint32_t SkipModeEn : MOS_BITFIELD_BIT(0); 546 uint32_t AdaptiveEn : MOS_BITFIELD_BIT(1); 547 uint32_t BiMixDis : MOS_BITFIELD_BIT(2); 548 uint32_t : MOS_BITFIELD_RANGE(3, 4); 549 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT(5); 550 uint32_t : MOS_BITFIELD_BIT(6); 551 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT(7); 552 uint32_t : MOS_BITFIELD_RANGE(8, 23); 553 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE(24, 31); 554 }; 555 struct 556 { 557 uint32_t Value; 558 }; 559 } DW0; 560 561 // DW1 562 union 563 { 564 struct 565 { 566 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE(0, 5); 567 uint32_t : MOS_BITFIELD_RANGE(6, 15); 568 uint32_t BiWeight : MOS_BITFIELD_RANGE(16, 21); 569 uint32_t : MOS_BITFIELD_RANGE(22, 27); 570 uint32_t UniMixDisable : MOS_BITFIELD_BIT(28); 571 uint32_t : MOS_BITFIELD_RANGE(29, 31); 572 }; 573 struct 574 { 575 uint32_t Value; 576 }; 577 } DW1; 578 579 // DW2 580 union 581 { 582 struct 583 { 584 uint32_t MaxLenSP : MOS_BITFIELD_RANGE(0, 7); 585 uint32_t MaxNumSU : MOS_BITFIELD_RANGE(8, 15); 586 uint32_t : MOS_BITFIELD_RANGE(16, 31); 587 }; 588 struct 589 { 590 uint32_t Value; 591 }; 592 } DW2; 593 594 // DW3 595 union 596 { 597 struct 598 { 599 uint32_t SrcSize : MOS_BITFIELD_RANGE(0, 1); 600 uint32_t : MOS_BITFIELD_RANGE(2, 3); 601 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE(4, 5); 602 uint32_t SrcAccess : MOS_BITFIELD_BIT(6); 603 uint32_t RefAccess : MOS_BITFIELD_BIT(7); 604 uint32_t SearchCtrl : MOS_BITFIELD_RANGE(8, 10); 605 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT(11); 606 uint32_t SubPelMode : MOS_BITFIELD_RANGE(12, 13); 607 uint32_t SkipType : MOS_BITFIELD_BIT(14); 608 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT(15); 609 uint32_t InterChromaMode : MOS_BITFIELD_BIT(16); 610 uint32_t FTEnable : MOS_BITFIELD_BIT(17); 611 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT(18); 612 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT(19); 613 uint32_t InterSAD : MOS_BITFIELD_RANGE(20, 21); 614 uint32_t IntraSAD : MOS_BITFIELD_RANGE(22, 23); 615 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE(24, 30); 616 uint32_t : MOS_BITFIELD_BIT(31); 617 }; 618 struct 619 { 620 uint32_t Value; 621 }; 622 } DW3; 623 624 // DW4 625 union 626 { 627 struct 628 { 629 uint32_t : MOS_BITFIELD_RANGE(0, 7); 630 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE(8, 15); 631 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 632 uint32_t: MOS_BITFIELD_RANGE(24, 31); 633 }; 634 struct 635 { 636 uint32_t Value; 637 }; 638 } DW4; 639 640 // DW5 641 union 642 { 643 struct 644 { 645 uint32_t : MOS_BITFIELD_RANGE(0, 7); 646 uint32_t QpPrimeY : MOS_BITFIELD_RANGE(8, 15); 647 uint32_t RefWidth : MOS_BITFIELD_RANGE(16, 23); 648 uint32_t RefHeight : MOS_BITFIELD_RANGE(24, 31); 649 }; 650 struct 651 { 652 uint32_t Value; 653 }; 654 } DW5; 655 656 // DW6 657 union 658 { 659 struct 660 { 661 uint32_t : MOS_BITFIELD_BIT(0); 662 uint32_t InputStreamInEn : MOS_BITFIELD_BIT(1); 663 uint32_t LCUSize : MOS_BITFIELD_BIT(2); 664 uint32_t WriteDistortions : MOS_BITFIELD_BIT(3); 665 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT(4); 666 uint32_t : MOS_BITFIELD_RANGE(5, 7); 667 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE(8, 15); 668 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 669 }; 670 struct 671 { 672 uint32_t Value; 673 }; 674 } DW6; 675 676 // DW7 677 union 678 { 679 struct 680 { 681 uint32_t : MOS_BITFIELD_RANGE(0, 15); 682 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE(16, 17); 683 uint32_t BilinearEnable : MOS_BITFIELD_BIT(18); 684 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT(19); 685 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT(20); 686 uint32_t AConlyHAAR : MOS_BITFIELD_BIT(21); 687 uint32_t RefIDCostMode : MOS_BITFIELD_BIT(22); 688 uint32_t : MOS_BITFIELD_BIT(23); 689 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE(24, 31); 690 }; 691 struct 692 { 693 uint32_t Value; 694 }; 695 } DW7; 696 697 // DW8 698 union 699 { 700 struct 701 { 702 uint32_t Mode0Cost : MOS_BITFIELD_RANGE(0, 7); 703 uint32_t Mode1Cost : MOS_BITFIELD_RANGE(8, 15); 704 uint32_t Mode2Cost : MOS_BITFIELD_RANGE(16, 23); 705 uint32_t Mode3Cost : MOS_BITFIELD_RANGE(24, 31); 706 }; 707 struct 708 { 709 uint32_t Value; 710 }; 711 } DW8; 712 713 // DW9 714 union 715 { 716 struct 717 { 718 uint32_t Mode4Cost : MOS_BITFIELD_RANGE(0, 7); 719 uint32_t Mode5Cost : MOS_BITFIELD_RANGE(8, 15); 720 uint32_t Mode6Cost : MOS_BITFIELD_RANGE(16, 23); 721 uint32_t Mode7Cost : MOS_BITFIELD_RANGE(24, 31); 722 }; 723 struct 724 { 725 uint32_t Value; 726 }; 727 } DW9; 728 729 // DW10 730 union 731 { 732 struct 733 { 734 uint32_t Mode8Cost : MOS_BITFIELD_RANGE(0, 7); 735 uint32_t Mode9Cost : MOS_BITFIELD_RANGE(8, 15); 736 uint32_t RefIDCost : MOS_BITFIELD_RANGE(16, 23); 737 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE(24, 31); 738 }; 739 struct 740 { 741 uint32_t Value; 742 }; 743 } DW10; 744 745 // DW11 746 union 747 { 748 struct 749 { 750 uint32_t MV0Cost : MOS_BITFIELD_RANGE(0, 7); 751 uint32_t MV1Cost : MOS_BITFIELD_RANGE(8, 15); 752 uint32_t MV2Cost : MOS_BITFIELD_RANGE(16, 23); 753 uint32_t MV3Cost : MOS_BITFIELD_RANGE(24, 31); 754 }; 755 struct 756 { 757 uint32_t Value; 758 }; 759 } DW11; 760 761 // DW12 762 union 763 { 764 struct 765 { 766 uint32_t MV4Cost : MOS_BITFIELD_RANGE(0, 7); 767 uint32_t MV5Cost : MOS_BITFIELD_RANGE(8, 15); 768 uint32_t MV6Cost : MOS_BITFIELD_RANGE(16, 23); 769 uint32_t MV7Cost : MOS_BITFIELD_RANGE(24, 31); 770 }; 771 struct 772 { 773 uint32_t Value; 774 }; 775 } DW12; 776 777 // DW13 778 union 779 { 780 struct 781 { 782 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE(0, 7); 783 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE(8, 15); 784 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 785 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 786 uint32_t : MOS_BITFIELD_RANGE(27, 31); 787 }; 788 struct 789 { 790 uint32_t Value; 791 }; 792 } DW13; 793 794 // DW14 795 union 796 { 797 struct 798 { 799 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT(0); 800 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT(1); 801 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT(2); 802 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT(3); 803 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT(4); 804 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT(5); 805 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT(6); 806 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT(7); 807 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT(8); 808 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT(9); 809 uint32_t : MOS_BITFIELD_RANGE(10, 31); 810 }; 811 struct 812 { 813 uint32_t Value; 814 }; 815 } DW14; 816 817 // DW15 818 union 819 { 820 struct 821 { 822 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE(0, 7); 823 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE(8, 15); 824 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 825 }; 826 struct 827 { 828 uint32_t Value; 829 }; 830 } DW15; 831 832 struct 833 { 834 // DW16 835 union 836 { 837 struct 838 { 839 SearchPathDelta SPDelta_0; 840 SearchPathDelta SPDelta_1; 841 SearchPathDelta SPDelta_2; 842 SearchPathDelta SPDelta_3; 843 }; 844 struct 845 { 846 uint32_t Value; 847 }; 848 } DW16; 849 850 // DW17 851 union 852 { 853 struct 854 { 855 SearchPathDelta SPDelta_4; 856 SearchPathDelta SPDelta_5; 857 SearchPathDelta SPDelta_6; 858 SearchPathDelta SPDelta_7; 859 }; 860 struct 861 { 862 uint32_t Value; 863 }; 864 } DW17; 865 866 // DW18 867 union 868 { 869 struct 870 { 871 SearchPathDelta SPDelta_8; 872 SearchPathDelta SPDelta_9; 873 SearchPathDelta SPDelta_10; 874 SearchPathDelta SPDelta_11; 875 }; 876 struct 877 { 878 uint32_t Value; 879 }; 880 } DW18; 881 882 // DW19 883 union 884 { 885 struct 886 { 887 SearchPathDelta SPDelta_12; 888 SearchPathDelta SPDelta_13; 889 SearchPathDelta SPDelta_14; 890 SearchPathDelta SPDelta_15; 891 }; 892 struct 893 { 894 uint32_t Value; 895 }; 896 } DW19; 897 898 // DW20 899 union 900 { 901 struct 902 { 903 SearchPathDelta SPDelta_16; 904 SearchPathDelta SPDelta_17; 905 SearchPathDelta SPDelta_18; 906 SearchPathDelta SPDelta_19; 907 }; 908 struct 909 { 910 uint32_t Value; 911 }; 912 } DW20; 913 914 // DW21 915 union 916 { 917 struct 918 { 919 SearchPathDelta SPDelta_20; 920 SearchPathDelta SPDelta_21; 921 SearchPathDelta SPDelta_22; 922 SearchPathDelta SPDelta_23; 923 }; 924 struct 925 { 926 uint32_t Value; 927 }; 928 } DW21; 929 930 // DW22 931 union 932 { 933 struct 934 { 935 SearchPathDelta SPDelta_24; 936 SearchPathDelta SPDelta_25; 937 SearchPathDelta SPDelta_26; 938 SearchPathDelta SPDelta_27; 939 }; 940 struct 941 { 942 uint32_t Value; 943 }; 944 } DW22; 945 946 // DW23 947 union 948 { 949 struct 950 { 951 SearchPathDelta SPDelta_28; 952 SearchPathDelta SPDelta_29; 953 SearchPathDelta SPDelta_30; 954 SearchPathDelta SPDelta_31; 955 }; 956 struct 957 { 958 uint32_t Value; 959 }; 960 } DW23; 961 962 // DW24 963 union 964 { 965 struct 966 { 967 SearchPathDelta SPDelta_32; 968 SearchPathDelta SPDelta_33; 969 SearchPathDelta SPDelta_34; 970 SearchPathDelta SPDelta_35; 971 }; 972 struct 973 { 974 uint32_t Value; 975 }; 976 } DW24; 977 978 // DW25 979 union 980 { 981 struct 982 { 983 SearchPathDelta SPDelta_36; 984 SearchPathDelta SPDelta_37; 985 SearchPathDelta SPDelta_38; 986 SearchPathDelta SPDelta_39; 987 }; 988 struct 989 { 990 uint32_t Value; 991 }; 992 } DW25; 993 994 // DW26 995 union 996 { 997 struct 998 { 999 SearchPathDelta SPDelta_40; 1000 SearchPathDelta SPDelta_41; 1001 SearchPathDelta SPDelta_42; 1002 SearchPathDelta SPDelta_43; 1003 }; 1004 struct 1005 { 1006 uint32_t Value; 1007 }; 1008 } DW26; 1009 1010 // DW27 1011 union 1012 { 1013 struct 1014 { 1015 SearchPathDelta SPDelta_44; 1016 SearchPathDelta SPDelta_45; 1017 SearchPathDelta SPDelta_46; 1018 SearchPathDelta SPDelta_47; 1019 }; 1020 struct 1021 { 1022 uint32_t Value; 1023 }; 1024 } DW27; 1025 1026 // DW28 1027 union 1028 { 1029 struct 1030 { 1031 SearchPathDelta SPDelta_48; 1032 SearchPathDelta SPDelta_49; 1033 SearchPathDelta SPDelta_50; 1034 SearchPathDelta SPDelta_51; 1035 }; 1036 struct 1037 { 1038 uint32_t Value; 1039 }; 1040 } DW28; 1041 1042 // DW29 1043 union 1044 { 1045 struct 1046 { 1047 SearchPathDelta SPDelta_52; 1048 SearchPathDelta SPDelta_53; 1049 SearchPathDelta SPDelta_54; 1050 SearchPathDelta SPDelta_55; 1051 }; 1052 struct 1053 { 1054 uint32_t Value; 1055 }; 1056 } DW29; 1057 } SPDelta; 1058 1059 // DW30 1060 union 1061 { 1062 struct 1063 { 1064 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE(0, 15); 1065 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 1066 }; 1067 struct 1068 { 1069 uint32_t Value; 1070 }; 1071 } DW30; 1072 1073 // DW31 1074 union 1075 { 1076 struct 1077 { 1078 uint32_t RoiCtrl : MOS_BITFIELD_RANGE(0, 7); 1079 uint32_t MaxTuSize : MOS_BITFIELD_RANGE(8, 9); 1080 uint32_t MaxCuSize : MOS_BITFIELD_RANGE(10, 11); 1081 uint32_t NumImePredictors : MOS_BITFIELD_RANGE(12, 15); 1082 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 23); 1083 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE(24, 31); 1084 }; 1085 struct 1086 { 1087 uint32_t Value; 1088 }; 1089 } DW31; 1090 1091 // DW32 1092 union 1093 { 1094 struct 1095 { 1096 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE(0, 15); 1097 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 1098 }; 1099 struct 1100 { 1101 uint32_t Value; 1102 }; 1103 } DW32; 1104 1105 // DW33 1106 union 1107 { 1108 struct 1109 { 1110 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE(0, 15); 1111 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 1112 }; 1113 struct 1114 { 1115 uint32_t Value; 1116 }; 1117 } DW33; 1118 1119 // DW34 1120 union 1121 { 1122 struct 1123 { 1124 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE(0, 15); 1125 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 1126 }; 1127 struct 1128 { 1129 uint32_t Value; 1130 }; 1131 } DW34; 1132 1133 // DW35 1134 union 1135 { 1136 struct 1137 { 1138 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE(0, 15); 1139 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 1140 }; 1141 struct 1142 { 1143 uint32_t Value; 1144 }; 1145 } DW35; 1146 1147 // DW36 1148 union 1149 { 1150 struct 1151 { 1152 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE(0, 3); 1153 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE(4, 7); 1154 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE(8, 11); 1155 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 1156 uint32_t NumMergeCandCu8x8 : MOS_BITFIELD_RANGE(16, 19); 1157 uint32_t NumMergeCandCu16x16 : MOS_BITFIELD_RANGE(20, 23); 1158 uint32_t NumMergeCandCu32x32 : MOS_BITFIELD_RANGE(24, 27); 1159 uint32_t NumMergeCandCu64x64 : MOS_BITFIELD_RANGE(28, 31); 1160 }; 1161 struct 1162 { 1163 uint32_t Value; 1164 }; 1165 } DW36; 1166 1167 // DW37 1168 union 1169 { 1170 struct 1171 { 1172 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); 1173 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 1174 uint32_t SegIDEnable : MOS_BITFIELD_BIT(20); 1175 uint32_t Reserved : MOS_BITFIELD_RANGE(21, 22); 1176 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT(23); 1177 uint32_t Reserved1 : MOS_BITFIELD_RANGE(24, 31); 1178 }; 1179 struct 1180 { 1181 uint32_t Value; 1182 }; 1183 } DW37; 1184 1185 // DW38 1186 union 1187 { 1188 struct 1189 { 1190 uint32_t ForceQp0 : MOS_BITFIELD_RANGE(0, 7); 1191 uint32_t ForceQp1 : MOS_BITFIELD_RANGE(8, 15); 1192 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 1193 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(24, 31); 1194 }; 1195 struct 1196 { 1197 uint32_t Value; 1198 }; 1199 } DW38; 1200 1201 // DW39 1202 union 1203 { 1204 struct 1205 { 1206 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31); 1207 }; 1208 struct 1209 { 1210 uint32_t Value; 1211 }; 1212 } DW39; 1213 1214 // DW40 1215 union 1216 { 1217 struct 1218 { 1219 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1220 }; 1221 struct 1222 { 1223 uint32_t Value; 1224 }; 1225 } DW40; 1226 1227 // DW41 1228 union 1229 { 1230 struct 1231 { 1232 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1233 }; 1234 struct 1235 { 1236 uint32_t Value; 1237 }; 1238 } DW41; 1239 1240 // DW42 1241 union 1242 { 1243 struct 1244 { 1245 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1246 }; 1247 struct 1248 { 1249 uint32_t Value; 1250 }; 1251 } DW42; 1252 1253 // DW43 1254 union 1255 { 1256 struct 1257 { 1258 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1259 }; 1260 struct 1261 { 1262 uint32_t Value; 1263 }; 1264 } DW43; 1265 1266 // DW44 1267 union 1268 { 1269 struct 1270 { 1271 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1272 }; 1273 struct 1274 { 1275 uint32_t Value; 1276 }; 1277 } DW44; 1278 1279 // DW45 1280 union 1281 { 1282 struct 1283 { 1284 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1285 }; 1286 struct 1287 { 1288 uint32_t Value; 1289 }; 1290 } DW45; 1291 1292 // DW46 1293 union 1294 { 1295 struct 1296 { 1297 uint32_t VDEncStreamInOutputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1298 }; 1299 struct 1300 { 1301 uint32_t Value; 1302 }; 1303 } DW46; 1304 1305 // DW47 1306 union 1307 { 1308 struct 1309 { 1310 uint32_t VDEncStreamInInputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1311 }; 1312 struct 1313 { 1314 uint32_t Value; 1315 }; 1316 } DW47; 1317 }; 1318 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(MEDIA_OBJECT_HEVC_VP9_VDENC_ME_CURBE_G12)) == 48); 1319 1320 struct CODECHAL_VDENC_HEVC_ME_CURBE_G12 1321 { 1322 // DW0 1323 union 1324 { 1325 struct 1326 { 1327 uint32_t SkipModeEn : MOS_BITFIELD_BIT(0); 1328 uint32_t AdaptiveEn : MOS_BITFIELD_BIT(1); 1329 uint32_t BiMixDis : MOS_BITFIELD_BIT(2); 1330 uint32_t : MOS_BITFIELD_RANGE(3, 4); 1331 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT(5); 1332 uint32_t : MOS_BITFIELD_BIT(6); 1333 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT(7); 1334 uint32_t : MOS_BITFIELD_RANGE(8, 23); 1335 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE(24, 31); 1336 }; 1337 struct 1338 { 1339 uint32_t Value; 1340 }; 1341 } DW0; 1342 1343 // DW1 1344 union 1345 { 1346 struct 1347 { 1348 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE(0, 5); 1349 uint32_t : MOS_BITFIELD_RANGE(6, 15); 1350 uint32_t BiWeight : MOS_BITFIELD_RANGE(16, 21); 1351 uint32_t : MOS_BITFIELD_RANGE(22, 27); 1352 uint32_t UniMixDisable : MOS_BITFIELD_BIT(28); 1353 uint32_t : MOS_BITFIELD_RANGE(29, 31); 1354 }; 1355 struct 1356 { 1357 uint32_t Value; 1358 }; 1359 } DW1; 1360 1361 // DW2 1362 union 1363 { 1364 struct 1365 { 1366 uint32_t MaxLenSP : MOS_BITFIELD_RANGE(0, 7); 1367 uint32_t MaxNumSU : MOS_BITFIELD_RANGE(8, 15); 1368 uint32_t : MOS_BITFIELD_RANGE(16, 31); 1369 }; 1370 struct 1371 { 1372 uint32_t Value; 1373 }; 1374 } DW2; 1375 1376 // DW3 1377 union 1378 { 1379 struct 1380 { 1381 uint32_t SrcSize : MOS_BITFIELD_RANGE(0, 1); 1382 uint32_t : MOS_BITFIELD_RANGE(2, 3); 1383 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE(4, 5); 1384 uint32_t SrcAccess : MOS_BITFIELD_BIT(6); 1385 uint32_t RefAccess : MOS_BITFIELD_BIT(7); 1386 uint32_t SearchCtrl : MOS_BITFIELD_RANGE(8, 10); 1387 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT(11); 1388 uint32_t SubPelMode : MOS_BITFIELD_RANGE(12, 13); 1389 uint32_t SkipType : MOS_BITFIELD_BIT(14); 1390 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT(15); 1391 uint32_t InterChromaMode : MOS_BITFIELD_BIT(16); 1392 uint32_t FTEnable : MOS_BITFIELD_BIT(17); 1393 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT(18); 1394 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT(19); 1395 uint32_t InterSAD : MOS_BITFIELD_RANGE(20, 21); 1396 uint32_t IntraSAD : MOS_BITFIELD_RANGE(22, 23); 1397 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE(24, 30); 1398 uint32_t : MOS_BITFIELD_BIT(31); 1399 }; 1400 struct 1401 { 1402 uint32_t Value; 1403 }; 1404 } DW3; 1405 1406 // DW4 1407 union 1408 { 1409 struct 1410 { 1411 uint32_t : MOS_BITFIELD_RANGE(0, 7); 1412 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE(8, 15); 1413 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 1414 uint32_t : MOS_BITFIELD_RANGE(24, 31); 1415 }; 1416 struct 1417 { 1418 uint32_t Value; 1419 }; 1420 } DW4; 1421 1422 // DW5 1423 union 1424 { 1425 struct 1426 { 1427 uint32_t : MOS_BITFIELD_RANGE(0, 7); 1428 uint32_t QpPrimeY : MOS_BITFIELD_RANGE(8, 15); 1429 uint32_t RefWidth : MOS_BITFIELD_RANGE(16, 23); 1430 uint32_t RefHeight : MOS_BITFIELD_RANGE(24, 31); 1431 }; 1432 struct 1433 { 1434 uint32_t Value; 1435 }; 1436 } DW5; 1437 1438 // DW6 1439 union 1440 { 1441 struct 1442 { 1443 uint32_t : MOS_BITFIELD_BIT(0); 1444 uint32_t InputStreamInEn : MOS_BITFIELD_BIT(1); 1445 uint32_t LCUSize : MOS_BITFIELD_BIT(2); 1446 uint32_t WriteDistortions : MOS_BITFIELD_BIT(3); 1447 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT(4); 1448 uint32_t : MOS_BITFIELD_RANGE(5, 7); 1449 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE(8, 15); 1450 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 1451 }; 1452 struct 1453 { 1454 uint32_t Value; 1455 }; 1456 } DW6; 1457 1458 // DW7 1459 union 1460 { 1461 struct 1462 { 1463 uint32_t : MOS_BITFIELD_RANGE(0, 15); 1464 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE(16, 17); 1465 uint32_t BilinearEnable : MOS_BITFIELD_BIT(18); 1466 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT(19); 1467 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT(20); 1468 uint32_t AConlyHAAR : MOS_BITFIELD_BIT(21); 1469 uint32_t RefIDCostMode : MOS_BITFIELD_BIT(22); 1470 uint32_t : MOS_BITFIELD_BIT(23); 1471 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE(24, 31); 1472 }; 1473 struct 1474 { 1475 uint32_t Value; 1476 }; 1477 } DW7; 1478 1479 // DW8 1480 union 1481 { 1482 struct 1483 { 1484 uint32_t Mode0Cost : MOS_BITFIELD_RANGE(0, 7); 1485 uint32_t Mode1Cost : MOS_BITFIELD_RANGE(8, 15); 1486 uint32_t Mode2Cost : MOS_BITFIELD_RANGE(16, 23); 1487 uint32_t Mode3Cost : MOS_BITFIELD_RANGE(24, 31); 1488 }; 1489 struct 1490 { 1491 uint32_t Value; 1492 }; 1493 } DW8; 1494 1495 // DW9 1496 union 1497 { 1498 struct 1499 { 1500 uint32_t Mode4Cost : MOS_BITFIELD_RANGE(0, 7); 1501 uint32_t Mode5Cost : MOS_BITFIELD_RANGE(8, 15); 1502 uint32_t Mode6Cost : MOS_BITFIELD_RANGE(16, 23); 1503 uint32_t Mode7Cost : MOS_BITFIELD_RANGE(24, 31); 1504 }; 1505 struct 1506 { 1507 uint32_t Value; 1508 }; 1509 } DW9; 1510 1511 // DW10 1512 union 1513 { 1514 struct 1515 { 1516 uint32_t Mode8Cost : MOS_BITFIELD_RANGE(0, 7); 1517 uint32_t Mode9Cost : MOS_BITFIELD_RANGE(8, 15); 1518 uint32_t RefIDCost : MOS_BITFIELD_RANGE(16, 23); 1519 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE(24, 31); 1520 }; 1521 struct 1522 { 1523 uint32_t Value; 1524 }; 1525 } DW10; 1526 1527 // DW11 1528 union 1529 { 1530 struct 1531 { 1532 uint32_t MV0Cost : MOS_BITFIELD_RANGE(0, 7); 1533 uint32_t MV1Cost : MOS_BITFIELD_RANGE(8, 15); 1534 uint32_t MV2Cost : MOS_BITFIELD_RANGE(16, 23); 1535 uint32_t MV3Cost : MOS_BITFIELD_RANGE(24, 31); 1536 }; 1537 struct 1538 { 1539 uint32_t Value; 1540 }; 1541 } DW11; 1542 1543 // DW12 1544 union 1545 { 1546 struct 1547 { 1548 uint32_t MV4Cost : MOS_BITFIELD_RANGE(0, 7); 1549 uint32_t MV5Cost : MOS_BITFIELD_RANGE(8, 15); 1550 uint32_t MV6Cost : MOS_BITFIELD_RANGE(16, 23); 1551 uint32_t MV7Cost : MOS_BITFIELD_RANGE(24, 31); 1552 }; 1553 struct 1554 { 1555 uint32_t Value; 1556 }; 1557 } DW12; 1558 1559 // DW13 1560 union 1561 { 1562 struct 1563 { 1564 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE(0, 7); 1565 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE(8, 15); 1566 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 1567 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 1568 uint32_t : MOS_BITFIELD_RANGE(27, 31); 1569 }; 1570 struct 1571 { 1572 uint32_t Value; 1573 }; 1574 } DW13; 1575 1576 // DW14 1577 union 1578 { 1579 struct 1580 { 1581 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT(0); 1582 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT(1); 1583 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT(2); 1584 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT(3); 1585 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT(4); 1586 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT(5); 1587 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT(6); 1588 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT(7); 1589 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT(8); 1590 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT(9); 1591 uint32_t : MOS_BITFIELD_RANGE(10, 31); 1592 }; 1593 struct 1594 { 1595 uint32_t Value; 1596 }; 1597 } DW14; 1598 1599 // DW15 1600 union 1601 { 1602 struct 1603 { 1604 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE(0, 7); 1605 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE(8, 15); 1606 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 1607 }; 1608 struct 1609 { 1610 uint32_t Value; 1611 }; 1612 } DW15; 1613 1614 struct 1615 { 1616 // DW16 1617 union 1618 { 1619 struct 1620 { 1621 SearchPathDelta SPDelta_0; 1622 SearchPathDelta SPDelta_1; 1623 SearchPathDelta SPDelta_2; 1624 SearchPathDelta SPDelta_3; 1625 }; 1626 struct 1627 { 1628 uint32_t Value; 1629 }; 1630 } DW16; 1631 1632 // DW17 1633 union 1634 { 1635 struct 1636 { 1637 SearchPathDelta SPDelta_4; 1638 SearchPathDelta SPDelta_5; 1639 SearchPathDelta SPDelta_6; 1640 SearchPathDelta SPDelta_7; 1641 }; 1642 struct 1643 { 1644 uint32_t Value; 1645 }; 1646 } DW17; 1647 1648 // DW18 1649 union 1650 { 1651 struct 1652 { 1653 SearchPathDelta SPDelta_8; 1654 SearchPathDelta SPDelta_9; 1655 SearchPathDelta SPDelta_10; 1656 SearchPathDelta SPDelta_11; 1657 }; 1658 struct 1659 { 1660 uint32_t Value; 1661 }; 1662 } DW18; 1663 1664 // DW19 1665 union 1666 { 1667 struct 1668 { 1669 SearchPathDelta SPDelta_12; 1670 SearchPathDelta SPDelta_13; 1671 SearchPathDelta SPDelta_14; 1672 SearchPathDelta SPDelta_15; 1673 }; 1674 struct 1675 { 1676 uint32_t Value; 1677 }; 1678 } DW19; 1679 1680 // DW20 1681 union 1682 { 1683 struct 1684 { 1685 SearchPathDelta SPDelta_16; 1686 SearchPathDelta SPDelta_17; 1687 SearchPathDelta SPDelta_18; 1688 SearchPathDelta SPDelta_19; 1689 }; 1690 struct 1691 { 1692 uint32_t Value; 1693 }; 1694 } DW20; 1695 1696 // DW21 1697 union 1698 { 1699 struct 1700 { 1701 SearchPathDelta SPDelta_20; 1702 SearchPathDelta SPDelta_21; 1703 SearchPathDelta SPDelta_22; 1704 SearchPathDelta SPDelta_23; 1705 }; 1706 struct 1707 { 1708 uint32_t Value; 1709 }; 1710 } DW21; 1711 1712 // DW22 1713 union 1714 { 1715 struct 1716 { 1717 SearchPathDelta SPDelta_24; 1718 SearchPathDelta SPDelta_25; 1719 SearchPathDelta SPDelta_26; 1720 SearchPathDelta SPDelta_27; 1721 }; 1722 struct 1723 { 1724 uint32_t Value; 1725 }; 1726 } DW22; 1727 1728 // DW23 1729 union 1730 { 1731 struct 1732 { 1733 SearchPathDelta SPDelta_28; 1734 SearchPathDelta SPDelta_29; 1735 SearchPathDelta SPDelta_30; 1736 SearchPathDelta SPDelta_31; 1737 }; 1738 struct 1739 { 1740 uint32_t Value; 1741 }; 1742 } DW23; 1743 1744 // DW24 1745 union 1746 { 1747 struct 1748 { 1749 SearchPathDelta SPDelta_32; 1750 SearchPathDelta SPDelta_33; 1751 SearchPathDelta SPDelta_34; 1752 SearchPathDelta SPDelta_35; 1753 }; 1754 struct 1755 { 1756 uint32_t Value; 1757 }; 1758 } DW24; 1759 1760 // DW25 1761 union 1762 { 1763 struct 1764 { 1765 SearchPathDelta SPDelta_36; 1766 SearchPathDelta SPDelta_37; 1767 SearchPathDelta SPDelta_38; 1768 SearchPathDelta SPDelta_39; 1769 }; 1770 struct 1771 { 1772 uint32_t Value; 1773 }; 1774 } DW25; 1775 1776 // DW26 1777 union 1778 { 1779 struct 1780 { 1781 SearchPathDelta SPDelta_40; 1782 SearchPathDelta SPDelta_41; 1783 SearchPathDelta SPDelta_42; 1784 SearchPathDelta SPDelta_43; 1785 }; 1786 struct 1787 { 1788 uint32_t Value; 1789 }; 1790 } DW26; 1791 1792 // DW27 1793 union 1794 { 1795 struct 1796 { 1797 SearchPathDelta SPDelta_44; 1798 SearchPathDelta SPDelta_45; 1799 SearchPathDelta SPDelta_46; 1800 SearchPathDelta SPDelta_47; 1801 }; 1802 struct 1803 { 1804 uint32_t Value; 1805 }; 1806 } DW27; 1807 1808 // DW28 1809 union 1810 { 1811 struct 1812 { 1813 SearchPathDelta SPDelta_48; 1814 SearchPathDelta SPDelta_49; 1815 SearchPathDelta SPDelta_50; 1816 SearchPathDelta SPDelta_51; 1817 }; 1818 struct 1819 { 1820 uint32_t Value; 1821 }; 1822 } DW28; 1823 1824 // DW29 1825 union 1826 { 1827 struct 1828 { 1829 SearchPathDelta SPDelta_52; 1830 SearchPathDelta SPDelta_53; 1831 SearchPathDelta SPDelta_54; 1832 SearchPathDelta SPDelta_55; 1833 }; 1834 struct 1835 { 1836 uint32_t Value; 1837 }; 1838 } DW29; 1839 } SPDelta; 1840 1841 // DW30 1842 union 1843 { 1844 struct 1845 { 1846 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE(0, 15); 1847 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 1848 }; 1849 struct 1850 { 1851 uint32_t Value; 1852 }; 1853 } DW30; 1854 1855 // DW31 1856 union 1857 { 1858 struct 1859 { 1860 uint32_t RoiCtrl : MOS_BITFIELD_RANGE(0, 7); 1861 uint32_t MaxTuSize : MOS_BITFIELD_RANGE(8, 9); 1862 uint32_t MaxCuSize : MOS_BITFIELD_RANGE(10, 11); 1863 uint32_t NumImePredictors : MOS_BITFIELD_RANGE(12, 15); 1864 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 23); 1865 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE(24, 31); 1866 }; 1867 struct 1868 { 1869 uint32_t Value; 1870 }; 1871 } DW31; 1872 1873 // DW32 1874 union 1875 { 1876 struct 1877 { 1878 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE(0, 15); 1879 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 1880 }; 1881 struct 1882 { 1883 uint32_t Value; 1884 }; 1885 } DW32; 1886 1887 // DW33 1888 union 1889 { 1890 struct 1891 { 1892 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE(0, 15); 1893 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 1894 }; 1895 struct 1896 { 1897 uint32_t Value; 1898 }; 1899 } DW33; 1900 1901 // DW34 1902 union 1903 { 1904 struct 1905 { 1906 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE(0, 15); 1907 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 1908 }; 1909 struct 1910 { 1911 uint32_t Value; 1912 }; 1913 } DW34; 1914 1915 // DW35 1916 union 1917 { 1918 struct 1919 { 1920 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE(0, 15); 1921 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 1922 }; 1923 struct 1924 { 1925 uint32_t Value; 1926 }; 1927 } DW35; 1928 1929 // DW36 1930 union 1931 { 1932 struct 1933 { 1934 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE(0, 3); 1935 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE(4, 7); 1936 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE(8, 11); 1937 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 1938 uint32_t NumMergeCandCu8x8 : MOS_BITFIELD_RANGE(16, 19); 1939 uint32_t NumMergeCandCu16x16 : MOS_BITFIELD_RANGE(20, 23); 1940 uint32_t NumMergeCandCu32x32 : MOS_BITFIELD_RANGE(24, 27); 1941 uint32_t NumMergeCandCu64x64 : MOS_BITFIELD_RANGE(28, 31); 1942 }; 1943 struct 1944 { 1945 uint32_t Value; 1946 }; 1947 } DW36; 1948 1949 // DW37 1950 union 1951 { 1952 struct 1953 { 1954 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); 1955 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 1956 uint32_t SegIDEnable : MOS_BITFIELD_BIT(20); 1957 uint32_t Reserved : MOS_BITFIELD_RANGE(21, 22); 1958 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT(23); 1959 uint32_t Reserved1 : MOS_BITFIELD_RANGE(24, 31); 1960 }; 1961 struct 1962 { 1963 uint32_t Value; 1964 }; 1965 } DW37; 1966 1967 // DW38 1968 union 1969 { 1970 struct 1971 { 1972 uint32_t ForceQp0 : MOS_BITFIELD_RANGE(0, 7); 1973 uint32_t ForceQp1 : MOS_BITFIELD_RANGE(8, 15); 1974 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 1975 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(24, 31); 1976 }; 1977 struct 1978 { 1979 uint32_t Value; 1980 }; 1981 } DW38; 1982 1983 // DW39 1984 union 1985 { 1986 struct 1987 { 1988 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31); 1989 }; 1990 struct 1991 { 1992 uint32_t Value; 1993 }; 1994 } DW39; 1995 1996 // DW40 1997 union 1998 { 1999 struct 2000 { 2001 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2002 }; 2003 struct 2004 { 2005 uint32_t Value; 2006 }; 2007 } DW40; 2008 2009 // DW41 2010 union 2011 { 2012 struct 2013 { 2014 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2015 }; 2016 struct 2017 { 2018 uint32_t Value; 2019 }; 2020 } DW41; 2021 2022 // DW42 2023 union 2024 { 2025 struct 2026 { 2027 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2028 }; 2029 struct 2030 { 2031 uint32_t Value; 2032 }; 2033 } DW42; 2034 2035 // DW43 2036 union 2037 { 2038 struct 2039 { 2040 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2041 }; 2042 struct 2043 { 2044 uint32_t Value; 2045 }; 2046 } DW43; 2047 2048 // DW44 2049 union 2050 { 2051 struct 2052 { 2053 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2054 }; 2055 struct 2056 { 2057 uint32_t Value; 2058 }; 2059 } DW44; 2060 2061 // DW45 2062 union 2063 { 2064 struct 2065 { 2066 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2067 }; 2068 struct 2069 { 2070 uint32_t Value; 2071 }; 2072 } DW45; 2073 2074 // DW46 2075 union 2076 { 2077 struct 2078 { 2079 uint32_t VDEncStreamInOutputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2080 }; 2081 struct 2082 { 2083 uint32_t Value; 2084 }; 2085 } DW46; 2086 2087 // DW47 2088 union 2089 { 2090 struct 2091 { 2092 uint32_t VDEncStreamInInputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 2093 }; 2094 struct 2095 { 2096 uint32_t Value; 2097 }; 2098 } DW47; 2099 }; 2100 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_VDENC_HEVC_ME_CURBE_G12)) == 48); 2101 2102 using PCODECHAL_VDENC_HEVC_ME_CURBE_G12 = CODECHAL_VDENC_HEVC_ME_CURBE_G12 * ; 2103 2104 //! HEVC VDEnc encoder class for GEN12 2105 /*! 2106 This class defines the member fields, functions for GEN12 platform 2107 */ 2108 class CodechalVdencHevcStateG12 : public CodechalVdencHevcState 2109 { 2110 public: 2111 static const uint32_t m_minScaledSurfaceSize = 64; //!< Minimum scaled surface size 2112 static const uint32_t m_brcPakStatsBufSize = 512; //!< Pak statistic buffer size 2113 static const uint32_t m_brcStatsBufSize = 1216; //!< BRC Statistic buf size: 48DWs (3CLs) of HMDC Frame Stats + 256 DWs (16CLs) of Histogram Stats = 1216 bytes 2114 static const uint32_t m_brcConstantSurfaceWidth = 64; //!< BRC constant surface width 2115 static const uint32_t m_brcConstantSurfaceHeight = 35; //!< BRC constant surface height 2116 static const uint32_t m_brcHistoryBufSize = 2304; //!< BRC history buffer size 2117 static const uint32_t m_bframeMeBidirectionalWeight = 32; //!< B frame bidirection weight 2118 uint32_t m_prevQpModulationStrength = 0; 2119 bool m_initDeltaQP = true; 2120 uint32_t m_prevVdencReadBatchBufferSize = 0; 2121 uint32_t m_numNAL = 0; 2122 uint32_t m_overallNALPayload = 0; 2123 2124 // HuC tables. 2125 // These Values are diff for each Gen 2126 static const int8_t m_devThreshPB0[8]; 2127 static const int8_t m_lowDelayDevThreshPB0[8]; 2128 static const int8_t m_devThreshVBR0[8]; 2129 static const int8_t m_lowDelayDevThreshVBR0[8]; 2130 static const int8_t m_devThreshI0[8]; 2131 static const int8_t m_lowDelayDevThreshI0[8]; 2132 static const uint32_t m_hucConstantData[]; 2133 2134 static constexpr uint32_t m_numDevThreshlds = 8; 2135 static constexpr double m_devStdFPS = 30.0; 2136 static constexpr double m_bpsRatioLow = 0.1; 2137 static constexpr double m_bpsRatioHigh = 3.5; 2138 static constexpr int32_t m_postMultPB = 50; 2139 static constexpr int32_t m_negMultPB = -50; 2140 static constexpr int32_t m_posMultVBR = 100; 2141 static constexpr int32_t m_negMultVBR = -50; 2142 2143 static const double m_devThreshIFPNEG[m_numDevThreshlds / 2]; 2144 static const double m_devThreshIFPPOS[m_numDevThreshlds / 2]; 2145 static const double m_devThreshPBFPNEG[m_numDevThreshlds / 2]; 2146 static const double m_devThreshPBFPPOS[m_numDevThreshlds / 2]; 2147 static const double m_devThreshVBRNEG[m_numDevThreshlds / 2]; 2148 static const double m_devThreshVBRPOS[m_numDevThreshlds / 2]; 2149 static const int8_t m_lowdelayDevThreshPB[m_numDevThreshlds]; 2150 static const int8_t m_lowdelayDevThreshVBR[m_numDevThreshlds]; 2151 static const int8_t m_lowdelayDevThreshI[m_numDevThreshlds]; 2152 static const int8_t m_lowdelayDeltaFrmszI[][8]; 2153 static const int8_t m_lowdelayDeltaFrmszP[][8]; 2154 static const int8_t m_lowdelayDeltaFrmszB[][8]; 2155 2156 // VDENC Display interface related 2157 bool m_enableTileReplay = false; //!< TileReplay Enable 2158 uint8_t m_tileRowPass = 0; //!< Current tile row pass 2159 2160 struct CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE 2161 { 2162 union { 2163 uint8_t VdBox[MOS_MAX_ENGINE_INSTANCE_PER_CLASS]; 2164 uint64_t Value; 2165 }; 2166 }; 2167 2168 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 m_tileParams[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC] = {}; //!< Pointer to the Tile params 2169 2170 // GEN12 specific resources 2171 MOS_RESOURCE m_vdencTileRowStoreBuffer = {}; //!< Tile row store buffer 2172 MOS_RESOURCE m_vdencCumulativeCuCountStreamoutSurface = {}; //!< Cumulative CU Count Streamout Surface 2173 MOS_RESOURCE m_vdencPaletteModeStreamOutBuffer = {}; //!< Palette mode stream out buffer 2174 MOS_RESOURCE m_vdencSAORowStoreBuffer = {}; //!< SAO RowStore buffer 2175 MOS_RESOURCE m_resHwCountTileReplay = {}; //!< Tile based HW Counter buffer 2176 2177 bool m_enableTileStitchByHW = false; //!< Enable HW to stitch commands in scalable mode 2178 bool m_enableHWSemaphore = false; //!< Enable HW semaphore 2179 bool m_enableVdBoxHWSemaphore = false; //!< Enable VDBOX HW semaphore 2180 2181 unsigned char m_slotForRecNotFiltered = 0; //!< Slot for not filtered reconstructed surface 2182 2183 // 3rd Level Batch buffer 2184 uint32_t m_thirdLBSize = 0; //!< Size of the 3rd level batch buffer 2185 MHW_BATCH_BUFFER m_thirdLevelBatchBuffer; //!< 3rd level batch buffer 2186 2187 // Tile level batch buffer 2188 uint32_t m_tileLevelBatchSize = 0; //!< Size of the 2rd level batch buffer for each tile 2189 uint32_t m_numTileBatchAllocated = 0; //!< The number of allocated batch buffer for tiles 2190 PMHW_BATCH_BUFFER m_tileLevelBatchBuffer[CODECHAL_VDENC_BRC_NUM_OF_PASSES] = {}; //!< Tile level batch buffer for each tile 2191 2192 // scalability 2193 unsigned char m_numPipe = 1; //!< Number of pipes 2194 unsigned char m_numPipePre = 1; //!< Number of pipes of previous frame 2195 unsigned char m_numPassesInOnePipe = 1; //!< Number of PAK passes in one pipe 2196 CODECHAL_ENCODE_BUFFER m_resPakSliceLevelStreamoutData = {}; //!< Surface for slice level stream out data from PAK 2197 CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE m_kmdVeOveride = {}; //!< KMD override virtual engine index 2198 uint32_t m_numTiles = 1; //!< Number of tiles 2199 uint32_t m_numLcu = 1; //!< LCU number 2200 CODECHAL_ENCODE_BUFFER m_resHcpScalabilitySyncBuffer = {}; //!< Hcp sync buffer for scalability 2201 CODECHAL_ENCODE_BUFFER m_resTileBasedStatisticsBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC] = {}; 2202 CODECHAL_ENCODE_BUFFER m_resHuCPakAggregatedFrameStatsBuffer = {}; 2203 CODECHAL_ENCODE_BUFFER m_tileRecordBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC] = {}; 2204 MOS_RESOURCE m_resHucPakStitchDmemBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_VDENC_BRC_NUM_OF_PASSES] = {}; //!< HuC Pak Integration Dmem data for each pass 2205 MOS_RESOURCE m_resBrcDataBuffer = {}; //!< Resource of bitrate control data buffer 2206 HEVC_TILE_STATS_INFO m_hevcTileStatsOffset = {}; //!< Page aligned offsets used to program HCP / VDEnc pipe and HuC PAK Integration kernel input 2207 HEVC_TILE_STATS_INFO m_hevcFrameStatsOffset = {}; //!< Page aligned offsets used to program HuC PAK Integration kernel output, HuC BRC kernel input 2208 HEVC_TILE_STATS_INFO m_hevcStatsSize = {}; //!< HEVC Statistics size 2209 bool m_enableTestMediaReset = 0; //!< enable media reset test. driver will send cmd to make hang happens 2210 bool m_forceScalability = false; //!< force scalability for resolution < 4K/5K if other checking for scalability passed 2211 2212 // HuC PAK stitch kernel 2213 MOS_RESOURCE m_resHucStitchDataBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_HEVC_MAX_NUM_BRC_PASSES] = {}; // data buffer for huc input cmd generation 2214 MHW_BATCH_BUFFER m_HucStitchCmdBatchBuffer = {}; //!< SLB for huc stitch cmd 2215 2216 // virtual engine 2217 bool m_useVirtualEngine = false; //!< Virtual engine enable flag 2218 MOS_COMMAND_BUFFER m_veBatchBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC][CODECHAL_HEVC_MAX_NUM_HCP_PIPE][CODECHAL_HEVC_MAX_NUM_BRC_PASSES]; //!< Virtual engine batch buffers 2219 MOS_COMMAND_BUFFER m_realCmdBuffer; //!< Virtual engine command buffer 2220 uint32_t m_sizeOfVeBatchBuffer = 0; //!< Virtual engine batch buffer size 2221 CODECHAL_ENCODE_BUFFER m_resBrcSemaphoreMem[CODECHAL_HEVC_MAX_NUM_HCP_PIPE]; //!< BRC HW semaphore 2222 CODECHAL_ENCODE_BUFFER m_resVdBoxSemaphoreMem[CODECHAL_HEVC_MAX_NUM_HCP_PIPE]; //!< VDBox HW semaphore 2223 CODECHAL_ENCODE_BUFFER m_resBrcPakSemaphoreMem; //!< BRC PAK HW semaphore 2224 CODECHAL_ENCODE_BUFFER m_resPipeStartSemaMem[CODECHAL_HEVC_MAX_NUM_HCP_PIPE]; //!< HW semaphore for scalability pipe start at the same time 2225 2226 int32_t m_curPicSlot = -1; //!< Slot selected to store current Picutre data 2227 uint32_t m_prevStoreData = 0; //!< Previous stored data 2228 2229 uint32_t m_roundInterValue = 0; 2230 uint32_t m_roundIntraValue = 0; 2231 2232 // Information for entry/slot in the picture data 2233 struct SlotInfo { 2234 uint32_t age; 2235 int32_t poc; 2236 bool isUsed; 2237 bool isRef; 2238 } slotInfo[CODECHAL_ENCODE_HEVC_VDENC_WP_DATA_BLOCK_NUMBER] = { { 0, 0, false, false } }; 2239 2240 // SCC 2241 bool m_enableLBCOnly = false; //!< Enable LBC only for IBC 2242 bool m_enableSCC = false; //!< Flag to indicate if HEVC SCC is enabled. 2243 MOS_RESOURCE m_vdencRecNotFilteredBuffer = {}; 2244 2245 //! 2246 //! \brief Constructor 2247 //! 2248 CodechalVdencHevcStateG12(CodechalHwInterface* hwInterface, 2249 CodechalDebugInterface* debugInterface, 2250 PCODECHAL_STANDARD_INFO standardInfo); 2251 2252 //! 2253 //! \brief Destructor 2254 //! 2255 ~CodechalVdencHevcStateG12(); 2256 2257 //! 2258 //! \brief Help function to get current pipe 2259 //! 2260 //! \return Current pipe value 2261 //! GetCurrentPipe()2262 int GetCurrentPipe() 2263 { 2264 if (m_numPipe <= 1) 2265 { 2266 return 0; 2267 } 2268 2269 return (int)(m_currPass) % (int)m_numPipe; 2270 } 2271 2272 //! 2273 //! \brief Help function to get current PAK pass 2274 //! 2275 //! \return Current PAK pass 2276 //! GetCurrentPass()2277 int GetCurrentPass() override 2278 { 2279 if (m_numPipe <= 1) 2280 { 2281 return m_currPass; 2282 } 2283 2284 return (int)(m_currPass) / (int)m_numPipe; 2285 } 2286 2287 //! 2288 //! \brief Help function to check if current pipe is first pipe 2289 //! 2290 //! \return True if current pipe is first pipe, otherwise return false 2291 //! IsFirstPipe()2292 bool IsFirstPipe() 2293 { 2294 return GetCurrentPipe() == 0 ? true : false; 2295 } 2296 2297 //! 2298 //! \brief Help function to check if current pipe is last pipe 2299 //! 2300 //! \return True if current pipe is last pipe, otherwise return false 2301 //! IsLastPipe()2302 bool IsLastPipe() 2303 { 2304 return GetCurrentPipe() == m_numPipe - 1 ? true : false; 2305 } 2306 2307 //! 2308 //! \brief Help function to check if current PAK pass is first pass 2309 //! 2310 //! \return True if current PAK pass is first pass, otherwise return false 2311 //! IsFirstPass()2312 bool IsFirstPass() override 2313 { 2314 return GetCurrentPass() == 0 ? true : false; 2315 } 2316 2317 //! 2318 //! \brief Help function to check if current PAK pass is last pass 2319 //! 2320 //! \return True if current PAK pass is last pass, otherwise return false 2321 //! IsLastPass()2322 bool IsLastPass() override 2323 { 2324 return GetCurrentPass() == m_numPassesInOnePipe ? true : false; 2325 } 2326 2327 //! 2328 //! \brief Help function to check if current PAK pass is first pass for tile replay 2329 //! 2330 //! \return True if current PAK pass is first pass, otherwise return false 2331 //! IsFirstPassForTileReplay()2332 bool IsFirstPassForTileReplay() 2333 { 2334 return (m_tileRowPass == 0) ? true : false; 2335 } 2336 2337 //! 2338 //! \brief Help function to check if current PAK pass is last pass for tile replay 2339 //! 2340 //! \return True if current PAK pass is last pass for tile replay, otherwise return false 2341 //! IsLastPassForTileReplay()2342 bool IsLastPassForTileReplay() 2343 { 2344 return (m_tileRowPass == m_NumPassesForTileReplay - 1) ? true : false; 2345 } 2346 2347 // inherited virtual functions 2348 uint32_t GetMaxBtCount() override; 2349 bool CheckSupportedFormat(PMOS_SURFACE surface) override; 2350 void SetHcpSliceStateCommonParams(MHW_VDBOX_HEVC_SLICE_STATE& sliceStateParams) override; 2351 void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams) override; 2352 void SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams) override; 2353 void SetHcpPicStateParams(MHW_VDBOX_HEVC_PIC_STATE& picStateParams) override; 2354 MOS_STATUS AddHcpRefIdxCmd(PMOS_COMMAND_BUFFER cmdBuffer, PMHW_BATCH_BUFFER batchBuffer, PMHW_VDBOX_HEVC_SLICE_STATE params) override; 2355 void SetVdencPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams) override; 2356 void SetVdencPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams) override; 2357 MOS_STATUS Initialize(CodechalSetting * settings) override; 2358 MOS_STATUS InitKernelState() override; 2359 MOS_STATUS PlatformCapabilityCheck() override; 2360 MOS_STATUS AllocatePakResources() override; 2361 MOS_STATUS FreePakResources() override; 2362 MOS_STATUS AllocateEncResources() override; 2363 MOS_STATUS FreeEncResources() override; 2364 MOS_STATUS AllocateBrcResources() override; 2365 MOS_STATUS FreeBrcResources() override; 2366 MOS_STATUS InitializePicture(const EncoderParams& params) override; 2367 MOS_STATUS ValidateRefFrameData(PCODEC_HEVC_ENCODE_SLICE_PARAMS slcParams) override; 2368 MOS_STATUS SetPictureStructs() override; 2369 MOS_STATUS SetSequenceStructs() override; 2370 MOS_STATUS GetStatusReport(EncodeStatus* encodeStatus, EncodeStatusReport* encodeStatusReport) override; 2371 MOS_STATUS UserFeatureKeyReport() override; 2372 MOS_STATUS EncodeKernelFunctions() override; 2373 MOS_STATUS ExecutePictureLevel() override; 2374 MOS_STATUS ExecuteSliceLevel() override; 2375 MOS_STATUS ConstructBatchBufferHuCBRC(PMOS_RESOURCE batchBuffer) override; 2376 MOS_STATUS SetDmemHuCBrcInitReset() override; 2377 MOS_STATUS SetConstDataHuCBrcUpdate() override; 2378 MOS_STATUS SetDmemHuCBrcUpdate() override; 2379 MOS_STATUS SetRegionsHuCBrcUpdate(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams) override; 2380 MOS_STATUS SetDmemHuCPakIntegrate(PMHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams); 2381 MOS_STATUS SetRegionsHuCPakIntegrate(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 2382 MOS_STATUS SetDmemHuCPakIntegrateStitch(PMHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams); 2383 MOS_STATUS SetRegionsHuCPakIntegrateStitch(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 2384 MOS_STATUS HucPakIntegrateStitch(PMOS_COMMAND_BUFFER cmdBuffer); 2385 MOS_STATUS PrepareVDEncStreamInData() override; 2386 MOS_STATUS SetGpuCtxCreatOption() override; 2387 MOS_STATUS ReadSliceSize(PMOS_COMMAND_BUFFER cmdBuffer) override; 2388 void GetTileInfo(uint32_t xPosition, uint32_t yPosition, uint32_t* tileId, uint32_t* tileEndLCUX, uint32_t* tileEndLCUY); 2389 void SetStreaminDataPerRegion( 2390 uint32_t streamInWidth, 2391 uint32_t top, 2392 uint32_t bottom, 2393 uint32_t left, 2394 uint32_t right, 2395 PMHW_VDBOX_VDENC_STREAMIN_STATE_PARAMS streaminParams, 2396 void* streaminData) override; 2397 void SetBrcRoiDeltaQpMap( 2398 uint32_t streamInWidth, 2399 uint32_t top, 2400 uint32_t bottom, 2401 uint32_t left, 2402 uint32_t right, 2403 uint8_t regionId, 2404 PDeltaQpForROI deltaQpMap) override; 2405 2406 void CreateMhwParams() override; 2407 2408 MOS_STATUS VerifyCommandBufferSize() override; 2409 2410 MOS_STATUS GetCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer) override; 2411 2412 MOS_STATUS ReturnCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer) override; 2413 2414 MOS_STATUS SubmitCommandBuffer( 2415 PMOS_COMMAND_BUFFER cmdBuffer, 2416 bool bNullRendering) override; 2417 2418 MOS_STATUS SendPrologWithFrameTracking( 2419 PMOS_COMMAND_BUFFER cmdBuffer, 2420 bool frameTrackingRequested, 2421 MHW_MI_MMIOREGISTERS *mmioRegister = nullptr) override; 2422 2423 MOS_STATUS SetSliceStructs() override; 2424 2425 MOS_STATUS AllocateTileStatistics(); 2426 2427 void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams) override; 2428 2429 MOS_STATUS ReadSseStatistics(PMOS_COMMAND_BUFFER cmdBuffer) override; 2430 2431 MOS_STATUS HuCBrcInitReset() override; 2432 2433 //! 2434 //! \brief Encode at tile level 2435 //! 2436 //! \return MOS_STATUS 2437 //! MOS_STATUS_SUCCESS if success, else fail reason 2438 //! 2439 MOS_STATUS EncTileLevel(); 2440 2441 //! 2442 //! \brief Decide number of pipes used for encoding 2443 //! \details called inside PlatformCapabilityCheck 2444 //! 2445 //! \return MOS_STATUS 2446 //! MOS_STATUS_SUCCESS if success, else fail reason 2447 //! 2448 MOS_STATUS DecideEncodingPipeNumber(); 2449 2450 // overload with more input params 2451 void SetHcpSliceStateParams( 2452 MHW_VDBOX_HEVC_SLICE_STATE& sliceState, 2453 PCODEC_ENCODER_SLCDATA slcData, 2454 uint16_t slcCount, 2455 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 tileCodingParams, 2456 bool lastSliceInTile, 2457 uint32_t idx); 2458 2459 //! 2460 //! \brief Get encoder kernel header and kernel size 2461 //! 2462 //! \param [in] binary 2463 //! Pointer to kernel binary 2464 //! \param [in] operation 2465 //! Enc kernel operation 2466 //! \param [in] krnStateIdx 2467 //! Kernel state index 2468 //! \param [out] krnHeader 2469 //! Pointer to kernel header 2470 //! \param [out] krnSize 2471 //! Pointer to kernel size 2472 //! 2473 //! \return MOS_STATUS 2474 //! MOS_STATUS_SUCCESS if success, else fail reason 2475 //! 2476 static MOS_STATUS GetKernelHeaderAndSize( 2477 void *binary, 2478 EncOperation operation, 2479 uint32_t krnStateIdx, 2480 void *krnHeader, 2481 uint32_t *krnSize); 2482 2483 //! 2484 //! \brief Init kernel state for HME kernel 2485 //! 2486 //! \return MOS_STATUS 2487 //! MOS_STATUS_SUCCESS if success, else fail reason 2488 //! 2489 MOS_STATUS InitKernelStateMe(); 2490 2491 //! 2492 //! \brief Init kernel state for streamin kernel 2493 //! 2494 //! \return MOS_STATUS 2495 //! MOS_STATUS_SUCCESS if success, else fail reason 2496 //! 2497 MOS_STATUS InitKernelStateStreamIn(); 2498 2499 //! 2500 //! \brief Set kernel parameters for specific kernel operation 2501 //! 2502 //! \param [in] operation 2503 //! Kernel operation 2504 //! \param [out] kernelParams 2505 //! Pointer to kernel parameters 2506 //! 2507 //! \return MOS_STATUS 2508 //! MOS_STATUS_SUCCESS if success, else fail reason 2509 //! 2510 MOS_STATUS SetKernelParams( 2511 EncOperation operation, 2512 MHW_KERNEL_PARAM *kernelParams); 2513 2514 //! 2515 //! \brief Set binding table for specific kernel operation 2516 //! 2517 //! \param [in] operation 2518 //! Kernel operation 2519 //! \param [out] bindingTable 2520 //! Pointer to binding table 2521 //! 2522 //! \return MOS_STATUS 2523 //! MOS_STATUS_SUCCESS if success, else fail reason 2524 //! 2525 MOS_STATUS SetBindingTable( 2526 EncOperation operation, 2527 PCODECHAL_ENCODE_BINDING_TABLE_GENERIC bindingTable); 2528 2529 //! 2530 //! \brief Invoke HME kernel 2531 //! 2532 //! \param [in] hmeLevel 2533 //! HME level like 4x, 16x 32x 2534 //! 2535 //! \return MOS_STATUS 2536 //! MOS_STATUS_SUCCESS if success, else fail reason 2537 //! 2538 MOS_STATUS EncodeMeKernel( 2539 HmeLevel hmeLevel); 2540 2541 //! 2542 //! \brief Set curbe for HME kernel 2543 //! 2544 //! \param [in] hmeLevel 2545 //! HME level like 4x, 16x 32x 2546 //! 2547 //! \return MOS_STATUS 2548 //! MOS_STATUS_SUCCESS if success, else fail reason 2549 //! 2550 MOS_STATUS SetMeCurbe( 2551 HmeLevel hmeLevel); 2552 2553 //! 2554 //! \brief Set surface state for HME kernel 2555 //! 2556 //! \param [in] hmeLevel 2557 //! HME level like 4x, 16x 32x 2558 //! \param [in] cmdBuffer 2559 //! Pointer to command buffer that surface states are added 2560 //! 2561 //! \return MOS_STATUS 2562 //! MOS_STATUS_SUCCESS if success, else fail reason 2563 //! 2564 MOS_STATUS SendMeSurfaces( 2565 HmeLevel hmeLevel, 2566 PMOS_COMMAND_BUFFER cmdBuffer); 2567 2568 //! 2569 //! \brief Construct the 3rd level batch buffer 2570 //! 2571 //! \param [in] thirdLevelBatchBuffer 2572 //! Pointer to the 3rd level batch buffer for each tile 2573 //! 2574 //! \return MOS_STATUS 2575 //! MOS_STATUS_SUCCESS if success, else fail reason 2576 //! 2577 MOS_STATUS ConstructTLB(PMHW_BATCH_BUFFER thirdLevelBatchBuffer); 2578 2579 MOS_STATUS AddVdencWalkerStateCmd( 2580 PMOS_COMMAND_BUFFER cmdBuffer, 2581 PMHW_VDBOX_HEVC_SLICE_STATE params) override; 2582 2583 //! \brief Allocate the batch buffer for each tile 2584 //! 2585 //! \return MOS_STATUS 2586 //! MOS_STATUS_SUCCESS if success, else fail reason 2587 //! 2588 MOS_STATUS AllocateTileLevelBatch(); 2589 2590 //! 2591 //! \brief Free the batch buffer for each tile 2592 //! 2593 //! \return MOS_STATUS 2594 //! MOS_STATUS_SUCCESS if success, else fail reason 2595 //! 2596 MOS_STATUS FreeTileLevelBatch(); 2597 2598 MOS_STATUS CalculatePictureStateCommandSize() override; 2599 2600 MOS_STATUS AddHcpPipeBufAddrCmd( 2601 PMOS_COMMAND_BUFFER cmdBuffer) override; 2602 2603 //! 2604 //! \brief Is slice in the current tile 2605 //! 2606 //! \param [in] sliceNumber 2607 //! Slice number 2608 //! \param [in] currentTile 2609 //! Pointer to current tile coding params 2610 //! \param [out] sliceInTile 2611 //! Pointer to return if slice in tile 2612 //! \param [out] lastSliceInTile 2613 //! Pointer to return if last slice in tile 2614 //! 2615 //! \return MOS_STATUS 2616 //! MOS_STATUS_SUCCESS if success, else fail reason 2617 //! 2618 MOS_STATUS IsSliceInTile( 2619 uint32_t sliceNumber, 2620 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 currentTile, 2621 bool *sliceInTile, 2622 bool *lastSliceInTile); 2623 2624 //! 2625 //! \brief Set tile data 2626 //! 2627 //! \param [in] tileCodingParams 2628 //! Pointer to tile coding params 2629 //! \return MOS_STATUS 2630 //! MOS_STATUS_SUCCESS if success, else fail reason 2631 //! 2632 MOS_STATUS SetTileData(MHW_VDBOX_HCP_TILE_CODING_PARAMS_G12* tileCodingParams); 2633 2634 //! 2635 //! \brief Invoke HuC BRC update 2636 //! 2637 //! \return MOS_STATUS 2638 //! MOS_STATUS_SUCCESS if success, else fail reason 2639 //! 2640 MOS_STATUS HuCBrcUpdate() override; 2641 2642 //! 2643 //! \brief HuC PAK integrate 2644 //! 2645 //! \param [in] cmdBuffer 2646 //! Pointer to command buffer 2647 //! 2648 //! \return MOS_STATUS 2649 //! MOS_STATUS_SUCCESS if success, else fail reason 2650 //! 2651 MOS_STATUS HucPakIntegrate( 2652 PMOS_COMMAND_BUFFER cmdBuffer); 2653 2654 //! \brief Check whether Scalability is enabled or not, 2655 //! Set number of VDBoxes accordingly 2656 //! 2657 //! \return MOS_STATUS 2658 //! MOS_STATUS_SUCCESS if success, else fail reason 2659 //! 2660 MOS_STATUS GetSystemPipeNumberCommon(); 2661 2662 MOS_STATUS InitMmcState() override; 2663 2664 MOS_STATUS InitReserveState(CodechalSetting * settings); 2665 2666 MOS_STATUS UpdateCmdBufAttribute( 2667 PMOS_COMMAND_BUFFER cmdBuffer, 2668 bool renderEngineInUse) override; 2669 2670 MOS_STATUS AddMediaVfeCmd( 2671 PMOS_COMMAND_BUFFER cmdBuffer, 2672 SendKernelCmdsParams *params) override; 2673 2674 //! 2675 //! \brief Calculate Command Buffer Size 2676 //! 2677 //! \return uint32_t 2678 //! Command buffer size calculated 2679 //! 2680 uint32_t CalculateCommandBufferSize() override; 2681 2682 //! 2683 //! \brief Set Streamin Data Per Lcu 2684 //! 2685 //! \param [in] streaminParams 2686 //! Streamin parameters 2687 //! \param [in] streaminData 2688 //! Streamin data 2689 //! 2690 //! \return void 2691 //! 2692 void SetStreaminDataPerLcu( 2693 PMHW_VDBOX_VDENC_STREAMIN_STATE_PARAMS streaminParams, 2694 void* streaminData) override; 2695 2696 //! 2697 //! \brief Set And Populate VE Hint parameters 2698 //! \details Set Virtual Engine hint parameter and populate it to primary cmd buffer attributes 2699 //! \param [in] cmdBuffer 2700 //! Pointer to primary cmd buffer 2701 //! \return MOS_STATUS 2702 //! MOS_STATUS_SUCCESS if success, else fail reason 2703 //! 2704 MOS_STATUS SetAndPopulateVEHintParams( 2705 PMOS_COMMAND_BUFFER cmdBuffer); 2706 2707 PCODECHAL_ENCODE_SCALABILITY_STATE m_scalabilityState; //!< Scalability state 2708 2709 #if USE_CODECHAL_DEBUG_TOOL 2710 virtual MOS_STATUS DumpVdencOutputs() override; 2711 #endif 2712 2713 MOS_STATUS SetRoundingValues(); 2714 2715 protected: 2716 #ifdef _ENCODE_VDENC_RESERVED 2717 CodechalVdencHevcG12Rsvd *m_rsvdState = nullptr; 2718 #endif 2719 2720 private: 2721 // tile row based BRC related 2722 bool m_FrameLevelBRCForTileRow = false; //!< Frame level BRC for tile row based encoding 2723 bool m_TileRowLevelBRC = false; //!< Tile Row level BRC for tile row based encoding 2724 uint32_t m_CurrentTileRow = 0; //!< Current tile row number, start from 0 2725 static const uint32_t m_NumPassesForTileReplay = 2; //!< Max number Passes for tile row based BRC 2726 uint32_t m_CurrentPassForTileReplay = 0; //!< Current BRC pass number for tile replay 2727 uint32_t m_CurrentPassForOverAll = 0; //!< Current tile replay pass for overall 2728 PMHW_BATCH_BUFFER m_TileRowBRCBatchBuffer[CODECHAL_VDENC_BRC_NUM_OF_PASSES] = {}; //!< Tile level batch buffer HUC BRC Update 2729 uint32_t m_numTileRows = 1; //!< Total number of tile rows 2730 uint32_t m_numTileRowBRCBatchAllocated = 0; //!< The number of allocated batch buffer for tile row BRC 2731 MOS_RESOURCE m_resTileRowBRCsyncSemaphore = {}; //!< HW semaphore buffer for tile row BRC update 2732 bool m_RGBEncodingEnable = false; //!< Enable RGB encoding 2733 bool m_CaptureModeEnable = false; //!< Enable Capture mode with display 2734 bool m_tcbrcQualityBoost = false; 2735 2736 // This may be removed to VDENC HW interface later 2737 static const uint32_t m_VdboxVDENCRegBase[4]; 2738 //! 2739 //! \brief Encode at tile level with tile row based multiple passes 2740 //! 2741 //! \return MOS_STATUS 2742 //! MOS_STATUS_SUCCESS if success, else fail reason 2743 //! 2744 MOS_STATUS EncWithTileRowLevelBRC(); 2745 2746 //! 2747 //! \brief Invoke HuC BRC update for tile row 2748 //! 2749 //! \param [in] cmdBuffer 2750 //! Pointer to command buffer 2751 //! \return MOS_STATUS 2752 //! MOS_STATUS_SUCCESS if success, else fail reason 2753 //! 2754 MOS_STATUS HuCBrcTileRowUpdate(PMOS_COMMAND_BUFFER cmdBuffer); 2755 2756 2757 //! \brief Allocate the BRC batch buffer for each tile row 2758 //! 2759 //! \return MOS_STATUS 2760 //! MOS_STATUS_SUCCESS if success, else fail reason 2761 //! 2762 MOS_STATUS AllocateTileRowLevelBRCBatch(); 2763 2764 //! 2765 //! \brief Free the batch buffer for each tile row level BRC 2766 //! 2767 //! \return MOS_STATUS 2768 //! MOS_STATUS_SUCCESS if success, else fail reason 2769 //! 2770 MOS_STATUS FreeTileRowLevelBRCBatch(); 2771 2772 //! 2773 //! \brief Setup Virtual Address Regions for HuC Tile Row BRC update 2774 //! 2775 //! \param [in] virtualAddrParams 2776 //! Huc Virtual Address parameters 2777 //! 2778 //! \return MOS_STATUS 2779 //! MOS_STATUS_SUCCESS if success, else fail reason 2780 //! 2781 MOS_STATUS SetRegionsHuCTileRowBrcUpdate(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 2782 2783 //! 2784 //! \brief Configue stitch data buffer as Huc Pak Integration input 2785 //! 2786 //! \return MOS_STATUS 2787 //! MOS_STATUS_SUCCESS if success, else fail reason 2788 //! 2789 MOS_STATUS ConfigStitchDataBuffer(); 2790 2791 //! 2792 //! \brief Dump HuC based debug output buffers 2793 //! 2794 //! \return MOS_STATUS 2795 //! MOS_STATUS_SUCCESS if success, else fail reason 2796 //! 2797 MOS_STATUS DumpHucDebugOutputBuffers(); 2798 2799 MOS_STATUS SetAddCommands(uint32_t commandtype, PMOS_COMMAND_BUFFER cmdBuffer, bool addToBatchBufferHuCBRC, uint32_t roundInterValue, uint32_t roundIntraValue, bool isLowDelayB = true, int8_t *pRefIdxMapping = nullptr, int8_t recNotFilteredID = 0); 2800 2801 //! \brief Lookahead analysis 2802 //! 2803 //! \return MOS_STATUS 2804 //! MOS_STATUS_SUCCESS if success, else fail reason 2805 //! 2806 MOS_STATUS AnalyzeLookaheadStats(); 2807 2808 MOS_STATUS HuCLookaheadInit(); 2809 2810 MOS_STATUS HuCLookaheadUpdate(); 2811 2812 MOS_STATUS InsertConditionalBBEndWithHucErrorStatus(PMOS_COMMAND_BUFFER cmdBuffer); 2813 2814 #if USE_CODECHAL_DEBUG_TOOL 2815 MOS_STATUS DumpHucPakIntegrate(); 2816 MOS_STATUS DumpHucCqp(); 2817 #endif 2818 2819 }; 2820 2821 //! \brief typedef of class CodechalVdencHevcStateG12* 2822 using PCODECHAL_VDENC_HEVC_STATE_G12 = class CodechalVdencHevcStateG12*; 2823 2824 #endif // __CODECHAL_VDENC_HEVC_G12_H__ 2825