1 /* 2 * Copyright (c) 2017-2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* 24 * Copyright (c) 2010 The WebM project authors. All Rights Reserved. 25 * 26 * Use of this source code is governed by a BSD-style license 27 * that can be found in the LICENSE file in the root of the source 28 * tree. An additional intellectual property rights grant can be found 29 * in the file PATENTS. All contributing project authors may 30 * be found in the AUTHORS file in the root of the source tree. 31 */ 32 33 //! 34 //! \file codechal_vdenc_vp9_base.h 35 //! \brief Defines base class for VP9 VDENC encoder. 36 //! 37 38 #ifndef __CODECHAL_VDENC_VP9_BASE_H__ 39 #define __CODECHAL_VDENC_VP9_BASE_H__ 40 41 #include "codechal_encoder_base.h" 42 #include "codechal_huc_cmd_initializer.h" 43 #include "codec_def_vp9_probs.h" 44 #include "codechal_debug.h" 45 46 #define CODECHAL_ENCODE_VP9_MAX_NUM_HCP_PIPE 4 47 #define CODECHAL_VP9_ENCODE_RECYCLED_BUFFER_NUM (CODECHAL_ENCODE_RECYCLED_BUFFER_NUM * CODECHAL_ENCODE_VP9_MAX_NUM_HCP_PIPE) // for salability, need 1 buffer per pipe, 48 #define CODECHAL_ENCODE_VP9_NUM_SYNC_TAGS 36 49 #define CODECHAL_ENCODE_VP9_INIT_DSH_SIZE (MHW_PAGE_SIZE * 3) 50 #define CODECHAL_ENCODE_VP9_SUPERFRAME_REPEATED_HEADER_SIZE 1 51 #define CODECHAL_ENCODE_VP9_SUPERFRAME_MARKER_HEADER_SIZE 1 52 #define CODECHAL_ENCODE_VP9_HUC_BRC_DATA_BUFFER_SIZE (16*4) 53 #define CODECHAL_ENCODE_VP9_PAK_INSERT_UNCOMPRESSED_HEADER 80 54 #define CODECHAL_ENCODE_VP9_BRC_SUPER_FRAME_BUFFER_SIZE MOS_ALIGN_CEIL(3 + 2 * sizeof(uint32_t), sizeof(uint32_t)) 55 #define CODECHAL_ENCODE_VP9_VDENC_DATA_EXTENSION_SIZE 32 56 #define CODECHAL_ENCODE_VP9_PIC_STATE_BUFFER_SIZE_PER_PASS 192 // 42 DWORDs for Pic State one uint32_t for BB End + 5 uint32_tS reserved to make it aligned for kernel read 57 #define CODECHAL_ENCODE_VP9_MIN_TILE_SIZE_WIDTH 256 58 #define CODECHAL_ENCODE_VP9_MIN_TILE_SIZE_HEIGHT 128 59 #define CODECHAL_ENCODE_VP9_NUM_MAX_L0_REF 3 60 #define CODECHAL_ENCODE_VP9_HUC_SUPERFRAME_PASS 2 61 #define CODECHAL_ENCODE_VP9_REF_SEGMENT_DISABLED 0xFF 62 #define CODECHAL_ENCODE_VP9_BRC_MAX_NUM_OF_PASSES 4 63 #define CODECHAL_ENCODE_VP9_CQP_NUM_OF_PASSES 2 64 #define CODECHAL_ENCODE_VP9_BRC_DEFAULT_NUM_OF_PASSES 2 // 2 Passes minimum so HuC is Run twice, second PAK is conditional. 65 #define CODECHAL_ENCODE_VP9_BRC_HISTORY_BUFFER_SIZE 768 66 #define CODECHAL_ENCODE_VP9_BRC_CONSTANTSURFACE_SIZE 17792 67 #define CODECHAL_ENCODE_VP9_SEGMENT_STATE_BUFFER_SIZE 256 68 #define CODECHAL_ENCODE_VP9_BRC_BITSTREAM_SIZE_BUFFER_SIZE 16 69 #define CODECHAL_ENCODE_VP9_BRC_MSDK_PAK_BUFFER_SIZE 64 70 #define CODECHAL_VDENC_VP9_BRC_HUC_STATUS_ERROR_MASK (1 << 30) 71 #define CODECHAL_VDENC_VP9_BRC_HUC_STATUS_ARITHMETIC_OVERFLOW_ERROR_MASK (1 << 27) 72 #define CODECHAL_VDENC_VP9_BRC_HUC_STATUS_MEMORY_ACCESS_ERROR_MASK (1 << 26) 73 #define CODECHAL_VDENC_VP9_BRC_HUC_STATUS_DMEM_ERROR_MASK (1 << 24) 74 75 #define VP9SWBRCLIB "VP9BRCDLL.dll" 76 77 typedef struct _HUC_AUX_BUFFER 78 { 79 uint32_t Function; // reserved for function related flags 80 uint32_t HuCStatus; // HuC Status 81 uint8_t BRC_PrevSceneChgType_U8; 82 uint8_t BRC_PrevSceneChgFrmAway_U8; 83 uint8_t rsvd2; 84 uint8_t rsvd3; 85 uint32_t RSVD[13]; 86 } HUC_AUX_BUFFER, *PHUC_AUX_BUFFER; 87 88 #define ENCODE_VP9_8K_PIC_WIDTH 8192 89 #define ENCODE_VP9_8K_PIC_HEIGHT 8192 90 #define ENCODE_VP9_16K_PIC_WIDTH 16384 91 #define ENCODE_VP9_16K_PIC_HEIGHT 16384 92 93 extern const uint8_t Keyframe_Default_Probs[2048]; 94 extern const uint8_t Inter_Default_Probs[2048]; 95 extern const uint8_t LF_VALUE_QP_LOOKUP[256]; 96 97 //! 98 //! \struct BRC_BITSTREAM_SIZE_BUFFER 99 //! \brief Brc bitstream size buffer 100 //! 101 struct BRC_BITSTREAM_SIZE_BUFFER 102 { 103 uint32_t dwHcpBitstreamByteCountFrame; 104 uint32_t dwHcpImageStatusControl; 105 uint32_t Reserved[2]; 106 }; 107 108 //! 109 //! \struct CU_DATA 110 //! \brief CU data 111 //! 112 struct CU_DATA 113 { 114 // DW0 115 uint32_t cu_size : 2; 116 uint32_t Res_DW0_2_3 : 2; 117 uint32_t cu_part_mode : 2; // 0=2Nx2N,1=2NxN,2=Nx2N,3=NxN(8x8 only) 118 uint32_t Res_DW0_6_7 : 2; 119 uint32_t intra_chroma_mode0 : 4; // 0=DC,1=V,2=H,3=TM,4=D45,5=D135,6=D117,7=D153,8=D207,9=D63 120 uint32_t Res_DW0_12_15 : 4; 121 uint32_t intra_chroma_mode1 : 4; // 0=DC,1=V,2=H,3=TM,4=D45,5=D135,6=D117,7=D153,8=D207,9=D63 122 uint32_t cu_pred_mode0 : 1; // 1=Intra,0=Inter 123 uint32_t cu_pred_mode1 : 1; 124 uint32_t Res_DW0_23_22 : 2; 125 uint32_t interpred_comp0 : 1; // 0=single,1=compound 126 uint32_t interpred_comp1 : 1; 127 uint32_t Res_DW0_31_26 : 6; 128 129 //DW1 130 uint32_t intra_mode0 : 4; // 0=DC,1=V,2=H,3=TM,4=D45,5=D135,6=D117,7=D153,8=D207,9=D63 131 uint32_t Res_DW1_4_7 : 4; 132 uint32_t intra_mode1 : 4; // 0=DC,1=V,2=H,3=TM,4=D45,5=D135,6=D117,7=D153,8=D207,9=D63 133 uint32_t Res_DW1_12_15 : 4; 134 uint32_t intra_mode2 : 4; // 0=DC,1=V,2=H,3=TM,4=D45,5=D135,6=D117,7=D153,8=D207,9=D63 135 uint32_t Res_DW1_20_23 : 4; 136 uint32_t intra_mode3 : 4; // 0=DC,1=V,2=H,3=TM,4=D45,5=D135,6=D117,7=D153,8=D207,9=D63 137 uint32_t Res_DW1_28_31 : 4; 138 139 //DW2 140 int16_t mvx_l0_part0 : 16; 141 int16_t mvy_l0_part0 : 16; 142 143 //DW3 144 int16_t mvx_l0_part1 : 16; 145 int16_t mvy_l0_part1 : 16; 146 147 //DW4 148 int16_t mvx_l0_part2 : 16; 149 int16_t mvy_l0_part2 : 16; 150 151 //DW5 152 int16_t mvx_l0_part3 : 16; 153 int16_t mvy_l0_part3 : 16; 154 155 //DW6 156 int16_t mvx_l1_part0 : 16; 157 int16_t mvy_l1_part0 : 16; 158 159 //DW7 160 int16_t mvx_l1_part1 : 16; 161 int16_t mvy_l1_part1 : 16; 162 163 //DW8 164 int16_t mvx_l1_part2 : 16; 165 int16_t mvy_l1_part2 : 16; 166 167 //DW9 168 int16_t mvx_l1_part3 : 16; 169 int16_t mvy_l1_part3 : 16; 170 171 //DW10 172 uint32_t refframe_part0_l0 : 2; // 0=intra,1=last,2=golden,3=altref 173 uint32_t Res_DW10_2_3 : 2; 174 uint32_t refframe_part1_l0 : 2; // 0=intra,1=last,2=golden,3=altref 175 uint32_t Res_DW10_6_7 : 2; 176 uint32_t refframe_part0_l1 : 2; // 0=intra,1=last,2=golden,3=altref 177 uint32_t Res_DW10_10_11 : 2; 178 uint32_t refframe_part1_l1 : 2; // 0=intra,1=last,2=golden,3=altref 179 uint32_t Res_DW10_14_15 : 2; 180 uint32_t round_part0 : 3; 181 uint32_t Res_DW10_19 : 1; 182 uint32_t round_part1 : 3; 183 uint32_t Res_DW10_23_31 : 9; 184 185 //DW11 186 uint32_t tu_size0 : 2; 187 uint32_t tu_size1 : 2; 188 uint32_t Res_DW11_4_13 : 10; 189 uint32_t segidx_pred0 : 1; 190 uint32_t segidx_pred1 : 1; 191 uint32_t segidx_part0 : 3; 192 uint32_t segidx_part1 : 3; 193 uint32_t mc_filtertype_part0 : 2; 194 uint32_t mc_filtertype_part1 : 2; 195 uint32_t Res_DW11_26_31 : 6; 196 197 uint32_t Res_DW12 : 32; 198 199 uint32_t Res_DW13 : 32; 200 201 uint32_t Res_DW14 : 32; 202 203 uint32_t Res_DW15 : 32; 204 205 }; 206 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CU_DATA)) == 16); 207 208 //! 209 //! \enum VP9_MBBRC_MODE 210 //! \brief VP9 mbbrc mode 211 //! 212 enum VP9_MBBRC_MODE 213 { 214 //Target usage determines whether MBBRC is enabled or not. 215 //Currently for all the target usages it is enabled. 216 //once the performance is measured for performance TU mode, decision will be taken 217 //whether to enable or disable MBBRC. 218 MBBRC_ENABLED_TU_DEPENDENCY = 0, 219 MBBRC_ENABLED = 1, 220 MBBRC_DISABLED = 2 221 222 }; 223 224 //! 225 //! \enum TU_MODE 226 //! \brief TU mode 227 //! 228 enum TU_MODE 229 { 230 TU_QUALITY = 1, 231 TU_NORMAL = 4, 232 TU_PERFORMANCE = 7 233 }; 234 235 //! 236 //! \enum DYS_REF_FLAGS 237 //! \brief DYS reference flags 238 //! 239 enum DYS_REF_FLAGS 240 { 241 DYS_REF_NONE = 0, 242 DYS_REF_LAST = (1 << 0), 243 DYS_REF_GOLDEN = (1 << 1), 244 DYS_REF_ALT = (1 << 2), 245 }; 246 247 //! 248 //! \enum PRED_MODE 249 //! \brief Pred mode 250 //! 251 enum PRED_MODE 252 { 253 PRED_MODE_SINGLE = 0, 254 PRED_MODE_COMPOUND = 1, 255 PRED_MODE_HYBRID = 2 256 }; 257 258 //! 259 //! \class CodechalVdencVp9State 260 //! \brief Codechal Vdenc Vp9 state 261 //! 262 class CodechalVdencVp9State : public CodechalEncoderState 263 { 264 public: 265 //! 266 //! \struct Compressed Header 267 //! \brief Compressed header 268 //! 269 struct CompressedHeader 270 { 271 union { 272 struct { 273 uint8_t valid : 1; // valid =1, invalid = 0 274 uint8_t bin_probdiff : 1; // 1= bin, 0 = prob diff 275 uint8_t prob : 1; // 0 = 128, 1 = 252 276 uint8_t bin : 1; 277 uint8_t reserved : 4; 278 } fields; 279 uint8_t value; 280 }; 281 }; 282 283 //! 284 //! \struct DysSamplerStateParams 285 //! \brief Dys sampler state parameters 286 //! 287 struct DysSamplerStateParams 288 { 289 PMHW_KERNEL_STATE pKernelState; 290 }; 291 292 //! 293 //! \struct DysCurbeParams 294 //! \brief Dys curbe parameters 295 //! 296 struct DysCurbeParams 297 { 298 uint32_t dwInputWidth; 299 uint32_t dwInputHeight; 300 uint32_t dwOutputWidth; 301 uint32_t dwOutputHeight; 302 PMHW_KERNEL_STATE pKernelState; 303 }; 304 305 //! 306 //! \struct DysKernelParams 307 //! \brief Dys kernel parameters 308 //! 309 struct DysKernelParams 310 { 311 uint32_t dwInputWidth; 312 uint32_t dwInputHeight; 313 uint32_t dwOutputWidth; 314 uint32_t dwOutputHeight; 315 PMOS_SURFACE psInputSurface; 316 PMOS_SURFACE psOutputSurface; 317 }; 318 319 //! 320 //! \struct HcpPakObject 321 //! \brief HCP pak object 322 //! 323 struct HcpPakObject 324 { 325 // DW0 326 struct 327 { 328 uint32_t DwordLength : 16; //[15:0] 329 uint32_t SubOp : 7; //[22:16] 330 uint32_t Opcode : 6; //[28:23] 331 uint32_t Type : 3; //[31:29] 332 } DW0; 333 334 //DW1 335 struct 336 { 337 uint32_t Split_flag_level2_level1part0 : 4; 338 uint32_t Split_flag_level2_level1part1 : 4; 339 uint32_t Split_flag_level2_level1part2 : 4; 340 uint32_t Split_flag_level2_level1part3 : 4; 341 uint32_t Split_flag_level1 : 4; 342 uint32_t Split_flag_level0 : 1; 343 uint32_t Reserved21_23 : 3; 344 uint32_t CU_count_minus1 : 6; 345 uint32_t IsLastSBFrameflag : 1; 346 uint32_t IsLastSBTileflag : 1; 347 } DW1; 348 349 //DW2 350 struct 351 { 352 uint32_t Current_SB_X_Addr : 16; 353 uint32_t Current_SB_Y_Addr : 16; 354 } DW2; 355 356 //DW3 357 uint32_t Reserved_DW03 : 32; 358 359 }; 360 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(HcpPakObject)) == 4); 361 362 //! 363 //! \struct HucFrameCtrl 364 //! \brief HUC frame contol 365 //! 366 struct HucFrameCtrl 367 { 368 uint32_t FrameType; //0:INTRA, 1:INTER // DW15 369 uint32_t ShowFrame; // DW16 370 uint32_t ErrorResilientMode; // DW17 371 uint32_t IntraOnly; // DW18 372 uint32_t ContextReset; // DW19 373 uint32_t LastRefFrameBias; // DW20 374 uint32_t GoldenRefFrameBias; // DW21 375 uint32_t AltRefFrameBias; // DW22 376 uint32_t AllowHighPrecisionMv; // DW23 377 uint32_t McompFilterMode; // DW24 378 uint32_t TxMode; // DW25 379 uint32_t RefreshFrameContext; // DW26 380 uint32_t FrameParallelDecode; // DW27 381 uint32_t CompPredMode; // DW28 382 uint32_t FrameContextIdx; // DW29 383 uint32_t SharpnessLevel; // DW30 384 uint32_t SegOn; // DW31 385 uint32_t SegMapUpdate; // DW32 386 uint32_t SegUpdateData; // DW33 387 uint8_t Rsvd[13]; // DW34-36, first byte of 37 388 uint8_t log2TileCols; // DW37 389 uint8_t log2TileRows; // DW37 390 uint8_t Reserved[5]; // DW37 last byte, DW38 391 }; 392 393 //! 394 //! \struct HucBrcBuffers 395 //! \brief HUC brc buffers 396 //! 397 struct HucBrcBuffers 398 { 399 MOS_RESOURCE resBrcHistoryBuffer; 400 MOS_RESOURCE resBrcConstantDataBuffer[2]; // 0 == I, 1 == P 401 MOS_RESOURCE resBrcMsdkPakBuffer; 402 MOS_RESOURCE resBrcMbEncCurbeWriteBuffer; 403 MOS_RESOURCE resMbEncAdvancedDsh; 404 MOS_RESOURCE resPicStateBrcReadBuffer; 405 MOS_RESOURCE resPicStateBrcWriteHucReadBuffer; 406 MOS_RESOURCE resPicStateHucWriteBuffer; 407 MOS_RESOURCE resSegmentStateBrcReadBuffer; 408 MOS_RESOURCE resSegmentStateBrcWriteBuffer; 409 MOS_RESOURCE resBrcBitstreamSizeBuffer; 410 MOS_RESOURCE resBrcHucDataBuffer; 411 }; 412 //! 413 //! \struct HucPrevFrameInfo 414 //! \brief HUC definition: PrevFrameInfo 415 //! 416 struct HucPrevFrameInfo 417 { 418 uint32_t IntraOnly; // DW39 419 uint32_t FrameWidth; // DW40 420 uint32_t FrameHeight; // DW41 421 uint32_t KeyFrame; // DW42 422 uint32_t ShowFrame; // DW43 423 }; 424 425 //! 426 //! \struct HucProbDmem 427 //! \brief HUC prob dmem 428 //! 429 struct HucProbDmem 430 { 431 uint32_t HuCPassNum; 432 uint32_t FrameWidth; 433 uint32_t FrameHeight; 434 uint32_t Rsvd32[6]; 435 char SegmentRef[CODEC_VP9_MAX_SEGMENTS]; 436 uint8_t SegmentSkip[CODEC_VP9_MAX_SEGMENTS]; 437 uint8_t SegCodeAbs; 438 uint8_t SegTemporalUpdate; 439 uint8_t LastRefIndex; 440 uint8_t GoldenRefIndex; 441 uint8_t AltRefIndex; 442 uint8_t RefreshFrameFlags; 443 uint8_t RefFrameFlags; 444 uint8_t ContextFrameTypes; 445 HucFrameCtrl FrameCtrl; 446 HucPrevFrameInfo PrevFrameInfo; 447 uint8_t Rsvd[2]; 448 uint8_t FrameToShow; 449 uint8_t LoadKeyFrameDefaultProbs; 450 uint32_t FrameSize; 451 uint32_t Reserved1; 452 uint32_t RePak; 453 uint16_t LFLevelBitOffset; 454 uint16_t QIndexBitOffset; 455 uint16_t SegBitOffset; 456 uint16_t SegLengthInBits; 457 uint16_t UnCompHdrTotalLengthInBits; 458 uint16_t SegUpdateDisable; 459 int32_t RePakThreshold[256]; 460 uint16_t PicStateOffset; 461 uint16_t SLBBSize; 462 uint8_t StreamInEnable; 463 uint8_t StreamInSegEnable; 464 uint8_t DisableDMA; 465 uint8_t IVFHeaderSize; 466 uint8_t Reserved[44]; 467 }; 468 469 //! 470 //! \struct HucBrcInitDmem 471 //! \brief HUC brc init dmem 472 //! 473 struct HucBrcInitDmem 474 { 475 uint32_t BRCFunc; // 0: Init; 2: Reset 476 uint32_t ProfileLevelMaxFrame; // Limit on maximum frame size based on selected profile and level, and can be user defined 477 uint32_t InitBufFullness; // Initial buffer fullness 478 uint32_t BufSize; // Buffer size 479 uint32_t TargetBitrate; // Average(target) bit rate 480 uint32_t MaxRate; // Maximum bit rate in bits per second (bps). 481 uint32_t MinRate; // Minimum bit rate 482 uint32_t FrameRateM; // Framerate numerator 483 uint32_t FrameRateD; // Framerate denominator 484 uint32_t RSVD32[4]; // Reserved, MBZ 485 486 uint16_t BRCFlag; // BRC flag 487 uint16_t GopP; // number of P frames in a GOP 488 uint16_t Reserved; 489 uint16_t FrameWidth; // Frame width 490 uint16_t FrameHeight; // Frame height 491 uint16_t MinQP; // Minimum QP 492 uint16_t MaxQP; // Maximum QP 493 uint16_t LevelQP; // Level QP 494 uint16_t GoldenFrameInterval; // Golden frame interval 495 uint16_t EnableScaling; // Enable resolution scaling 496 uint16_t OvershootCBR; // default: 115, CBR overshoot percentage 497 uint16_t RSVD16[5]; // Reserved, MBZ 498 499 int8_t InstRateThreshP0[4]; // Instant rate threshold for P frame 500 int8_t Reserved2[4]; 501 int8_t InstRateThreshI0[4]; 502 int8_t DevThreshPB0[8]; // Deviation threshold for P and B frame 503 int8_t DevThreshVBR0[8]; // Deviation threshold for VBR control 504 int8_t DevThreshI0[8]; // Deviation threshold for I frame 505 506 uint8_t InitQPP; 507 uint8_t InitQPI; 508 uint8_t RSVD3; 509 uint8_t Total_Level; 510 uint8_t MaxLevel_Ratio[16]; 511 uint8_t SlidingWindowEnable; 512 uint8_t SlidingWindowSize; 513 uint8_t RSVD8[47]; // Reserved, MBZ 514 }; 515 516 //! 517 //! \struct HucBrcUpdateDmem 518 //! \brief HUC brc update dmem 519 //! 520 struct HucBrcUpdateDmem 521 { 522 int32_t UPD_TARGET_BUF_FULLNESS_U32; //passed by the driver 523 uint32_t UPD_FRAMENUM_U32; //passed by the driver 524 int32_t UPD_HRD_BUFF_FULLNESS_UPPER_I32; //passed by the driver 525 int32_t UPD_HRD_BUFF_FULLNESS_LOWER_I32; //passed by the driver 526 uint32_t RSVD32[7]; // mbz 527 528 uint16_t UPD_startGAdjFrame_U16[4]; // start global adjust frame (4 items) 529 uint16_t UPD_CurWidth_U16; // current width 530 uint16_t UPD_CurHeight_U16; // current height 531 uint16_t UPD_Asyn_U16; 532 uint16_t UPD_VDEncImgStateOffset; // the image state start position in bytes from the begining of Second Level BB 533 uint16_t UPD_SLBBSize; // second level batch buffer total size in bytes 534 uint16_t UPD_PicStateOffset; // the pic state offset in bytes from the beginning of second level batch buffer 535 uint16_t RSVD16[6]; // mbz 536 537 uint8_t UPD_OVERFLOW_FLAG_U8; //passed by the driver 538 uint8_t UPD_BRCFlag_U8; //BRC flag, 0 - nothing to report, others - BRCPIC\BRCCUR flag defines 1 - scene change, etc // RSVD on G10, remove when G11 drops dependency 539 uint8_t UPD_MaxNumPAKs_U8; //maximum number of PAKs (default set to 4) 540 int8_t UPD_CurrFrameType_U8; //current frame type (0:P, 1:B, 2:I) 541 uint8_t UPD_QPThreshold_U8[4]; // QP threshold (4 entries) 542 uint8_t UPD_gRateRatioThreshold_U8[6]; // global rate ratio threshold (6 items) 543 int8_t UPD_startGAdjMult_U8[5]; // start global adjust mult (5 items) 544 int8_t UPD_startGAdjDiv_U8[5]; // start global adjust div (5 items) 545 int8_t UPD_gRateRatioThresholdQP_U8[7]; // global rate ratio threshold QP (7 items) 546 uint8_t UPD_DistThreshldI_U8[9]; //(N_DISTORION_THRESHLDS+1) distortion thresholds for I frames 547 uint8_t UPD_DistThreshldP_U8[9]; //(N_DISTORION_THRESHLDS+1) distortion thresholds for P frames 548 uint8_t UPD_DistThreshldB_U8[9]; //(N_DISTORION_THRESHLDS+1) distortion thresholds for B frames; no needed for Vp8 - to clean up 549 int8_t UPD_MaxFrameThreshI_U8[5]; //num qp threshld + 1 of multiplyers 550 int8_t UPD_MaxFrameThreshP_U8[5]; //num qp threshld + 1 of multiplyers 551 int8_t UPD_MaxFrameThreshB_U8[5]; //num qp threshld + 1 of multiplyers; no needed for Vp8 - to clean up 552 uint8_t UPD_PAKPassNum_U8; // current pak pass number 553 uint8_t UPD_ACQQp_U8; 554 int8_t UPD_DeltaQPForSadZone0_I8; 555 int8_t UPD_DeltaQPForSadZone1_I8; 556 int8_t UPD_DeltaQPForSadZone2_I8; 557 int8_t UPD_DeltaQPForSadZone3_I8; 558 int8_t UPD_DeltaQPForMvZero_I8; 559 int8_t UPD_DeltaQPForMvZone0_I8; 560 int8_t UPD_DeltaQPForMvZone1_I8; 561 int8_t UPD_DeltaQPForMvZone2_I8; 562 uint8_t UPD_Temporal_Level_U8; 563 uint8_t UPD_SegMapGenerating_U8; // Default 0: HuC does not update segmentation state; 1: HuC updates all 8 segmentation states in second level batch buffer 564 uint8_t RSVD8[95]; // mbz 565 }; 566 567 //! 568 //! \struct HucBrcDataBuffer 569 //! \brief HUC brc data buffer 570 //! 571 struct HucBrcDataBuffer 572 { 573 //DW0-DW4 574 uint32_t Reserved1[5]; 575 576 // DW5 577 union 578 { 579 struct 580 { 581 uint32_t NextFrameWidth : MOS_BITFIELD_RANGE(0, 15); 582 uint32_t NextFrameHeight : MOS_BITFIELD_RANGE(16, 31); 583 }; 584 struct 585 { 586 uint32_t Value; 587 }; 588 } DW5; 589 590 // DW6, DW7 591 uint32_t Reserved2[2]; 592 }; 593 594 //! 595 //! \struct DysBindingTable 596 //! \brief Dys binding table 597 //! 598 struct DysBindingTable 599 { 600 uint32_t dysInputFrameNv12 = 0; 601 uint32_t dysOutputFrameY = 1; 602 uint32_t dysOutputFrameUV = 2; 603 }; 604 605 //! 606 //! \struct DysSurfaceParams 607 //! \brief Dys surface data 608 //! 609 struct DysSurfaceParams 610 { 611 PMOS_SURFACE inputFrameSurface; 612 PMOS_SURFACE outputFrameSurface; 613 uint32_t verticalLineStride; 614 uint32_t verticalLineStrideOffset; 615 DysBindingTable* dysBindingTable; 616 PMHW_KERNEL_STATE kernelState; 617 }; 618 619 //! 620 //! \struct DysStaticData 621 //! \brief Dys static data 622 //! 623 struct DysStaticData 624 { 625 // DW0 626 union 627 { 628 struct 629 { 630 uint32_t InputFrameWidth : MOS_BITFIELD_RANGE(0, 15); 631 uint32_t InputFrameHeight : MOS_BITFIELD_RANGE(16, 31); 632 }; 633 struct 634 { 635 uint32_t Value; 636 }; 637 } DW0; 638 639 // DW1 640 union 641 { 642 struct 643 { 644 uint32_t OutputFrameWidth : MOS_BITFIELD_RANGE(0, 15); 645 uint32_t OutputFrameHeight : MOS_BITFIELD_RANGE(16, 31); 646 }; 647 struct 648 { 649 uint32_t Value; 650 }; 651 } DW1; 652 653 // DW2 654 union 655 { 656 struct 657 { 658 float DeltaU; 659 }; 660 661 uint32_t Value; 662 } DW2; 663 664 // DW3 665 union 666 { 667 struct 668 { 669 float DeltaV; 670 }; 671 672 uint32_t Value; 673 } DW3; 674 675 // DW4 - DW15 676 uint32_t Reserved[12]; 677 678 // DW16 679 union 680 { 681 struct 682 { 683 uint32_t InputFrameNV12SurfBTI : MOS_BITFIELD_RANGE(0, 31); 684 }; 685 struct 686 { 687 uint32_t Value; 688 }; 689 } DW16; 690 691 // DW17 692 union 693 { 694 struct 695 { 696 uint32_t OutputFrameYSurfBTI : MOS_BITFIELD_RANGE(0, 31); 697 }; 698 struct 699 { 700 uint32_t Value; 701 }; 702 } DW17; 703 704 // DW18 705 union 706 { 707 struct 708 { 709 uint32_t AVSSampleIdx : MOS_BITFIELD_RANGE(0, 31); 710 }; 711 struct 712 { 713 uint32_t Value; 714 }; 715 } DW18; 716 }; 717 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(DysStaticData)) == 19); 718 719 typedef enum VP9BufferType 720 { 721 eVp9UnknownBuff = 0, 722 eVp9INLINE_DMEM, 723 eVp9HISTORY_BUFF, 724 eVp9VDENC_STATISTICS_BUFF, 725 eVp9PAK_STATISTICS_BUFF, 726 eVp9INPUT_SLBB_BUFF, 727 eVp9BRC_DATA_BUFF, 728 eVp9CONSTANT_DATA_BUFF, 729 eVp9OUTPUT_SLBB_BUFF, 730 eVp9PAKMMIO_BUFF, 731 eVp9AUX_BUFF 732 } VP9BufferType; 733 734 //! 735 //! \struct VdencVmeState 736 //! \brief Vdenc vme state 737 //! 738 struct VdencVmeState 739 { 740 PCODEC_REF_LIST pRefList[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC]; 741 CODEC_PIC_ID PicIdx[CODEC_MAX_NUM_REF_FRAME_HEVC]; 742 MOS_SURFACE s16xMeMvDataBuffer; 743 MOS_SURFACE s4xMeMvDataBuffer; 744 MOS_SURFACE s32xMeMvDataBuffer; 745 MOS_SURFACE s4xMeDistortionBuffer; 746 uint8_t Level; 747 uint16_t direct_spatial_mv_pred_flag; 748 uint32_t dwBiWeight; 749 bool bFirstFieldIdrPic; 750 bool bMbaff; 751 EncodeBrcBuffers BrcBuffer; 752 753 bool b16xMeInUse; 754 bool b4xMeInUse; 755 bool segmapProvided; 756 757 //Sequence Params 758 uint8_t TargetUsage; 759 uint8_t GopRefDist; 760 761 //Picture Params 762 CODEC_PICTURE CurrOriginalPic; 763 int8_t QpY; 764 765 //Slice Params 766 CODEC_PICTURE RefPicList[2][CODEC_MAX_NUM_REF_FRAME_HEVC]; 767 uint8_t num_ref_idx_l0_active_minus1; // [0..15] 768 uint8_t num_ref_idx_l1_active_minus1; // [0..15] 769 int8_t slice_qp_delta; 770 }; 771 772 //! 773 //! \struct VdencMeCurbe 774 //! \brief Vdenc Me curbe 775 //! 776 struct VdencMeCurbe 777 { 778 // DW0 779 union 780 { 781 struct 782 { 783 uint32_t SkipModeEn : MOS_BITFIELD_BIT( 0 ); 784 uint32_t AdaptiveEn : MOS_BITFIELD_BIT( 1 ); 785 uint32_t BiMixDis : MOS_BITFIELD_BIT( 2 ); 786 uint32_t : MOS_BITFIELD_RANGE( 3, 4 ); 787 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT( 5 ); 788 uint32_t : MOS_BITFIELD_BIT( 6 ); 789 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT( 7 ); 790 uint32_t : MOS_BITFIELD_RANGE( 8,23 ); 791 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE( 24,31 ); 792 }; 793 struct 794 { 795 uint32_t Value; 796 }; 797 } DW0; 798 799 // DW1 800 union 801 { 802 struct 803 { 804 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE( 0, 5 ); 805 uint32_t : MOS_BITFIELD_RANGE( 6,15 ); 806 uint32_t BiWeight : MOS_BITFIELD_RANGE( 16,21 ); 807 uint32_t : MOS_BITFIELD_RANGE( 22,27 ); 808 uint32_t UniMixDisable : MOS_BITFIELD_BIT( 28 ); 809 uint32_t : MOS_BITFIELD_RANGE( 29,31 ); 810 }; 811 struct 812 { 813 uint32_t Value; 814 }; 815 } DW1; 816 817 // DW2 818 union 819 { 820 struct 821 { 822 uint32_t MaxLenSP : MOS_BITFIELD_RANGE( 0, 7 ); 823 uint32_t MaxNumSU : MOS_BITFIELD_RANGE( 8, 15 ); 824 uint32_t : MOS_BITFIELD_RANGE( 16, 31); 825 }; 826 struct 827 { 828 uint32_t Value; 829 }; 830 } DW2; 831 832 // DW3 833 union 834 { 835 struct 836 { 837 uint32_t SrcSize : MOS_BITFIELD_RANGE( 0, 1 ); 838 uint32_t : MOS_BITFIELD_RANGE( 2, 3 ); 839 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE( 4, 5 ); 840 uint32_t SrcAccess : MOS_BITFIELD_BIT( 6 ); 841 uint32_t RefAccess : MOS_BITFIELD_BIT( 7 ); 842 uint32_t SearchCtrl : MOS_BITFIELD_RANGE( 8,10 ); 843 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT( 11 ); 844 uint32_t SubPelMode : MOS_BITFIELD_RANGE( 12,13 ); 845 uint32_t SkipType : MOS_BITFIELD_BIT( 14 ); 846 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT( 15 ); 847 uint32_t InterChromaMode : MOS_BITFIELD_BIT( 16 ); 848 uint32_t FTEnable : MOS_BITFIELD_BIT( 17 ); 849 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT( 18 ); 850 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT( 19 ); 851 uint32_t InterSAD : MOS_BITFIELD_RANGE( 20,21 ); 852 uint32_t IntraSAD : MOS_BITFIELD_RANGE( 22,23 ); 853 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE( 24,30 ); 854 uint32_t : MOS_BITFIELD_BIT( 31 ); 855 }; 856 struct 857 { 858 uint32_t Value; 859 }; 860 } DW3; 861 862 // DW4 863 union 864 { 865 struct 866 { 867 uint32_t : MOS_BITFIELD_RANGE(0, 7); 868 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE(8, 15); 869 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 870 uint32_t : MOS_BITFIELD_RANGE(24, 31); 871 }; 872 struct 873 { 874 uint32_t Value; 875 }; 876 } DW4; 877 878 // DW5 879 union 880 { 881 struct 882 { 883 uint32_t : MOS_BITFIELD_RANGE(0, 7); 884 uint32_t QpPrimeY : MOS_BITFIELD_RANGE(8, 15); 885 uint32_t RefWidth : MOS_BITFIELD_RANGE( 16,23 ); 886 uint32_t RefHeight : MOS_BITFIELD_RANGE( 24,31 ); 887 }; 888 struct 889 { 890 uint32_t Value; 891 }; 892 } DW5; 893 894 // DW6 895 union 896 { 897 struct 898 { 899 uint32_t : MOS_BITFIELD_BIT(0); 900 uint32_t InputStreamInEn : MOS_BITFIELD_BIT(1); 901 uint32_t LCUSize : MOS_BITFIELD_BIT(2); 902 uint32_t WriteDistortions : MOS_BITFIELD_BIT(3); 903 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT(4); 904 uint32_t : MOS_BITFIELD_RANGE(5, 7); 905 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE(8, 15); 906 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 907 }; 908 struct 909 { 910 uint32_t Value; 911 }; 912 } DW6; 913 914 // DW7 915 union 916 { 917 struct 918 { 919 uint32_t : MOS_BITFIELD_RANGE(0, 15); 920 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE( 16,17 ); 921 uint32_t BilinearEnable : MOS_BITFIELD_BIT( 18 ); 922 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT( 19 ); 923 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT( 20 ); 924 uint32_t AConlyHAAR : MOS_BITFIELD_BIT( 21 ); 925 uint32_t RefIDCostMode : MOS_BITFIELD_BIT( 22 ); 926 uint32_t : MOS_BITFIELD_BIT( 23 ); 927 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE( 24,31 ); 928 }; 929 struct 930 { 931 uint32_t Value; 932 }; 933 } DW7; 934 935 // DW8 936 union 937 { 938 struct 939 { 940 uint32_t Mode0Cost : MOS_BITFIELD_RANGE( 0, 7 ); 941 uint32_t Mode1Cost : MOS_BITFIELD_RANGE( 8,15 ); 942 uint32_t Mode2Cost : MOS_BITFIELD_RANGE( 16,23 ); 943 uint32_t Mode3Cost : MOS_BITFIELD_RANGE( 24,31 ); 944 }; 945 struct 946 { 947 uint32_t Value; 948 }; 949 } DW8; 950 951 // DW9 952 union 953 { 954 struct 955 { 956 uint32_t Mode4Cost : MOS_BITFIELD_RANGE( 0, 7 ); 957 uint32_t Mode5Cost : MOS_BITFIELD_RANGE( 8,15 ); 958 uint32_t Mode6Cost : MOS_BITFIELD_RANGE( 16,23 ); 959 uint32_t Mode7Cost : MOS_BITFIELD_RANGE( 24,31 ); 960 }; 961 struct 962 { 963 uint32_t Value; 964 }; 965 } DW9; 966 967 // DW10 968 union 969 { 970 struct 971 { 972 uint32_t Mode8Cost : MOS_BITFIELD_RANGE( 0, 7 ); 973 uint32_t Mode9Cost : MOS_BITFIELD_RANGE( 8,15 ); 974 uint32_t RefIDCost : MOS_BITFIELD_RANGE( 16,23 ); 975 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE( 24,31 ); 976 }; 977 struct 978 { 979 uint32_t Value; 980 }; 981 } DW10; 982 983 // DW11 984 union 985 { 986 struct 987 { 988 uint32_t MV0Cost : MOS_BITFIELD_RANGE( 0, 7 ); 989 uint32_t MV1Cost : MOS_BITFIELD_RANGE( 8,15 ); 990 uint32_t MV2Cost : MOS_BITFIELD_RANGE( 16,23 ); 991 uint32_t MV3Cost : MOS_BITFIELD_RANGE( 24,31 ); 992 }; 993 struct 994 { 995 uint32_t Value; 996 }; 997 } DW11; 998 999 // DW12 1000 union 1001 { 1002 struct 1003 { 1004 uint32_t MV4Cost : MOS_BITFIELD_RANGE( 0, 7 ); 1005 uint32_t MV5Cost : MOS_BITFIELD_RANGE( 8,15 ); 1006 uint32_t MV6Cost : MOS_BITFIELD_RANGE( 16,23 ); 1007 uint32_t MV7Cost : MOS_BITFIELD_RANGE( 24,31 ); 1008 }; 1009 struct 1010 { 1011 uint32_t Value; 1012 }; 1013 } DW12; 1014 1015 // DW13 1016 union 1017 { 1018 struct 1019 { 1020 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE(0, 7); 1021 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE(8, 15); 1022 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 1023 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 1024 uint32_t : MOS_BITFIELD_RANGE(27, 31); 1025 }; 1026 struct 1027 { 1028 uint32_t Value; 1029 }; 1030 } DW13; 1031 1032 // DW14 1033 union 1034 { 1035 struct 1036 { 1037 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT(0); 1038 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT(1); 1039 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT(2); 1040 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT(3); 1041 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT(4); 1042 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT(5); 1043 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT(6); 1044 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT(7); 1045 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT(8); 1046 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT(9); 1047 uint32_t : MOS_BITFIELD_RANGE(10, 31); 1048 }; 1049 struct 1050 { 1051 uint32_t Value; 1052 }; 1053 } DW14; 1054 1055 // DW15 1056 union 1057 { 1058 struct 1059 { 1060 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE(0, 7); 1061 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE(8, 15); 1062 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 1063 }; 1064 struct 1065 { 1066 uint32_t Value; 1067 }; 1068 } DW15; 1069 1070 struct 1071 { 1072 // DW16 1073 union 1074 { 1075 struct 1076 { 1077 SearchPathDelta SPDelta_0; 1078 SearchPathDelta SPDelta_1; 1079 SearchPathDelta SPDelta_2; 1080 SearchPathDelta SPDelta_3; 1081 }; 1082 struct 1083 { 1084 uint32_t Value; 1085 }; 1086 } DW16; 1087 1088 // DW17 1089 union 1090 { 1091 struct 1092 { 1093 SearchPathDelta SPDelta_4; 1094 SearchPathDelta SPDelta_5; 1095 SearchPathDelta SPDelta_6; 1096 SearchPathDelta SPDelta_7; 1097 }; 1098 struct 1099 { 1100 uint32_t Value; 1101 }; 1102 } DW17; 1103 1104 // DW18 1105 union 1106 { 1107 struct 1108 { 1109 SearchPathDelta SPDelta_8; 1110 SearchPathDelta SPDelta_9; 1111 SearchPathDelta SPDelta_10; 1112 SearchPathDelta SPDelta_11; 1113 }; 1114 struct 1115 { 1116 uint32_t Value; 1117 }; 1118 } DW18; 1119 1120 // DW19 1121 union 1122 { 1123 struct 1124 { 1125 SearchPathDelta SPDelta_12; 1126 SearchPathDelta SPDelta_13; 1127 SearchPathDelta SPDelta_14; 1128 SearchPathDelta SPDelta_15; 1129 }; 1130 struct 1131 { 1132 uint32_t Value; 1133 }; 1134 } DW19; 1135 1136 // DW20 1137 union 1138 { 1139 struct 1140 { 1141 SearchPathDelta SPDelta_16; 1142 SearchPathDelta SPDelta_17; 1143 SearchPathDelta SPDelta_18; 1144 SearchPathDelta SPDelta_19; 1145 }; 1146 struct 1147 { 1148 uint32_t Value; 1149 }; 1150 } DW20; 1151 1152 // DW21 1153 union 1154 { 1155 struct 1156 { 1157 SearchPathDelta SPDelta_20; 1158 SearchPathDelta SPDelta_21; 1159 SearchPathDelta SPDelta_22; 1160 SearchPathDelta SPDelta_23; 1161 }; 1162 struct 1163 { 1164 uint32_t Value; 1165 }; 1166 } DW21; 1167 1168 // DW22 1169 union 1170 { 1171 struct 1172 { 1173 SearchPathDelta SPDelta_24; 1174 SearchPathDelta SPDelta_25; 1175 SearchPathDelta SPDelta_26; 1176 SearchPathDelta SPDelta_27; 1177 }; 1178 struct 1179 { 1180 uint32_t Value; 1181 }; 1182 } DW22; 1183 1184 // DW23 1185 union 1186 { 1187 struct 1188 { 1189 SearchPathDelta SPDelta_28; 1190 SearchPathDelta SPDelta_29; 1191 SearchPathDelta SPDelta_30; 1192 SearchPathDelta SPDelta_31; 1193 }; 1194 struct 1195 { 1196 uint32_t Value; 1197 }; 1198 } DW23; 1199 1200 // DW24 1201 union 1202 { 1203 struct 1204 { 1205 SearchPathDelta SPDelta_32; 1206 SearchPathDelta SPDelta_33; 1207 SearchPathDelta SPDelta_34; 1208 SearchPathDelta SPDelta_35; 1209 }; 1210 struct 1211 { 1212 uint32_t Value; 1213 }; 1214 } DW24; 1215 1216 // DW25 1217 union 1218 { 1219 struct 1220 { 1221 SearchPathDelta SPDelta_36; 1222 SearchPathDelta SPDelta_37; 1223 SearchPathDelta SPDelta_38; 1224 SearchPathDelta SPDelta_39; 1225 }; 1226 struct 1227 { 1228 uint32_t Value; 1229 }; 1230 } DW25; 1231 1232 // DW26 1233 union 1234 { 1235 struct 1236 { 1237 SearchPathDelta SPDelta_40; 1238 SearchPathDelta SPDelta_41; 1239 SearchPathDelta SPDelta_42; 1240 SearchPathDelta SPDelta_43; 1241 }; 1242 struct 1243 { 1244 uint32_t Value; 1245 }; 1246 } DW26; 1247 1248 // DW27 1249 union 1250 { 1251 struct 1252 { 1253 SearchPathDelta SPDelta_44; 1254 SearchPathDelta SPDelta_45; 1255 SearchPathDelta SPDelta_46; 1256 SearchPathDelta SPDelta_47; 1257 }; 1258 struct 1259 { 1260 uint32_t Value; 1261 }; 1262 } DW27; 1263 1264 // DW28 1265 union 1266 { 1267 struct 1268 { 1269 SearchPathDelta SPDelta_48; 1270 SearchPathDelta SPDelta_49; 1271 SearchPathDelta SPDelta_50; 1272 SearchPathDelta SPDelta_51; 1273 }; 1274 struct 1275 { 1276 uint32_t Value; 1277 }; 1278 } DW28; 1279 1280 // DW29 1281 union 1282 { 1283 struct 1284 { 1285 SearchPathDelta SPDelta_52; 1286 SearchPathDelta SPDelta_53; 1287 SearchPathDelta SPDelta_54; 1288 SearchPathDelta SPDelta_55; 1289 }; 1290 struct 1291 { 1292 uint32_t Value; 1293 }; 1294 } DW29; 1295 } SPDelta; 1296 1297 // DW30 1298 union 1299 { 1300 struct 1301 { 1302 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE(0, 15); 1303 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 1304 }; 1305 struct 1306 { 1307 uint32_t Value; 1308 }; 1309 } DW30; 1310 1311 // DW31 1312 union 1313 { 1314 struct 1315 { 1316 uint32_t RoiCtrl : MOS_BITFIELD_RANGE( 0, 7 ); 1317 uint32_t MaxTuSize : MOS_BITFIELD_RANGE( 8, 9 ); 1318 uint32_t MaxCuSize : MOS_BITFIELD_RANGE( 10, 11 ); 1319 uint32_t NumImePredictors : MOS_BITFIELD_RANGE( 12, 15 ); 1320 uint32_t Reserved : MOS_BITFIELD_RANGE( 16, 23 ); 1321 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE( 24, 31 ); 1322 }; 1323 struct 1324 { 1325 uint32_t Value; 1326 }; 1327 } DW31; 1328 1329 // DW32 1330 union 1331 { 1332 struct 1333 { 1334 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE(0, 15); 1335 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 1336 }; 1337 struct 1338 { 1339 uint32_t Value; 1340 }; 1341 } DW32; 1342 1343 // DW33 1344 union 1345 { 1346 struct 1347 { 1348 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE(0, 15); 1349 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 1350 }; 1351 struct 1352 { 1353 uint32_t Value; 1354 }; 1355 } DW33; 1356 1357 // DW34 1358 union 1359 { 1360 struct 1361 { 1362 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE(0, 15); 1363 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 1364 }; 1365 struct 1366 { 1367 uint32_t Value; 1368 }; 1369 } DW34; 1370 1371 // DW35 1372 union 1373 { 1374 struct 1375 { 1376 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE(0, 15); 1377 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 1378 }; 1379 struct 1380 { 1381 uint32_t Value; 1382 }; 1383 } DW35; 1384 1385 // DW36 1386 union 1387 { 1388 struct 1389 { 1390 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE(0, 3); 1391 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE(4, 7); 1392 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE(8, 11); 1393 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 1394 uint32_t NumMergeCandCu8x8 : MOS_BITFIELD_RANGE(16, 19); 1395 uint32_t NumMergeCandCu16x16 : MOS_BITFIELD_RANGE(20, 23); 1396 uint32_t NumMergeCandCu32x32 : MOS_BITFIELD_RANGE(24, 27); 1397 uint32_t NumMergeCandCu64x64 : MOS_BITFIELD_RANGE(28, 31); 1398 }; 1399 struct 1400 { 1401 uint32_t Value; 1402 }; 1403 } DW36; 1404 1405 // DW37 1406 union 1407 { 1408 struct 1409 { 1410 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); 1411 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 1412 uint32_t SegIDEnable : MOS_BITFIELD_BIT(20); 1413 uint32_t Reserved : MOS_BITFIELD_RANGE(21, 22); 1414 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT(23); 1415 uint32_t Reserved1 : MOS_BITFIELD_RANGE(24, 31); 1416 }; 1417 struct 1418 { 1419 uint32_t Value; 1420 }; 1421 } DW37; 1422 1423 // DW38 1424 union 1425 { 1426 struct 1427 { 1428 uint32_t ForceQp0 : MOS_BITFIELD_RANGE(0, 7); 1429 uint32_t ForceQp1 : MOS_BITFIELD_RANGE(8, 15); 1430 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 1431 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(24, 31); 1432 }; 1433 struct 1434 { 1435 uint32_t Value; 1436 }; 1437 } DW38; 1438 1439 // DW39 1440 union 1441 { 1442 struct 1443 { 1444 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31); 1445 }; 1446 struct 1447 { 1448 uint32_t Value; 1449 }; 1450 } DW39; 1451 1452 // DW40 1453 union 1454 { 1455 struct 1456 { 1457 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1458 }; 1459 struct 1460 { 1461 uint32_t Value; 1462 }; 1463 } DW40; 1464 1465 // DW41 1466 union 1467 { 1468 struct 1469 { 1470 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1471 }; 1472 struct 1473 { 1474 uint32_t Value; 1475 }; 1476 } DW41; 1477 1478 // DW42 1479 union 1480 { 1481 struct 1482 { 1483 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1484 }; 1485 struct 1486 { 1487 uint32_t Value; 1488 }; 1489 } DW42; 1490 1491 // DW43 1492 union 1493 { 1494 struct 1495 { 1496 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1497 }; 1498 struct 1499 { 1500 uint32_t Value; 1501 }; 1502 } DW43; 1503 1504 // DW44 1505 union 1506 { 1507 struct 1508 { 1509 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1510 }; 1511 struct 1512 { 1513 uint32_t Value; 1514 }; 1515 } DW44; 1516 1517 // DW45 1518 union 1519 { 1520 struct 1521 { 1522 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1523 }; 1524 struct 1525 { 1526 uint32_t Value; 1527 }; 1528 } DW45; 1529 1530 // DW46 1531 union 1532 { 1533 struct 1534 { 1535 uint32_t VDEncStreamInOutputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1536 }; 1537 struct 1538 { 1539 uint32_t Value; 1540 }; 1541 } DW46; 1542 1543 // DW47 1544 union 1545 { 1546 struct 1547 { 1548 uint32_t VDEncStreamInInputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1549 }; 1550 struct 1551 { 1552 uint32_t Value; 1553 }; 1554 } DW47; 1555 }; 1556 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(VdencMeCurbe)) == 48); 1557 1558 /* BinIdx for compressed header generation for PAK */ 1559 /* The first value indicates previous SE index and second value indicates the size of the previous SE*/ 1560 static constexpr uint32_t PAK_TX_MODE_IDX = 0; //idx=0 1561 static constexpr uint32_t PAK_TX_MODE_SELECT_IDX = (PAK_TX_MODE_IDX + 2); //idx=2 1562 static constexpr uint32_t PAK_TX_8x8_PROB_IDX = (PAK_TX_MODE_SELECT_IDX + 1); //idx=3 1563 static constexpr uint32_t PAK_TX_16x16_PROB_IDX = (PAK_TX_8x8_PROB_IDX + 4); //idx=7 1564 static constexpr uint32_t PAK_TX_32x32_PROB_IDX = (PAK_TX_16x16_PROB_IDX + 8); //idx=15 1565 static constexpr uint32_t PAK_TX_4x4_COEFF_PROB_IDX = (PAK_TX_32x32_PROB_IDX + 12); //idx=27 1566 static constexpr uint32_t PAK_TX_8x8_COEFF_PROB_IDX = (PAK_TX_4x4_COEFF_PROB_IDX + 793); //idx=820 1567 static constexpr uint32_t PAK_TX_16x16_COEFF_PROB_IDX = (PAK_TX_8x8_COEFF_PROB_IDX + 793); //idx=1613 1568 static constexpr uint32_t PAK_TX_32x32_COEFF_PROB_IDX = (PAK_TX_16x16_COEFF_PROB_IDX + 793); //idx=2406 1569 static constexpr uint32_t PAK_SKIP_CONTEXT_IDX = (PAK_TX_32x32_COEFF_PROB_IDX + 793); //idx=3199 1570 static constexpr uint32_t PAK_INTER_MODE_CTX_IDX = (PAK_SKIP_CONTEXT_IDX + 6); //idx=3205 1571 static constexpr uint32_t PAK_SWITCHABLE_FILTER_CTX_IDX = (PAK_INTER_MODE_CTX_IDX + 42); //idx=3247 1572 static constexpr uint32_t PAK_INTRA_INTER_CTX_IDX = (PAK_SWITCHABLE_FILTER_CTX_IDX + 16); //idx=3263 1573 static constexpr uint32_t PAK_COMPOUND_PRED_MODE_IDX = (PAK_INTRA_INTER_CTX_IDX + 8); //idx=3271 1574 static constexpr uint32_t PAK_HYBRID_PRED_CTX_IDX = (PAK_COMPOUND_PRED_MODE_IDX + 2); //idx=3273 1575 static constexpr uint32_t PAK_SINGLE_REF_PRED_CTX_IDX = (PAK_HYBRID_PRED_CTX_IDX + 10); //idx=3283 1576 static constexpr uint32_t PAK_CMPUND_PRED_CTX_IDX = (PAK_SINGLE_REF_PRED_CTX_IDX + 20); //idx=3303 1577 static constexpr uint32_t PAK_INTRA_MODE_PROB_CTX_IDX = (PAK_CMPUND_PRED_CTX_IDX + 10); //idx=3313 1578 static constexpr uint32_t PAK_PARTITION_PROB_IDX = (PAK_INTRA_MODE_PROB_CTX_IDX + 72); //idx=3385 1579 static constexpr uint32_t PAK_MVJOINTS_PROB_IDX = (PAK_PARTITION_PROB_IDX + 96); //idx=3481 1580 static constexpr uint32_t PAK_MVCOMP0_IDX = (PAK_MVJOINTS_PROB_IDX + 24); //idx=3505 1581 static constexpr uint32_t PAK_MVCOMP1_IDX = (PAK_MVCOMP0_IDX + 176); //idx=3681 1582 static constexpr uint32_t PAK_MVFRAC_COMP0_IDX = (PAK_MVCOMP1_IDX + 176); //idx=3857 1583 static constexpr uint32_t PAK_MVFRAC_COMP1_IDX = (PAK_MVFRAC_COMP0_IDX + 72); //idx=3929 1584 static constexpr uint32_t PAK_MVHP_COMP0_IDX = (PAK_MVFRAC_COMP1_IDX + 72); //idx=4001 1585 static constexpr uint32_t PAK_MVHP_COMP1_IDX = (PAK_MVHP_COMP0_IDX + 16); //idx=4017 1586 static constexpr uint32_t PAK_COMPRESSED_HDR_SYNTAX_ELEMS = (PAK_MVHP_COMP1_IDX + 16); //=4033 1587 1588 static constexpr uint32_t m_dysStaticDataSize = sizeof(DysStaticData); 1589 1590 static constexpr uint32_t m_brcMaxNumPasses = 3; 1591 static constexpr uint32_t m_numUncompressedSurface = 128; 1592 static constexpr uint32_t m_brcConstantSurfaceSize = 1664; 1593 static constexpr uint32_t m_segmentStateBlockSize = 32; 1594 static constexpr uint32_t m_probabilityCounterBufferSize = 193 * CODECHAL_CACHELINE_SIZE; 1595 1596 static constexpr float m_devStdFps = 30.0; 1597 static constexpr float m_bpsRatioLow = 0.1f; 1598 static constexpr float m_bpsRatioHigh = 3.5; 1599 static constexpr int32_t m_numInstRateThresholds = 4; 1600 static constexpr int32_t m_numDevThresholds = 8; 1601 static constexpr int32_t m_posMultPb = 50; 1602 static constexpr int32_t m_negMultPb = -50; 1603 static constexpr int32_t m_posMultVbr = 100; 1604 static constexpr int32_t m_negMultVbr = -50; 1605 1606 static constexpr uint32_t m_maxMvLen = 511; 1607 1608 static constexpr int8_t m_instRateThresholdI[m_numInstRateThresholds] = { 30, 50, 90, 115 }; 1609 static constexpr int8_t m_instRateThresholdP[m_numInstRateThresholds] = { 30, 50, 70, 120 }; 1610 static constexpr double m_devThresholdFpNegI[m_numDevThresholds / 2] = { 0.80, 0.60, 0.34, 0.2 }; 1611 static constexpr double m_devThresholdFpPosI[m_numDevThresholds / 2] = { 0.2, 0.4, 0.66, 0.9 }; 1612 static constexpr double m_devThresholdFpNegPB[m_numDevThresholds / 2] = { 0.90, 0.66, 0.46, 0.3 }; 1613 static constexpr double m_devThresholdFpPosPB[m_numDevThresholds / 2] = { 0.3, 0.46, 0.70, 0.90 }; 1614 static constexpr double m_devThresholdVbrNeg[m_numDevThresholds / 2] = { 0.90, 0.70, 0.50, 0.3 }; 1615 static constexpr double m_devThresholdVbrPos[m_numDevThresholds / 2] = { 0.4, 0.5, 0.75, 0.90 }; 1616 1617 static constexpr uint32_t m_vdboxHucVp9VdencBrcInitKernelDescriptor = 11; //!< VDBox Huc VDEnc Brc init kernel descriptor 1618 static constexpr uint32_t m_vdboxHucVp9VdencBrcUpdateKernelDescriptor = 12; //!< VDBox Huc VDEnc Brc init kernel descriptor 1619 static constexpr uint32_t m_vdboxHucVp9VdencProbKernelDescriptor = 13; //!< VDBox Huc VDEnc prob kernel descriptor 1620 static constexpr uint32_t m_vdboxHucPakIntegrationKernelDescriptor = 15; //!< VDBox Huc PAK integration kernel descriptor 1621 1622 static const uint32_t m_vdencMeCurbeInit[48]; 1623 static const uint32_t m_brcInitDmem[48]; 1624 static const uint32_t m_brcUpdateDmem[64]; 1625 static const uint32_t m_probDmem[320]; 1626 static const uint32_t m_brcConstData[2][416]; 1627 static const uint32_t m_samplerFilterCoeffs[32][6]; 1628 1629 static const uint32_t m_dysNumSurfaces = 3; 1630 1631 static constexpr uint16_t m_cmd1Size = 120; 1632 static constexpr uint16_t m_cmd2Size = 148; 1633 1634 // Parameters passed from application 1635 PCODEC_VP9_ENCODE_SEQUENCE_PARAMS m_vp9SeqParams = nullptr; //!< Pointer to sequence parameters 1636 PCODEC_VP9_ENCODE_PIC_PARAMS m_vp9PicParams = nullptr; //!< Pointer to picture parameters 1637 PCODEC_VP9_ENCODE_SEGMENT_PARAMS m_vp9SegmentParams = nullptr; //!< Pointer to segment parameters 1638 1639 CODEC_PIC_ID m_picIdx[CODEC_VP9_NUM_REF_FRAMES] = {}; 1640 PCODEC_REF_LIST m_refList[m_numUncompressedSurface] = {}; 1641 PCODECHAL_NAL_UNIT_PARAMS* m_nalUnitParams = nullptr; 1642 uint32_t m_numNalUnit = 0; 1643 1644 uint32_t m_maxPicWidth = 0; 1645 uint32_t m_maxPicHeight = 0; 1646 uint32_t m_picWidthInSb = 0; 1647 uint32_t m_picHeightInSb = 0; 1648 uint32_t m_picSizeInSb = 0; 1649 1650 uint8_t m_txMode = 0; 1651 bool m_hmeEnabled = false; 1652 bool m_16xMeEnabled = false; 1653 bool m_brcEnabled = false; 1654 bool m_brcInit = false; 1655 bool m_brcReset = false; 1656 bool m_advancedDshInUse = false; 1657 bool m_mbBrcEnabled = false; 1658 bool m_waitForEnc = false; 1659 bool m_adaptiveRepakSupported = false; 1660 bool m_tsEnabled = false; 1661 bool m_superFrameHucPass = false; 1662 bool m_storeSingleTaskPhaseSupported = false; //For dynamic scaling, need to save the original state 1663 uint8_t m_refFrameFlags = 0; 1664 uint8_t m_numRefFrames = 0; 1665 uint8_t m_dysRefFrameFlags = 0; 1666 uint8_t m_dysCurrFrameFlag = 0; 1667 uint32_t m_vdencPicStateSecondLevelBatchBufferSize = 0; 1668 1669 MOS_RESOURCE m_resDeblockingFilterLineBuffer; 1670 MOS_RESOURCE m_resDeblockingFilterTileLineBuffer; 1671 MOS_RESOURCE m_resDeblockingFilterTileColumnBuffer; 1672 MOS_RESOURCE m_resMetadataLineBuffer; 1673 MOS_RESOURCE m_resMetadataTileLineBuffer; 1674 MOS_RESOURCE m_resMetadataTileColumnBuffer; 1675 MOS_RESOURCE m_resProbBuffer[CODEC_VP9_NUM_CONTEXTS]; 1676 MOS_RESOURCE m_resSegmentIdBuffer; 1677 MOS_RESOURCE m_resHvcLineRowstoreBuffer; // Handle of HVC Line Row Store surface 1678 MOS_RESOURCE m_resHvcTileRowstoreBuffer; // Handle of HVC Tile Row Store surface 1679 MOS_RESOURCE m_resProbabilityDeltaBuffer; 1680 MOS_RESOURCE m_resTileRecordStrmOutBuffer; 1681 MOS_RESOURCE m_resCuStatsStrmOutBuffer; 1682 MOS_RESOURCE m_resCompressedHeaderBuffer; 1683 MOS_RESOURCE m_resProbabilityCounterBuffer; 1684 MOS_RESOURCE m_resModeDecision[2]; 1685 MOS_RESOURCE m_resFrameStatStreamOutBuffer; 1686 MOS_RESOURCE m_resSseSrcPixelRowStoreBuffer; 1687 1688 bool m_clearAllToKey[CODEC_VP9_NUM_CONTEXTS] = { false }; 1689 bool m_isPreCtx0InterProbSaved = false; 1690 uint8_t m_preCtx0InterProbSaved[CODECHAL_VP9_INTER_PROB_SIZE] = { 0 }; 1691 1692 HucPrevFrameInfo m_prevFrameInfo; 1693 1694 uint8_t m_contextFrameTypes[CODEC_VP9_NUM_CONTEXTS] = { 0 }; 1695 uint8_t m_currMvTemporalBufferIndex = 0; 1696 1697 bool m_hucEnabled = false; 1698 bool m_segmentMapAllocated = false; 1699 MOS_RESOURCE m_resHucProbDmemBuffer[3][CODECHAL_ENCODE_RECYCLED_BUFFER_NUM]; 1700 MOS_RESOURCE m_resHucDefaultProbBuffer; 1701 MOS_RESOURCE m_resHucProbOutputBuffer; 1702 MOS_RESOURCE m_resHucPakInsertUncompressedHeaderReadBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM]; 1703 MOS_RESOURCE m_resHucPakInsertUncompressedHeaderWriteBuffer; 1704 MOS_RESOURCE m_resHucPakMmioBuffer; 1705 MOS_RESOURCE m_resHucDebugOutputBuffer; 1706 MOS_SURFACE m_mbSegmentMapSurface; 1707 MOS_SURFACE m_output16X16InterModes; 1708 1709 uint32_t m_rePakThreshold[CODEC_VP9_QINDEX_RANGE] = { 0 }; 1710 1711 // ME 1712 MOS_SURFACE m_4xMeMvDataBuffer; 1713 MOS_SURFACE m_16xMeMvDataBuffer; 1714 MOS_SURFACE m_4xMeDistortionBuffer; 1715 1716 // BRC 1717 HucBrcBuffers m_brcBuffers = {}; 1718 1719 // DYS 1720 MHW_KERNEL_STATE m_dysKernelState; 1721 DysBindingTable m_dysBindingTable; 1722 uint32_t m_dysDshSize = 0; 1723 1724 // pointer to the reference surfaces 1725 PMOS_SURFACE m_lastRefPic = nullptr; 1726 PMOS_SURFACE m_goldenRefPic = nullptr; 1727 PMOS_SURFACE m_altRefPic = nullptr; 1728 1729 bool m_segmentMapProvided = false; 1730 bool m_dysVdencMultiPassEnabled = false; 1731 bool m_dysHucEnabled = false; 1732 bool m_dysCqp = false; 1733 bool m_dysBrc = false; 1734 bool m_vdencPakonlyMultipassEnabled = false; 1735 bool m_vdencPakObjCmdStreamOutEnabled = false; 1736 bool m_prevFrameSegEnabled = false; 1737 uint32_t m_vdencPictureState2ndLevelBatchBufferSize = 0; 1738 uint16_t m_sadQpLambda = 0; 1739 uint16_t m_rdQpLambda = 0; 1740 uint16_t m_hucPicStateOffset = 0; 1741 uint16_t m_hucSlbbSize = 0; 1742 uint8_t m_vdencMvCosts[12] = { 0 }; 1743 uint8_t m_vdencRdMvCosts[12] = { 0 }; 1744 uint8_t m_vdencHmeMvCosts[8] = { 0 }; 1745 uint8_t m_vdencModeCosts[CODEC_VDENC_NUM_MODE_COST] = { 0 }; 1746 uint32_t *m_mapBuffer = nullptr; 1747 uint32_t m_segStreamInHeight = 0; 1748 uint32_t m_segStreamInWidth = 0; 1749 double m_inputBitsPerFrame = 0.0; 1750 double m_curTargetFullness = 0.0; 1751 uint16_t m_slbbImgStateOffset = 0; 1752 uint32_t m_defaultPictureStatesSize = 0; 1753 uint32_t m_defaultPicturePatchListSize = 0; 1754 uint32_t m_defaultHucCmdsSize = 0; 1755 uint32_t m_defaultHucPatchListSize = 0; 1756 1757 MOS_RESOURCE m_resVdencIntraRowStoreScratchBuffer; // Handle of intra row store surface 1758 MOS_RESOURCE m_resVdencBrcStatsBuffer; 1759 MOS_RESOURCE m_resVdencSegmentMapStreamOut; 1760 MOS_RESOURCE m_resVdencPictureState2NdLevelBatchBufferRead[3][CODECHAL_VP9_ENCODE_RECYCLED_BUFFER_NUM]; 1761 MOS_RESOURCE m_resVdencPictureState2NdLevelBatchBufferWrite[CODECHAL_VP9_ENCODE_RECYCLED_BUFFER_NUM]; 1762 uint16_t m_vdencPictureState2ndLevelBBIndex = 0; 1763 MOS_RESOURCE m_resVdencDysPictureState2NdLevelBatchBuffer; 1764 MOS_RESOURCE m_resVdencBrcInitDmemBuffer; 1765 MOS_RESOURCE m_resVdencBrcUpdateDmemBuffer[3][CODECHAL_VP9_ENCODE_RECYCLED_BUFFER_NUM]; 1766 MOS_RESOURCE m_resVdencDataExtensionBuffer; 1767 CODECHAL_ENCODE_BUFFER m_resPakcuLevelStreamoutData; 1768 CODECHAL_ENCODE_BUFFER m_resPakSliceLevelStreamutData; 1769 1770 uint32_t m_maxTileNumber = 1; 1771 1772 uint32_t m_bitDepth = 0; 1773 uint8_t m_chromaFormat = 0; 1774 uint32_t m_sizeOfSseSrcPixelRowStoreBufferPerLcu = 0; 1775 PCODECHAL_CMD_INITIALIZER m_hucCmdInitializer = nullptr; 1776 1777 bool m_initBrcConstantDataBuffer = false; 1778 1779 protected: 1780 //! 1781 //! \brief Constructor 1782 //! 1783 CodechalVdencVp9State(CodechalHwInterface* hwInterface, 1784 CodechalDebugInterface* debugInterface, 1785 PCODECHAL_STANDARD_INFO standardInfo); 1786 1787 //! 1788 //! \brief Set pipe buffer address parameter 1789 //! \details Set pipe buffer address parameter in MMC case 1790 //! 1791 //! \param [in,out] pipeBufAddrParams 1792 //! Pointer to PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS 1793 //! \param [in] refSurface 1794 //! Pointer to reference surfaces 1795 //! \param [in] cmdBuffer 1796 //! Pointer to MOS command buffer 1797 //! 1798 //! \return MOS_STATUS 1799 //! MOS_STATUS_SUCCESS if success, else fail reason 1800 //! 1801 virtual MOS_STATUS SetPipeBufAddr( 1802 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams, 1803 PMOS_SURFACE refSurface[3], 1804 PMOS_COMMAND_BUFFER cmdBuffer); 1805 1806 public: 1807 //! 1808 //! \brief Destructor 1809 //! ~CodechalVdencVp9State()1810 virtual ~CodechalVdencVp9State() {}; 1811 GetCurrentPass()1812 virtual int GetCurrentPass() 1813 { 1814 return m_currPass; 1815 } 1816 GetNumPasses()1817 virtual int GetNumPasses() 1818 { 1819 return m_numPasses; 1820 } 1821 IsFirstPass()1822 virtual bool IsFirstPass() 1823 { 1824 return (m_currPass == 0) ? true : false; 1825 } 1826 IsLastPass()1827 virtual bool IsLastPass() 1828 { 1829 return (m_currPass == m_numPasses) ? true : false; 1830 } 1831 1832 //! 1833 //! \brief Perform platform capability check 1834 //! 1835 //! \return MOS_STATUS 1836 //! MOS_STATUS_SUCCESS if success, else fail reason 1837 //! PlatformCapabilityCheck()1838 virtual MOS_STATUS PlatformCapabilityCheck() 1839 { 1840 return MOS_STATUS_SUCCESS; 1841 } 1842 1843 virtual MOS_STATUS SetupSegmentationStreamIn() = 0; 1844 1845 virtual void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams); 1846 1847 virtual void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams); 1848 1849 virtual MOS_STATUS InitializePicture(const EncoderParams& params); 1850 1851 virtual MOS_STATUS AllocateResources(); 1852 1853 virtual void FreeResources(); 1854 1855 virtual MOS_STATUS Initialize(CodechalSetting * settings); 1856 1857 //! 1858 //! \brief Execute kernel functions 1859 //! 1860 //! \return MOS_STATUS 1861 //! MOS_STATUS_SUCCESS if success, else fail reason 1862 //! 1863 MOS_STATUS ExecuteKernelFunctions() = 0; 1864 1865 //! 1866 //! \brief Execute slice level 1867 //! 1868 //! \return MOS_STATUS 1869 //! MOS_STATUS_SUCCESS if success, else fail reason 1870 //! 1871 MOS_STATUS ExecuteSliceLevel(); 1872 1873 virtual MOS_STATUS ExecuteDysSliceLevel(); 1874 1875 virtual MOS_STATUS HuCVp9Prob(); 1876 1877 virtual MOS_STATUS HuCBrcUpdate(); 1878 1879 virtual MOS_STATUS HuCBrcInitReset(); 1880 1881 virtual MOS_STATUS ExecutePictureLevel(); 1882 1883 virtual MOS_STATUS ExecuteDysPictureLevel(); 1884 1885 virtual MOS_STATUS SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams, 1886 PMOS_SURFACE* refSurface, 1887 PMOS_SURFACE* refSurfaceNonScaled, 1888 PMOS_SURFACE* dsRefSurface4x, 1889 PMOS_SURFACE* dsRefSurface8x); 1890 1891 virtual MOS_STATUS SetSequenceStructs(); 1892 1893 virtual MOS_STATUS SetPictureStructs(); 1894 1895 virtual MOS_STATUS SetRowstoreCachingOffsets(); 1896 1897 //! 1898 //! \brief User feature key report 1899 //! 1900 //! \return MOS_STATUS 1901 //! MOS_STATUS_SUCCESS if success, else fail reason 1902 //! 1903 MOS_STATUS UserFeatureKeyReport(); 1904 1905 //! 1906 //! \brief Read Hcp status 1907 //! 1908 //! \param [in] cmdBuffer 1909 //! Pointer to command buffer 1910 //! 1911 //! \return MOS_STATUS 1912 //! MOS_STATUS_SUCCESS if success, else fail reason 1913 //! 1914 MOS_STATUS ReadHcpStatus( 1915 PMOS_COMMAND_BUFFER cmdBuffer); 1916 1917 virtual MOS_STATUS ConstructPicStateBatchBuf( 1918 PMOS_RESOURCE picStateBuffer); 1919 1920 //! 1921 //! \brief Construct super frame 1922 //! 1923 //! \return MOS_STATUS 1924 //! MOS_STATUS_SUCCESS if success, else fail reason 1925 //! 1926 MOS_STATUS ConstructSuperFrame(); 1927 1928 //! 1929 //! \brief Set dmem HuC Vp9 Prob 1930 //! 1931 //! \return MOS_STATUS 1932 //! MOS_STATUS_SUCCESS if success, else fail reason 1933 //! 1934 virtual MOS_STATUS SetDmemHuCVp9Prob(); 1935 1936 //! 1937 //! \brief Store HuC status to register 1938 //! 1939 //! \return MOS_STATUS 1940 //! MOS_STATUS_SUCCESS if success, else fail reason 1941 //! 1942 MOS_STATUS StoreHuCStatus2Register(PMOS_COMMAND_BUFFER cmdBuffer); 1943 1944 //! 1945 //! \brief Add store HUC_ERROR_STATUS register command in the command buffer 1946 //! 1947 //! \param [in] mmioRegisters 1948 //! Pointer to mmio huc register 1949 //! \param [in] cmdBuffer 1950 //! Pointer to the command buffer 1951 //! \param [in] addToEnncodeStatus 1952 //! Flag to indicate whether huc error status will be stored in encode status buffer 1953 //! 1954 //! \return MOS_STATUS 1955 //! MOS_STATUS_SUCCESS if success, else fail reason 1956 //! 1957 MOS_STATUS StoreHucErrorStatus(MmioRegistersHuc *mmioRegisters, PMOS_COMMAND_BUFFER cmdBuffer, bool addToEnncodeStatus); 1958 1959 //! 1960 //! \brief Init brc constant buffer 1961 //! 1962 //! \param [in] brcConstResource 1963 //! Pointer to MOS resource 1964 //! \param [in] pictureCodingType 1965 //! Picture coding type 1966 //! 1967 //! \return MOS_STATUS 1968 //! MOS_STATUS_SUCCESS if success, else fail reason 1969 //! 1970 MOS_STATUS InitBrcConstantBuffer( 1971 PMOS_RESOURCE brcConstResource, 1972 uint16_t pictureCodingType); 1973 1974 PMOS_RESOURCE GetBrcConstantBuffer( 1975 PMOS_RESOURCE brcConstResource, 1976 uint16_t pictureCodingType); 1977 1978 //! 1979 //! \brief Compute VD Encode BRC initQP 1980 //! 1981 //! \param [in] initQpI 1982 //! Init QPI 1983 //! \param [in] initQpP 1984 //! Init QPP 1985 //! 1986 //! \return MOS_STATUS 1987 //! MOS_STATUS_SUCCESS if success, else fail reason 1988 //! 1989 MOS_STATUS ComputeVDEncBRCInitQP( 1990 int32_t* initQpI, 1991 int32_t* initQpP); 1992 1993 //! 1994 //! \brief Set dmem huc brc update 1995 //! 1996 //! \return MOS_STATUS 1997 //! MOS_STATUS_SUCCESS if success, else fail reason 1998 //! 1999 MOS_STATUS SetDmemHuCBrcUpdate(); 2000 2001 //! 2002 //! \brief Set dmem huc brc init reset 2003 //! 2004 //! \return MOS_STATUS 2005 //! MOS_STATUS_SUCCESS if success, else fail reason 2006 //! 2007 MOS_STATUS SetDmemHuCBrcInitReset(); 2008 2009 //! 2010 //! \brief Software BRC 2011 //! 2012 //! \param [in] update 2013 //! Update status 2014 //! 2015 //! \return MOS_STATUS 2016 //! MOS_STATUS_SUCCESS if success, else fail reason 2017 //! 2018 MOS_STATUS SoftwareBRC(bool update); 2019 2020 //! 2021 //! \brief 2022 //! 2023 //! \param [in] idx 2024 //! Index 2025 //! \param [in] width 2026 //! Width 2027 //! \param [in] blockSize 2028 //! Block size 2029 //! \param [in] bufferPitch 2030 //! Buffer pitch 2031 //! 2032 //! \return uint32_t 2033 //! Return 0if call success, else -1 if fail 2034 //! 2035 uint32_t CalculateBufferOffset( 2036 uint32_t idx, 2037 uint32_t width, 2038 uint32_t blockSize, 2039 uint32_t bufferPitch); 2040 2041 //! 2042 //! \brief Pak construct picture state batch buffer 2043 //! 2044 //! \param [in] picStateBuffer 2045 //! Pointer to MOS surface 2046 //! 2047 //! \return MOS_STATUS 2048 //! MOS_STATUS_SUCCESS if success, else fail reason 2049 //! 2050 MOS_STATUS PakConstructPicStateBatchBuf( 2051 PMOS_RESOURCE picStateBuffer); 2052 2053 //! 2054 //! \brief Return if this surface has to be compressed 2055 //! 2056 //! \param [in] isDownScaledSurface 2057 //! indicating if surface is downscaled 2058 //! 2059 //! \return int32_t 2060 //! 1 if to be compressed 2061 //! 0 if not 2062 //! 2063 virtual bool IsToBeCompressed(bool isDownScaledSurface); 2064 2065 //! 2066 //! \brief Dys Reference frames 2067 //! 2068 //! \return MOS_STATUS 2069 //! MOS_STATUS_SUCCESS if success, else fail reason 2070 //! 2071 MOS_STATUS DysRefFrames(); 2072 2073 //! 2074 //! \brief Set sampler state Dys 2075 //! 2076 //! \param [in] params 2077 //! Pointer to Dys sampler state parameters 2078 //! 2079 //! \return MOS_STATUS 2080 //! MOS_STATUS_SUCCESS if success, else fail reason 2081 //! 2082 MOS_STATUS SetSamplerStateDys( 2083 DysSamplerStateParams* params); 2084 2085 //! 2086 //! \brief Set curbe Dys 2087 //! 2088 //! \param [in] params 2089 //! Pointer to Dys curbe parameters 2090 //! 2091 //! \return MOS_STATUS 2092 //! MOS_STATUS_SUCCESS if success, else fail reason 2093 //! 2094 MOS_STATUS SetCurbeDys( 2095 DysCurbeParams* params); 2096 2097 //! 2098 //! \brief Send Dys surfaces 2099 //! 2100 //! \param [in] cmdBuffer 2101 //! Pointer to MOS command buffer 2102 //! \param [in] params 2103 //! Pointer to Dys surface parameters 2104 //! 2105 //! \return MOS_STATUS 2106 //! MOS_STATUS_SUCCESS if success, else fail reason 2107 //! 2108 MOS_STATUS SendDysSurfaces( 2109 PMOS_COMMAND_BUFFER cmdBuffer, 2110 DysSurfaceParams* params); 2111 2112 //! 2113 //! \brief Dys kernel 2114 //! 2115 //! \param [in] dysKernelParams 2116 //! Pointer to Dys kernel parameters 2117 //! 2118 //! \return MOS_STATUS 2119 //! MOS_STATUS_SUCCESS if success, else fail reason 2120 //! 2121 virtual MOS_STATUS DysKernel( 2122 DysKernelParams* dysKernelParams); 2123 2124 //! 2125 //! \brief Initalize ME state 2126 //! 2127 //! \param [in] state 2128 //! Pointer to Vdenc vme state 2129 //! 2130 //! \return MOS_STATUS 2131 //! MOS_STATUS_SUCCESS if success, else fail reason 2132 //! 2133 MOS_STATUS InitMEState(VdencVmeState* state); 2134 2135 //! 2136 //! \brief Vdenc set curbe hme kernel 2137 //! 2138 //! \param [in] state 2139 //! Pointer to Vdenc vme state 2140 //! 2141 //! \return MOS_STATUS 2142 //! MOS_STATUS_SUCCESS if success, else fail reason 2143 //! 2144 MOS_STATUS VdencSetCurbeHmeKernel( 2145 VdencVmeState* state); 2146 2147 //! 2148 //! \brief Sets the SurfaceStates for 16xMe and 4xME 2149 //! \details Sets the Input and Output SurfaceStates for respective BTI for 2150 //! 16xMe and 4xME using the parameters from the input kernel state. 2151 //! 2152 //! \param state 2153 //! [in] Parameters used for setting up the CURBE 2154 //! \param cmdBuffer 2155 //! [in] Command buffer 2156 //! 2157 //! \return MOS_STATUS 2158 //! MOS_STATUS_SUCCESS if success, else fail reason 2159 //! 2160 MOS_STATUS VdencSendHmeSurfaces( 2161 VdencVmeState* state, 2162 PMOS_COMMAND_BUFFER cmdBuffer); 2163 2164 //! 2165 //! \brief Vdenc hme kernel 2166 //! 2167 //! \param [in] state 2168 //! Pointer to Vdenc vme state 2169 //! 2170 //! \return MOS_STATUS 2171 //! MOS_STATUS_SUCCESS if success, else fail reason 2172 //! 2173 MOS_STATUS VdencHmeKernel( 2174 VdencVmeState* state); 2175 2176 virtual PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS CreateHcpPipeBufAddrParams(PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams); 2177 2178 //! 2179 //! \brief Set hcp ds surface params 2180 //! 2181 //! \param [in] dsSurfaceParams 2182 //! Pointer to MHW vdbox surface parameters 2183 //! 2184 //! \return MOS_STATUS 2185 //! MOS_STATUS_SUCCESS if success, else fail reason 2186 //! 2187 void SetHcpDsSurfaceParams(MHW_VDBOX_SURFACE_PARAMS* dsSurfaceParams); 2188 2189 //! 2190 //! \brief Resize 4x and 8x DS recon Surfaces to VDEnc 2191 //! 2192 //! \param [in] bufIdx 2193 //! Index of the surface 2194 //! 2195 //! \return MOS_STATUS 2196 //! MOS_STATUS_SUCCESS if success, else fail reason 2197 //! 2198 MOS_STATUS Resize4x8xforDS( 2199 uint8_t bufIdx); 2200 2201 //! 2202 //! \brief Set hcp source surface parameters 2203 //! 2204 //! \param [in] surfaceParams 2205 //! Pointer to MHW vdbox surface parameters 2206 //! \param [in] refSurface 2207 //! Pointer to MOS surface 2208 //! \param [in] refSurfaceNonScaled 2209 //! Pointer to MOS surface 2210 //! \param [in] dsRefSurface4x 2211 //! Pointer to MOS surface 2212 //! \param [in] dsRefSurface8x 2213 //! Pointer to MOS surface 2214 //! 2215 //! \return MOS_STATUS 2216 //! MOS_STATUS_SUCCESS if success, else fail reason 2217 //! 2218 2219 MOS_STATUS SetHcpSrcSurfaceParams(MHW_VDBOX_SURFACE_PARAMS* surfaceParams, 2220 PMOS_SURFACE* refSurface, 2221 PMOS_SURFACE* refSurfaceNonScaled, 2222 PMOS_SURFACE* dsRefSurface4x, 2223 PMOS_SURFACE* dsRefSurface8x); 2224 2225 virtual MOS_STATUS GetStatusReport( 2226 EncodeStatus* encodeStatus, 2227 EncodeStatusReport* encodeStatusReport); 2228 2229 //! 2230 //! \brief Get reference buffer slot index 2231 //! 2232 //! \param [in] refreshFlags 2233 //! Refresh flags 2234 //! 2235 //! \return uint8_t 2236 //! Return 0 if call success, else -1 if fail 2237 //! 2238 uint8_t GetReferenceBufferSlotIndex(uint8_t refreshFlags); 2239 2240 //! 2241 //! \brief Put data for compressed header 2242 //! 2243 //! \param [in] compressedHdr 2244 //! Compressed header 2245 //! \param [in] bit 2246 //! Bit 2247 //! \param [in] prob 2248 //! Prob 2249 //! \param [in] binIdx 2250 //! Bin index 2251 //! 2252 void PutDataForCompressedHdr( 2253 CompressedHeader* compressedHdr, 2254 uint32_t bit, 2255 uint32_t prob, 2256 uint32_t binIdx); 2257 2258 //! 2259 //! \brief Allocate resources brc 2260 //! 2261 //! \return MOS_STATUS 2262 //! MOS_STATUS_SUCCESS if success, else fail reason 2263 //! 2264 MOS_STATUS AllocateResourcesBrc(); 2265 2266 //! 2267 //! \brief Release resources brc 2268 //! 2269 void ReleaseResourcesBrc(); 2270 2271 //! 2272 //! \brief Calculate temporal ratios 2273 //! 2274 //! \param [in] numberOfLayers 2275 //! Number of layers 2276 //! \param [in] maxTemporalBitrate 2277 //! Max temporal frame rate 2278 //! \param [in] maxTemporalFrameRate 2279 //! Frame rate 2280 //! \param [in] maxLevelRatios 2281 //! Max level ratios 2282 //! 2283 //! \return MOS_STATUS 2284 //! MOS_STATUS_SUCCESS if success, else fail reason 2285 //! 2286 MOS_STATUS CalculateTemporalRatios( 2287 uint16_t numberOfLayers, 2288 uint32_t maxTemporalBitrate, 2289 FRAME_RATE maxTemporalFrameRate, 2290 uint8_t* maxLevelRatios); 2291 2292 //! 2293 //! \brief Calculate normalized denominator 2294 //! 2295 //! \param [in] frameRates 2296 //! Pointer to frame rate 2297 //! \param [in] numberOfLayers 2298 //! Number of layers 2299 //! \param [in] normalizedDenominator 2300 //! Normalized denominator 2301 //! 2302 //! \return uint32_t 2303 //! Return 0 if call success, else -1 if fail 2304 //! 2305 uint32_t CalculateNormalizedDenominator( 2306 FRAME_RATE* frameRates, 2307 uint16_t numberOfLayers, 2308 uint32_t normalizedDenominator); 2309 2310 //! 2311 //! \brief Calculate rePak thresholds 2312 //! \details 2313 //! 2314 //! \return MOS_STATUS 2315 //! MOS_STATUS_SUCCESS if success, else fail reason 2316 //! 2317 MOS_STATUS CalculateRePakThresholds(); 2318 2319 //! 2320 //! \brief Construct Pak insert object batch buf 2321 //! \details 2322 //! 2323 //! \param [in] pakInsertObjBuffer 2324 //! Pointer to MOS resource 2325 //! 2326 //! \return MOS_STATUS 2327 //! MOS_STATUS_SUCCESS if success, else fail reason 2328 //! 2329 MOS_STATUS ConstructPakInsertObjBatchBuf( 2330 PMOS_RESOURCE pakInsertObjBuffer); 2331 2332 //! 2333 //! \brief Refresh frame internal buffers 2334 //! \details 2335 //! 2336 //! \return MOS_STATUS 2337 //! MOS_STATUS_SUCCESS if success, else fail reason 2338 //! 2339 MOS_STATUS RefreshFrameInternalBuffers(); 2340 2341 //! 2342 //! \brief Allocate Mb brc segment map surface 2343 //! \details 2344 //! 2345 //! \return MOS_STATUS 2346 //! MOS_STATUS_SUCCESS if success, else fail reason 2347 //! 2348 MOS_STATUS AllocateMbBrcSegMapSurface(); 2349 2350 //! 2351 //! \brief Init context buffer 2352 //! \details 2353 //! \param [in,out] ctxBuffer 2354 //! Pointer to context buffer 2355 //! 2356 //! \param [in] setToKey 2357 //! Specify if it's key frame 2358 //! 2359 //! \return MOS_STATUS 2360 //! MOS_STATUS_SUCCESS if success, else fail reason 2361 //! 2362 MOS_STATUS ContextBufferInit( 2363 uint8_t *ctxBuffer, 2364 bool setToKey); 2365 2366 //! 2367 //! \brief Populate prob values which are different between Key and Non-Key frame 2368 //! \details 2369 //! \param [in,out] ctxBuffer 2370 //! Pointer to context buffer 2371 //! 2372 //! \param [in] setToKey 2373 //! Specify if it's key frame 2374 //! 2375 //! \return MOS_STATUS 2376 //! MOS_STATUS_SUCCESS if success, else fail reason 2377 //! 2378 MOS_STATUS CtxBufDiffInit( 2379 uint8_t *ctxBuffer, 2380 bool setToKey); 2381 2382 //! 2383 //! \brief Calculate Vdenc Picture State CommandSize 2384 //! 2385 //! \return MOS_STATUS 2386 //! MOS_STATUS_SUCCESS if success 2387 //! 2388 virtual MOS_STATUS CalculateVdencPictureStateCommandSize(); 2389 2390 //! 2391 //! \brief Initialize MMC state 2392 //! 2393 //! \return MOS_STATUS 2394 //! MOS_STATUS_SUCCESS if success 2395 //! 2396 virtual MOS_STATUS InitMmcState(); 2397 2398 virtual MOS_STATUS VerifyCommandBufferSize(); 2399 2400 virtual MOS_STATUS GetCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 2401 2402 virtual MOS_STATUS ReturnCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 2403 2404 virtual MOS_STATUS SubmitCommandBuffer( 2405 PMOS_COMMAND_BUFFER cmdBuffer, 2406 bool bNullRendering); 2407 2408 #if USE_CODECHAL_DEBUG_TOOL 2409 MOS_STATUS DumpSegmentParams( 2410 PCODEC_VP9_ENCODE_SEGMENT_PARAMS segmentParams); 2411 2412 MOS_STATUS DumpSeqParams( 2413 PCODEC_VP9_ENCODE_SEQUENCE_PARAMS seqParams); 2414 2415 MOS_STATUS DumpPicParams( 2416 PCODEC_VP9_ENCODE_PIC_PARAMS picParams); 2417 #endif 2418 2419 void fill_pad_with_value(PMOS_SURFACE psSurface, uint32_t real_height, uint32_t aligned_height); 2420 }; 2421 2422 #endif // __CODECHAL_VDENC_VP9_BASE_H__ 2423 2424