1 /* 2 * Copyright (c) 2017-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 //! 24 //! \file codechal_vdenc_vp9_g12.h 25 //! \brief VP9 VDENC encoder for GEN12 platform. 26 //! 27 28 #ifndef __CODECHAL_VDENC_VP9_G12_H__ 29 #define __CODECHAL_VDENC_VP9_G12_H__ 30 31 #include "codechal.h" 32 #include "codechal_hw.h" 33 #include "codechal_vdenc_vp9_base.h" 34 #include "mhw_vdbox_g12_X.h" 35 #include "codechal_encode_singlepipe_virtualengine.h" 36 #include "codechal_encode_scalability.h" 37 38 #define HUC_CMD_LIST_MODE 1 39 #define HUC_BATCH_BUFFER_END 0x05000000 40 #define VDBOX_HUC_PAK_INTEGRATION_KERNEL_DESCRIPTOR 15 41 42 class CodechalVdencVp9StateG12 : public CodechalVdencVp9State 43 { 44 public: 45 enum MeBindingTableOffset 46 { 47 48 CODECHAL_ENCODE_ME_MV_DATA_SURFACE_G12 = 0, 49 CODECHAL_ENCODE_16xME_MV_DATA_SURFACE_G12 = 1, 50 CODECHAL_ENCODE_32xME_MV_DATA_SURFACE_G12 = 1, 51 CODECHAL_ENCODE_ME_DISTORTION_SURFACE_G12 = 2, 52 CODECHAL_ENCODE_ME_BRC_DISTORTION_G12 = 3, 53 CODECHAL_ENCODE_ME_RESERVED0_G12 = 4, 54 CODECHAL_ENCODE_ME_CURR_FOR_FWD_REF_G12 = 5, 55 CODECHAL_ENCODE_ME_FWD_REF_IDX0_G12 = 6, 56 CODECHAL_ENCODE_ME_RESERVED1_G12 = 7, 57 CODECHAL_ENCODE_ME_FWD_REF_IDX1_G12 = 8, 58 CODECHAL_ENCODE_ME_RESERVED2_G12 = 9, 59 CODECHAL_ENCODE_ME_FWD_REF_IDX2_G12 = 10, 60 CODECHAL_ENCODE_ME_RESERVED3_G12 = 11, 61 CODECHAL_ENCODE_ME_FWD_REF_IDX3_G12 = 12, 62 CODECHAL_ENCODE_ME_RESERVED4_G12 = 13, 63 CODECHAL_ENCODE_ME_FWD_REF_IDX4_G12 = 14, 64 CODECHAL_ENCODE_ME_RESERVED5_G12 = 15, 65 CODECHAL_ENCODE_ME_FWD_REF_IDX5_G12 = 16, 66 CODECHAL_ENCODE_ME_RESERVED6_G12 = 17, 67 CODECHAL_ENCODE_ME_FWD_REF_IDX6_G12 = 18, 68 CODECHAL_ENCODE_ME_RESERVED7_G12 = 19, 69 CODECHAL_ENCODE_ME_FWD_REF_IDX7_G12 = 20, 70 CODECHAL_ENCODE_ME_RESERVED8_G12 = 21, 71 CODECHAL_ENCODE_ME_CURR_FOR_BWD_REF_G12 = 22, 72 CODECHAL_ENCODE_ME_BWD_REF_IDX0_G12 = 23, 73 CODECHAL_ENCODE_ME_RESERVED9_G12 = 24, 74 CODECHAL_ENCODE_ME_BWD_REF_IDX1_G12 = 25, 75 CODECHAL_ENCODE_ME_VDENC_STREAMIN_OUTPUT_G12 = 26, 76 CODECHAL_ENCODE_ME_VDENC_STREAMIN_INPUT_G12 = 27, 77 CODECHAL_ENCODE_ME_NUM_SURFACES_G12 = 28 78 }; 79 80 struct MeCurbe 81 { 82 // DW0 83 union 84 { 85 struct 86 { 87 uint32_t SkipModeEn : MOS_BITFIELD_BIT ( 0); 88 uint32_t AdaptiveEn : MOS_BITFIELD_BIT ( 1); 89 uint32_t BiMixDis : MOS_BITFIELD_BIT ( 2); 90 uint32_t : MOS_BITFIELD_RANGE( 3, 4); 91 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT ( 5); 92 uint32_t : MOS_BITFIELD_BIT ( 6); 93 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT ( 7); 94 uint32_t : MOS_BITFIELD_RANGE( 8, 23); 95 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE(24, 31); 96 }; 97 struct 98 { 99 uint32_t Value; 100 }; 101 } DW0; 102 103 // DW1 104 union 105 { 106 struct 107 { 108 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE( 0, 5); 109 uint32_t : MOS_BITFIELD_RANGE( 6, 15); 110 uint32_t BiWeight : MOS_BITFIELD_RANGE(16, 21); 111 uint32_t : MOS_BITFIELD_RANGE(22, 27); 112 uint32_t UniMixDisable : MOS_BITFIELD_BIT ( 28); 113 uint32_t : MOS_BITFIELD_RANGE(29, 31); 114 }; 115 struct 116 { 117 uint32_t Value; 118 }; 119 } DW1; 120 121 // DW2 122 union 123 { 124 struct 125 { 126 uint32_t MaxLenSP : MOS_BITFIELD_RANGE( 0, 7); 127 uint32_t MaxNumSU : MOS_BITFIELD_RANGE( 8, 15); 128 uint32_t : MOS_BITFIELD_RANGE(16, 31); 129 }; 130 struct 131 { 132 uint32_t Value; 133 }; 134 } DW2; 135 136 // DW3 137 union 138 { 139 struct 140 { 141 uint32_t SrcSize : MOS_BITFIELD_RANGE( 0, 1); 142 uint32_t : MOS_BITFIELD_RANGE( 2, 3); 143 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE( 4, 5); 144 uint32_t SrcAccess : MOS_BITFIELD_BIT ( 6); 145 uint32_t RefAccess : MOS_BITFIELD_BIT ( 7); 146 uint32_t SearchCtrl : MOS_BITFIELD_RANGE( 8, 10); 147 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT ( 11); 148 uint32_t SubPelMode : MOS_BITFIELD_RANGE(12, 13); 149 uint32_t SkipType : MOS_BITFIELD_BIT ( 14); 150 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT ( 15); 151 uint32_t InterChromaMode : MOS_BITFIELD_BIT ( 16); 152 uint32_t FTEnable : MOS_BITFIELD_BIT ( 17); 153 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT ( 18); 154 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT ( 19); 155 uint32_t InterSAD : MOS_BITFIELD_RANGE(20, 21); 156 uint32_t IntraSAD : MOS_BITFIELD_RANGE(22, 23); 157 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE(24, 30); 158 uint32_t : MOS_BITFIELD_BIT ( 31); 159 }; 160 struct 161 { 162 uint32_t Value; 163 }; 164 } DW3; 165 166 // DW4 167 union 168 { 169 struct 170 { 171 uint32_t : MOS_BITFIELD_RANGE( 0, 7); 172 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE( 8, 15); 173 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 174 uint32_t : MOS_BITFIELD_RANGE(24, 31); 175 }; 176 struct 177 { 178 uint32_t Value; 179 }; 180 } DW4; 181 182 // DW5 183 union 184 { 185 struct 186 { 187 uint32_t : MOS_BITFIELD_RANGE( 0, 7); 188 uint32_t QpPrimeY : MOS_BITFIELD_RANGE( 8, 15); 189 uint32_t RefWidth : MOS_BITFIELD_RANGE(16, 23); 190 uint32_t RefHeight : MOS_BITFIELD_RANGE(24, 31); 191 }; 192 struct 193 { 194 uint32_t Value; 195 }; 196 } DW5; 197 198 // DW6 199 union 200 { 201 struct 202 { 203 uint32_t : MOS_BITFIELD_BIT ( 0); 204 uint32_t InputStreamInSurfaceEnable : MOS_BITFIELD_BIT ( 1); 205 uint32_t LCUSize : MOS_BITFIELD_BIT ( 2); 206 uint32_t WriteDistortions : MOS_BITFIELD_BIT ( 3); 207 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT ( 4); 208 uint32_t : MOS_BITFIELD_RANGE( 5, 7); 209 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE( 8, 15); 210 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 211 }; 212 struct 213 { 214 uint32_t Value; 215 }; 216 } DW6; 217 218 // DW7 219 union 220 { 221 struct 222 { 223 uint32_t : MOS_BITFIELD_RANGE( 0, 15); 224 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE(16, 17); 225 uint32_t BilinearEnable : MOS_BITFIELD_BIT ( 18); 226 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT ( 19); 227 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT ( 20); 228 uint32_t AConlyHAAR : MOS_BITFIELD_BIT ( 21); 229 uint32_t RefIDCostMode : MOS_BITFIELD_BIT ( 22); 230 uint32_t : MOS_BITFIELD_BIT ( 23); 231 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE(24, 31); 232 }; 233 struct 234 { 235 uint32_t Value; 236 }; 237 } DW7; 238 239 // DW8 240 union 241 { 242 struct 243 { 244 uint32_t Mode0Cost : MOS_BITFIELD_RANGE( 0, 7); 245 uint32_t Mode1Cost : MOS_BITFIELD_RANGE( 8, 15); 246 uint32_t Mode2Cost : MOS_BITFIELD_RANGE(16, 23); 247 uint32_t Mode3Cost : MOS_BITFIELD_RANGE(24, 31); 248 }; 249 struct 250 { 251 uint32_t Value; 252 }; 253 } DW8; 254 255 // DW9 256 union 257 { 258 struct 259 { 260 uint32_t Mode4Cost : MOS_BITFIELD_RANGE( 0, 7); 261 uint32_t Mode5Cost : MOS_BITFIELD_RANGE( 8, 15); 262 uint32_t Mode6Cost : MOS_BITFIELD_RANGE(16, 23); 263 uint32_t Mode7Cost : MOS_BITFIELD_RANGE(24, 31); 264 }; 265 struct 266 { 267 uint32_t Value; 268 }; 269 } DW9; 270 271 // DW10 272 union 273 { 274 struct 275 { 276 uint32_t Mode8Cost : MOS_BITFIELD_RANGE( 0, 7); 277 uint32_t Mode9Cost : MOS_BITFIELD_RANGE( 8, 15); 278 uint32_t RefIDCost : MOS_BITFIELD_RANGE(16, 23); 279 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE(24, 31); 280 }; 281 struct 282 { 283 uint32_t Value; 284 }; 285 } DW10; 286 287 // DW11 288 union 289 { 290 struct 291 { 292 uint32_t MV0Cost : MOS_BITFIELD_RANGE( 0, 7); 293 uint32_t MV1Cost : MOS_BITFIELD_RANGE( 8, 15); 294 uint32_t MV2Cost : MOS_BITFIELD_RANGE(16, 23); 295 uint32_t MV3Cost : MOS_BITFIELD_RANGE(24, 31); 296 }; 297 struct 298 { 299 uint32_t Value; 300 }; 301 } DW11; 302 303 // DW12 304 union 305 { 306 struct 307 { 308 uint32_t MV4Cost : MOS_BITFIELD_RANGE( 0, 7); 309 uint32_t MV5Cost : MOS_BITFIELD_RANGE( 8, 15); 310 uint32_t MV6Cost : MOS_BITFIELD_RANGE(16, 23); 311 uint32_t MV7Cost : MOS_BITFIELD_RANGE(24, 31); 312 }; 313 struct 314 { 315 uint32_t Value; 316 }; 317 } DW12; 318 319 // DW13 320 union 321 { 322 struct 323 { 324 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE( 0, 7); 325 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE( 8, 15); 326 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 327 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 328 uint32_t : MOS_BITFIELD_RANGE(27, 31); 329 }; 330 struct 331 { 332 uint32_t Value; 333 }; 334 } DW13; 335 336 // DW14 337 union 338 { 339 struct 340 { 341 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT ( 0); 342 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT ( 1); 343 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT ( 2); 344 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT ( 3); 345 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT ( 4); 346 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT ( 5); 347 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT ( 6); 348 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT ( 7); 349 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT ( 8); 350 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT ( 9); 351 uint32_t : MOS_BITFIELD_RANGE(10, 31); 352 }; 353 struct 354 { 355 uint32_t Value; 356 }; 357 } DW14; 358 359 // DW15 360 union 361 { 362 struct 363 { 364 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE( 0, 7); 365 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE( 8, 15); 366 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 367 }; 368 struct 369 { 370 uint32_t Value; 371 }; 372 } DW15; 373 374 struct 375 { 376 // DW16 377 union 378 { 379 struct 380 { 381 SearchPathDelta SPDelta_0; 382 SearchPathDelta SPDelta_1; 383 SearchPathDelta SPDelta_2; 384 SearchPathDelta SPDelta_3; 385 }; 386 struct 387 { 388 uint32_t Value; 389 }; 390 } DW16; 391 392 // DW17 393 union 394 { 395 struct 396 { 397 SearchPathDelta SPDelta_4; 398 SearchPathDelta SPDelta_5; 399 SearchPathDelta SPDelta_6; 400 SearchPathDelta SPDelta_7; 401 }; 402 struct 403 { 404 uint32_t Value; 405 }; 406 } DW17; 407 408 // DW18 409 union 410 { 411 struct 412 { 413 SearchPathDelta SPDelta_8; 414 SearchPathDelta SPDelta_9; 415 SearchPathDelta SPDelta_10; 416 SearchPathDelta SPDelta_11; 417 }; 418 struct 419 { 420 uint32_t Value; 421 }; 422 } DW18; 423 424 // DW19 425 union 426 { 427 struct 428 { 429 SearchPathDelta SPDelta_12; 430 SearchPathDelta SPDelta_13; 431 SearchPathDelta SPDelta_14; 432 SearchPathDelta SPDelta_15; 433 }; 434 struct 435 { 436 uint32_t Value; 437 }; 438 } DW19; 439 440 // DW20 441 union 442 { 443 struct 444 { 445 SearchPathDelta SPDelta_16; 446 SearchPathDelta SPDelta_17; 447 SearchPathDelta SPDelta_18; 448 SearchPathDelta SPDelta_19; 449 }; 450 struct 451 { 452 uint32_t Value; 453 }; 454 } DW20; 455 456 // DW21 457 union 458 { 459 struct 460 { 461 SearchPathDelta SPDelta_20; 462 SearchPathDelta SPDelta_21; 463 SearchPathDelta SPDelta_22; 464 SearchPathDelta SPDelta_23; 465 }; 466 struct 467 { 468 uint32_t Value; 469 }; 470 } DW21; 471 472 // DW22 473 union 474 { 475 struct 476 { 477 SearchPathDelta SPDelta_24; 478 SearchPathDelta SPDelta_25; 479 SearchPathDelta SPDelta_26; 480 SearchPathDelta SPDelta_27; 481 }; 482 struct 483 { 484 uint32_t Value; 485 }; 486 } DW22; 487 488 // DW23 489 union 490 { 491 struct 492 { 493 SearchPathDelta SPDelta_28; 494 SearchPathDelta SPDelta_29; 495 SearchPathDelta SPDelta_30; 496 SearchPathDelta SPDelta_31; 497 }; 498 struct 499 { 500 uint32_t Value; 501 }; 502 } DW23; 503 504 // DW24 505 union 506 { 507 struct 508 { 509 SearchPathDelta SPDelta_32; 510 SearchPathDelta SPDelta_33; 511 SearchPathDelta SPDelta_34; 512 SearchPathDelta SPDelta_35; 513 }; 514 struct 515 { 516 uint32_t Value; 517 }; 518 } DW24; 519 520 // DW25 521 union 522 { 523 struct 524 { 525 SearchPathDelta SPDelta_36; 526 SearchPathDelta SPDelta_37; 527 SearchPathDelta SPDelta_38; 528 SearchPathDelta SPDelta_39; 529 }; 530 struct 531 { 532 uint32_t Value; 533 }; 534 } DW25; 535 536 // DW26 537 union 538 { 539 struct 540 { 541 SearchPathDelta SPDelta_40; 542 SearchPathDelta SPDelta_41; 543 SearchPathDelta SPDelta_42; 544 SearchPathDelta SPDelta_43; 545 }; 546 struct 547 { 548 uint32_t Value; 549 }; 550 } DW26; 551 552 // DW27 553 union 554 { 555 struct 556 { 557 SearchPathDelta SPDelta_44; 558 SearchPathDelta SPDelta_45; 559 SearchPathDelta SPDelta_46; 560 SearchPathDelta SPDelta_47; 561 }; 562 struct 563 { 564 uint32_t Value; 565 }; 566 } DW27; 567 568 // DW28 569 union 570 { 571 struct 572 { 573 SearchPathDelta SPDelta_48; 574 SearchPathDelta SPDelta_49; 575 SearchPathDelta SPDelta_50; 576 SearchPathDelta SPDelta_51; 577 }; 578 struct 579 { 580 uint32_t Value; 581 }; 582 } DW28; 583 584 // DW29 585 union 586 { 587 struct 588 { 589 SearchPathDelta SPDelta_52; 590 SearchPathDelta SPDelta_53; 591 SearchPathDelta SPDelta_54; 592 SearchPathDelta SPDelta_55; 593 }; 594 struct 595 { 596 uint32_t Value; 597 }; 598 } DW29; 599 }SPDelta; 600 601 // DW30 602 union 603 { 604 struct 605 { 606 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE( 0, 15); 607 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 608 }; 609 struct 610 { 611 uint32_t Value; 612 }; 613 } DW30; 614 615 // DW31 616 union 617 { 618 struct 619 { 620 uint32_t RoiCtrl : MOS_BITFIELD_RANGE( 0, 7); 621 uint32_t MaxTuSize : MOS_BITFIELD_RANGE( 8, 9); 622 uint32_t MaxCuSize : MOS_BITFIELD_RANGE(10, 11); 623 uint32_t NumImePredictors : MOS_BITFIELD_RANGE(12, 15); 624 uint32_t : MOS_BITFIELD_RANGE(16, 23); 625 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE(24, 31); 626 }; 627 struct 628 { 629 uint32_t Value; 630 }; 631 } DW31; 632 633 // DW32 634 union 635 { 636 struct 637 { 638 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE( 0, 15); 639 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 640 }; 641 struct 642 { 643 uint32_t Value; 644 }; 645 } DW32; 646 647 // DW33 648 union 649 { 650 struct 651 { 652 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE( 0, 15); 653 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 654 }; 655 struct 656 { 657 uint32_t Value; 658 }; 659 } DW33; 660 661 // DW34 662 union 663 { 664 struct 665 { 666 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE( 0, 15); 667 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 668 }; 669 struct 670 { 671 uint32_t Value; 672 }; 673 } DW34; 674 675 // DW35 676 union 677 { 678 struct 679 { 680 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE( 0, 15); 681 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 682 }; 683 struct 684 { 685 uint32_t Value; 686 }; 687 } DW35; 688 689 // DW36 690 union 691 { 692 struct 693 { 694 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE( 0, 3); 695 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE( 4, 7); 696 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE( 8, 11); 697 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 698 uint32_t NumMergeCandidateCu8x8 : MOS_BITFIELD_RANGE(16, 19); 699 uint32_t NumMergeCandidateCu16x16 : MOS_BITFIELD_RANGE(20, 23); 700 uint32_t NumMergeCandidateCu32x32 : MOS_BITFIELD_RANGE(24, 27); 701 uint32_t NumMergeCandidateCu64x64 : MOS_BITFIELD_RANGE(28, 31); 702 }; 703 struct 704 { 705 uint32_t Value; 706 }; 707 } DW36; 708 709 // DW37 710 union 711 { 712 struct 713 { 714 uint32_t SegID : MOS_BITFIELD_RANGE( 0, 15); 715 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 716 uint32_t SegIDEnable : MOS_BITFIELD_BIT ( 20); 717 uint32_t : MOS_BITFIELD_RANGE(21, 22); 718 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT ( 23); 719 uint32_t : MOS_BITFIELD_RANGE(24, 31); 720 }; 721 struct 722 { 723 uint32_t Value; 724 }; 725 } DW37; 726 727 // DW38 728 union 729 { 730 struct 731 { 732 uint32_t ForceQp0 : MOS_BITFIELD_RANGE( 0, 7); 733 uint32_t ForceQp1 : MOS_BITFIELD_RANGE( 8, 15); 734 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 735 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(16, 19); 736 }; 737 struct 738 { 739 uint32_t Value; 740 }; 741 } DW38; 742 743 // DW39 744 union 745 { 746 struct 747 { 748 uint32_t : MOS_BITFIELD_RANGE( 0, 31); 749 }; 750 struct 751 { 752 uint32_t Value; 753 }; 754 } DW39; 755 756 // DW40 757 union 758 { 759 struct 760 { 761 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 762 }; 763 struct 764 { 765 uint32_t Value; 766 }; 767 } DW40; 768 769 // DW41 770 union 771 { 772 struct 773 { 774 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 775 }; 776 struct 777 { 778 uint32_t Value; 779 }; 780 } DW41; 781 782 // DW42 783 union 784 { 785 struct 786 { 787 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 788 }; 789 struct 790 { 791 uint32_t Value; 792 }; 793 } DW42; 794 795 // DW43 796 union 797 { 798 struct 799 { 800 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 801 }; 802 struct 803 { 804 uint32_t Value; 805 }; 806 } DW43; 807 808 // DW44 809 union 810 { 811 struct 812 { 813 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 814 }; 815 struct 816 { 817 uint32_t Value; 818 }; 819 } DW44; 820 821 // DW45 822 union 823 { 824 struct 825 { 826 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 827 }; 828 struct 829 { 830 uint32_t Value; 831 }; 832 } DW45; 833 834 // DW46 835 union 836 { 837 struct 838 { 839 uint32_t VDEncStreamInOutputSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 840 }; 841 struct 842 { 843 uint32_t Value; 844 }; 845 } DW46; 846 847 // DW47 848 union 849 { 850 struct 851 { 852 uint32_t VDEncStreamInInputSurfIndex : MOS_BITFIELD_RANGE( 0, 31); 853 }; 854 struct 855 { 856 uint32_t Value; 857 }; 858 } DW47; 859 860 }; 861 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(MeCurbe)) == 48); 862 863 // Integrated stats information 864 struct StatsInfo 865 { 866 uint32_t tileSizeRecord; 867 uint32_t vdencStats; 868 uint32_t pakStats; 869 uint32_t counterBuffer; 870 }; 871 872 //! 873 //! \struct HucPakStitchDmemEncG12 874 //! \brief The struct of Huc Com Dmem 875 //! 876 struct HucPakIntDmem 877 { 878 uint32_t tileSizeRecordOffset[5]; // Tile Size Records, start offset in byte, 0xffffffff means unavailable 879 uint32_t vdencStatOffset[5]; // needed for HEVC VDEnc, VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 880 uint32_t hevcPakStatOffset[5]; // needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 881 uint32_t hevcStreamoutOffset[5]; // needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 882 uint32_t vp9PakStatOffset[5]; // needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 883 uint32_t vp9CounterBufferOffset[5]; // needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 884 uint32_t lastTileBSStartInBytes; // last tile in bitstream for region 4 and region 5 885 uint32_t SliceHeaderSizeinBits; // needed for HEVC dual pipe BRC 886 uint16_t totalSizeInCommandBuffer; // Total size in bytes of valid data in the command buffer 887 uint16_t offsetInCommandBuffer; // Byte offset of the to-be-updated Length (uint32_t ) in the command buffer, 0xffff means unavailable 888 uint16_t picWidthInPixel; // Picture width in pixel 889 uint16_t picHeightInPixel; // Picture hieght in pixel 890 uint16_t totalNumberOfPaks; // [2..4] for Gen11 891 uint16_t numSlices[4]; // this is number of slices in each PAK 892 uint16_t numTiles[4]; // this is number of tiles from each PAK 893 uint16_t picStateStartInBytes; // offset for region 7 and region 8 894 uint8_t codec; // 1: HEVC DP; 2: HEVC VDEnc; 3: VP9 VDEnc 895 uint8_t maxPass; // Max number of BRC pass >=1 896 uint8_t currentPass; // Current BRC pass [1..MAXPass] 897 uint8_t minCUSize; // Minimum CU size (3: 8x8, 4:16x16), HEVC only. 898 uint8_t cabacZeroWordFlag; // Cabac zero flag, HEVC only 899 uint8_t bitdepthLuma; // luma bitdepth, HEVC only 900 uint8_t bitdepthChroma; // chroma bitdepth, HEVC only 901 uint8_t chromaFormatIdc; // chroma format idc, HEVC only 902 uint8_t currFrameBRClevel; // Hevc dual pipe only 903 uint8_t brcUnderFlowEnable; // Hevc dual pipe only 904 uint8_t StitchEnable;// enable stitch cmd for Hevc dual pipe 905 uint8_t reserved1; 906 uint16_t StitchCommandOffset; // offset in region 10 which is the second level batch buffer 907 uint16_t reserved2; 908 uint32_t BBEndforStitch; 909 uint8_t RSVD[16]; 910 }; 911 912 //! 913 //! \struct HucProbDmem 914 //! \brief HUC prob dmem 915 //! 916 struct HucProbDmem 917 { 918 uint32_t HuCPassNum; 919 uint32_t FrameWidth; 920 uint32_t FrameHeight; 921 uint32_t Rsvd32[6]; 922 char SegmentRef[CODEC_VP9_MAX_SEGMENTS]; 923 uint8_t SegmentSkip[CODEC_VP9_MAX_SEGMENTS]; 924 uint8_t SegCodeAbs; 925 uint8_t SegTemporalUpdate; 926 uint8_t LastRefIndex; 927 uint8_t GoldenRefIndex; 928 uint8_t AltRefIndex; 929 uint8_t RefreshFrameFlags; 930 uint8_t RefFrameFlags; 931 uint8_t ContextFrameTypes; 932 HucFrameCtrl FrameCtrl; 933 HucPrevFrameInfo PrevFrameInfo; 934 uint8_t Rsvd[2]; 935 uint8_t FrameToShow; 936 uint8_t LoadKeyFrameDefaultProbs; 937 uint32_t FrameSize; 938 uint32_t VDEncImgStateOffset; 939 uint32_t RePak; 940 uint16_t LFLevelBitOffset; 941 uint16_t QIndexBitOffset; 942 uint16_t SegBitOffset; 943 uint16_t SegLengthInBits; 944 uint16_t UnCompHdrTotalLengthInBits; 945 uint16_t SegUpdateDisable; 946 int32_t RePakThreshold[256]; 947 uint16_t PicStateOffset; 948 uint16_t SLBBSize; 949 uint8_t StreamInEnable; 950 uint8_t StreamInSegEnable; 951 uint8_t DisableDMA; 952 uint8_t IVFHeaderSize; 953 uint8_t PakOnlyEnable; 954 uint8_t Reserved[43]; 955 }; 956 957 958 //! 959 //! \struct HucInputCmdG12 960 //! \brief The struct of Huc input command 961 //! 962 struct HucInputCmdG12 963 { 964 uint8_t SelectionForIndData = 0; 965 uint8_t CmdMode = 0; 966 uint16_t LengthOfTable = 0; 967 968 uint32_t SrcBaseOffset = 0; 969 uint32_t DestBaseOffset = 0; 970 971 uint32_t Reserved[3] = { 0 }; 972 973 uint32_t CopySize = 0; 974 975 uint32_t ReservedCounter[4] = {0}; 976 977 uint32_t SrcAddrBottom = 0; 978 uint32_t SrcAddrTop = 0; 979 uint32_t DestAddrBottom = 0; 980 uint32_t DestAddrTop = 0; 981 }; 982 983 //! 984 //! \struct HucCommandData 985 //! \brief The struct of Huc commands data 986 //! 987 struct HucCommandData 988 { 989 uint32_t TotalCommands; //!< Total Commands in the Data buffer 990 struct 991 { 992 uint16_t ID; //!< Command ID, defined and order must be same as that in DMEM 993 uint16_t SizeOfData; //!< data size in uint32_t 994 uint32_t data[40]; 995 } InputCOM[10]; 996 }; 997 998 // VDENC BRC related buffer size 999 static constexpr uint32_t m_brcStatsBufSize = ((48 + 256) * sizeof(uint32_t)); 1000 static constexpr uint32_t m_brcPakStatsBufSize = (64 * sizeof(uint32_t)); 1001 static constexpr uint32_t m_brcHistoryBufSize = 1152; 1002 // VDENC Pak Int related constants 1003 static constexpr uint32_t m_pakIntDmemOffsetsSize = 120; 1004 static constexpr uint32_t m_pakIntVp9CodecId = 3; 1005 static constexpr uint32_t m_maxNumPipes = 4; 1006 1007 static constexpr uint32_t m_hmeMaxMvLength = 511; 1008 1009 static constexpr uint32_t m_hmeFirstStep = 0; 1010 static constexpr uint32_t m_hmeFollowingStep = 1; 1011 static constexpr uint32_t m_mvShiftFactor32x = 1; 1012 static constexpr uint32_t m_mvShiftFactor16x = 2; 1013 static constexpr uint32_t m_mvShiftFactor4x = 2; 1014 static constexpr uint32_t m_prevMvReadPosition16x = 1; 1015 static constexpr uint32_t m_prevMvReadPosition4x = 0; 1016 1017 // ME CURBE init data for G12 Kernel 1018 static const uint32_t meCurbeInit[48]; 1019 1020 CODEC_PICTURE m_refPicList0[3] = {}; 1021 1022 // Virtual engine 1023 //Scalability 1024 uint8_t m_numPipe = 0; 1025 uint8_t m_numPassesInOnePipe = 0; 1026 bool m_scalableMode = false; 1027 bool m_lastFrameScalableMode = false; 1028 bool m_isTilingSupported = false; 1029 bool m_enableTileStitchByHW = true; 1030 bool m_useVirtualEngine = true; 1031 MOS_COMMAND_BUFFER m_veBatchBuffer[m_numUncompressedSurface][CODECHAL_ENCODE_VP9_MAX_NUM_HCP_PIPE][m_brcMaxNumPasses] = {}; 1032 MOS_COMMAND_BUFFER m_realCmdBuffer = {}; 1033 uint32_t m_sizeOfVEBatchBuffer = 0; 1034 uint8_t m_virtualEngineBBIndex = 0; 1035 uint32_t m_32BlocksRasterized = 0; 1036 CODECHAL_ENCODE_BUFFER m_tileRecordBuffer[m_numUncompressedSurface] = {}; 1037 CODECHAL_ENCODE_BUFFER m_hcpScalabilitySyncBuffer = {}; 1038 1039 // Stats Integration regions 1040 CODECHAL_ENCODE_BUFFER m_tileStatsPakIntegrationBuffer[m_numUncompressedSurface] = {}; 1041 uint32_t m_tileStatsPakIntegrationBufferSize = 0; 1042 CODECHAL_ENCODE_BUFFER m_frameStatsPakIntegrationBuffer = {}; 1043 uint32_t m_frameStatsPakIntegrationBufferSize = 0; 1044 MOS_RESOURCE m_hucPakIntDmemBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][m_brcMaxNumPasses] = {}; 1045 MOS_RESOURCE m_hucPakIntDummyBuffer = {}; 1046 MOS_RESOURCE m_hucPakIntBrcDataBuffer = {}; 1047 StatsInfo m_tileStatsOffset = {}; // Page aligned offsets for HuC PAK Integration kernel input 1048 StatsInfo m_frameStatsOffset = {}; // Page aligned offsets for HuC PAK Integration kernel output 1049 StatsInfo m_statsSize = {}; // Sizes for the stats for HuC PAK Integration kernel input 1050 MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS m_hpuVirtualAddrParams = {}; 1051 // Needed for WA, fix for hang during resolution change 1052 uint16_t m_picWidthInMinBlk = 0; //!< Picture Width aligned to minBlock 1053 uint16_t m_picHeightInMinBlk = 0; //!< Picture Height aligned to minBlock 1054 1055 // Semaphore memory for synchronizing 1056 CODECHAL_ENCODE_BUFFER m_pakIntDoneSemaphoreMem; 1057 CODECHAL_ENCODE_BUFFER m_hucDoneSemaphoreMem[m_maxNumPipes]; 1058 CODECHAL_ENCODE_BUFFER m_stitchWaitSemaphoreMem[m_maxNumPipes]; 1059 // Indexes used to propagate buffers between frames/passes 1060 uint16_t m_lastVdencPictureState2ndLevelBBIndex = 0; 1061 uint8_t m_lastVirtualEngineBBIndex = 0; 1062 1063 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 m_tileParams = nullptr; //!< Pointer to the Tile params 1064 PCODECHAL_ENCODE_SCALABILITY_STATE m_scalabilityState = nullptr; //!< Scalability state 1065 1066 MOS_RESOURCE m_vdencCumulativeCuCountStreamoutSurface = {}; 1067 MOS_RESOURCE m_vdencTileRowStoreBuffer = {}; 1068 1069 bool m_hucPakStitchEnabled = true; 1070 MOS_RESOURCE m_resHucStitchDataBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_ENCODE_VP9_BRC_MAX_NUM_OF_PASSES] = {}; 1071 MHW_BATCH_BUFFER m_HucStitchCmdBatchBuffer = {}; 1072 1073 bool m_pakOnlyModeEnabledForLastPass = false; 1074 1075 //! 1076 //! \brief Constructor 1077 //! 1078 CodechalVdencVp9StateG12(CodechalHwInterface* hwInterface, 1079 CodechalDebugInterface* debugInterface, 1080 PCODECHAL_STANDARD_INFO standardInfo); 1081 1082 //! 1083 //! \brief Destructor 1084 //! 1085 virtual ~CodechalVdencVp9StateG12(); 1086 GetCurrentPipe()1087 int GetCurrentPipe() 1088 { 1089 return (m_numPipe <= 1) ? 0 : (int)(m_currPass) % (int)m_numPipe; 1090 } 1091 GetCurrentPass()1092 int GetCurrentPass() override 1093 { 1094 return (m_numPipe <= 1) ? m_currPass : (int)(m_currPass) / (int)m_numPipe; 1095 } 1096 GetNumPasses()1097 int GetNumPasses() override 1098 { 1099 return m_numPassesInOnePipe; 1100 } 1101 IsLastPipe()1102 bool IsLastPipe() 1103 { 1104 return (GetCurrentPipe() == (m_numPipe - 1)) ? true : false; 1105 } 1106 IsFirstPipe()1107 bool IsFirstPipe() 1108 { 1109 return (GetCurrentPipe() == 0) ? true : false; 1110 } 1111 IsFirstPass()1112 bool IsFirstPass() override 1113 { 1114 return (GetCurrentPass() == 0) ? true : false; 1115 } 1116 IsLastPass()1117 bool IsLastPass() override 1118 { 1119 return (GetCurrentPass() == m_numPassesInOnePipe) ? true : false; 1120 } 1121 UseLegacyCommandBuffer()1122 bool UseLegacyCommandBuffer() 1123 { 1124 return ((!m_scalableMode) || (m_osInterface->pfnGetGpuContext(m_osInterface) == m_renderContext)); 1125 } 1126 IsRenderContext()1127 bool IsRenderContext() 1128 { 1129 return (m_osInterface->pfnGetGpuContext(m_osInterface) == m_renderContext); 1130 } 1131 ToHCPChromaFormat(uint8_t vp9ChromaFormat)1132 uint8_t ToHCPChromaFormat(uint8_t vp9ChromaFormat) 1133 { 1134 HCP_CHROMA_FORMAT_IDC hcpChromaFormat = HCP_CHROMA_FORMAT_YUV420; 1135 1136 switch(vp9ChromaFormat) 1137 { 1138 case VP9_ENCODED_CHROMA_FORMAT_YUV420: 1139 hcpChromaFormat = HCP_CHROMA_FORMAT_YUV420; 1140 break; 1141 case VP9_ENCODED_CHROMA_FORMAT_YUV422: 1142 hcpChromaFormat = HCP_CHROMA_FORMAT_YUV422; 1143 break; 1144 case VP9_ENCODED_CHROMA_FORMAT_YUV444: 1145 hcpChromaFormat = HCP_CHROMA_FORMAT_YUV444; 1146 break; 1147 default: 1148 hcpChromaFormat = HCP_CHROMA_FORMAT_YUV420; 1149 break; 1150 } 1151 return hcpChromaFormat; 1152 } 1153 1154 MOS_STATUS VerifyCommandBufferSize() override; 1155 1156 MOS_STATUS GetCommandBuffer( 1157 PMOS_COMMAND_BUFFER cmdBuffer) override; 1158 1159 MOS_STATUS ReturnCommandBuffer( 1160 PMOS_COMMAND_BUFFER cmdBuffer) override; 1161 1162 MOS_STATUS SubmitCommandBuffer( 1163 PMOS_COMMAND_BUFFER cmdBuffer, 1164 bool bNullRendering) override; 1165 1166 MOS_STATUS SendPrologWithFrameTracking( 1167 PMOS_COMMAND_BUFFER cmdBuffer, 1168 bool frameTrackingRequested, 1169 MHW_MI_MMIOREGISTERS *mmioRegister = nullptr) override; 1170 1171 MOS_STATUS SetSemaphoreMem( 1172 PMOS_RESOURCE semaphoreMem, 1173 PMOS_COMMAND_BUFFER cmdBuffer, 1174 uint32_t value); 1175 1176 MOS_STATUS SendHWWaitCommand( 1177 PMOS_RESOURCE semaphoreMem, 1178 PMOS_COMMAND_BUFFER cmdBuffer, 1179 uint32_t value); 1180 1181 MOS_STATUS UserFeatureKeyReport() override; 1182 1183 MOS_STATUS SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams, 1184 PMOS_SURFACE* refSurface, 1185 PMOS_SURFACE* refSurfaceNonScaled, 1186 PMOS_SURFACE* dsRefSurface4x, 1187 PMOS_SURFACE* dsRefSurface8x) override; 1188 1189 uint16_t GetNumTilesInFrame(); 1190 1191 MOS_STATUS ExecutePictureLevel() override; 1192 1193 MOS_STATUS SetSequenceStructs() override; 1194 1195 MOS_STATUS SetPictureStructs() override; 1196 1197 MOS_STATUS SetRowstoreCachingOffsets() override; 1198 1199 virtual MOS_STATUS AllocateResources() override; 1200 1201 void FreeResources() override; 1202 1203 MOS_STATUS SetMeSurfaceParams(MeSurfaceParams *meSurfaceParams); 1204 1205 MOS_STATUS SetMeCurbeParams(MeCurbeParams *meParams); 1206 1207 MOS_STATUS ExecuteKernelFunctions() override; 1208 1209 MOS_STATUS SetupSegmentationStreamIn() override; 1210 1211 void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams) override; 1212 1213 void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams) override; 1214 1215 MOS_STATUS ExecuteSliceLevel() override; 1216 1217 MOS_STATUS ExecuteDysSliceLevel() override; 1218 1219 MOS_STATUS ExecuteDysPictureLevel() override; 1220 1221 MOS_STATUS Initialize(CodechalSetting * settings) override; 1222 1223 MOS_STATUS InitMmcState() override; 1224 1225 virtual MOS_STATUS GetSystemPipeNumberCommon(); 1226 1227 MOS_STATUS InitKernelStateMe(); 1228 1229 virtual MOS_STATUS SetCurbeMe( 1230 MeCurbeParams* params); 1231 1232 MOS_STATUS SendMeSurfaces( 1233 PMOS_COMMAND_BUFFER cmdBuffer, 1234 MeSurfaceParams* params); 1235 1236 MOS_STATUS InitInterface(); 1237 1238 MOS_STATUS InitKernelStates(); 1239 1240 uint32_t GetMaxBtCount(); 1241 1242 MOS_STATUS ExecuteMeKernel( 1243 MeCurbeParams *meParams, 1244 MeSurfaceParams *meSurfaceParams, 1245 HmeLevel hmeLevel) override; 1246 1247 MOS_STATUS InitKernelStateDys(); 1248 1249 MOS_STATUS ExecuteTileLevel(); 1250 1251 MOS_STATUS SetTileData(); 1252 1253 virtual MOS_STATUS SetTileCommands( 1254 PMOS_COMMAND_BUFFER cmdBuffer); 1255 1256 MOS_STATUS GetStatusReport( 1257 EncodeStatus* encodeStatus, 1258 EncodeStatusReport* encodeStatusReport) override; 1259 1260 MOS_STATUS DecideEncodingPipeNumber(); 1261 1262 MOS_STATUS PlatformCapabilityCheck() override; 1263 1264 uint32_t GetSegmentBlockIndexInFrame( 1265 uint32_t frameWidth, 1266 uint32_t curr32XInTile, 1267 uint32_t curr32YInTile, 1268 uint32_t currTileStartY64aligned, 1269 uint32_t currTileStartX64aligned); 1270 1271 MOS_STATUS InitZigZagToRasterLUTPerTile( 1272 uint32_t tileHeight, 1273 uint32_t tileWidth, 1274 uint32_t currTileStartYInFrame, 1275 uint32_t currTileStartXInFrame); 1276 1277 MOS_STATUS CalculateVdencPictureStateCommandSize() override; 1278 1279 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS CreateHcpPipeBufAddrParams( 1280 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams) override; 1281 1282 MOS_STATUS UpdateCmdBufAttribute( 1283 PMOS_COMMAND_BUFFER cmdBuffer, 1284 bool renderEngineInUse) override; 1285 1286 MOS_STATUS AddMediaVfeCmd( 1287 PMOS_COMMAND_BUFFER cmdBuffer, 1288 SendKernelCmdsParams *params) override; 1289 1290 MOS_STATUS ConstructPicStateBatchBuf( 1291 PMOS_RESOURCE picStateBuffer) override; 1292 1293 virtual MOS_STATUS SetDmemHuCPakInt(); 1294 1295 virtual MOS_STATUS HuCVp9PakInt( 1296 PMOS_COMMAND_BUFFER cmdBuffer); 1297 1298 MOS_STATUS ConfigStitchDataBuffer(); 1299 1300 MOS_STATUS HuCBrcUpdate() override; 1301 MOS_STATUS HuCVp9Prob() override; 1302 MOS_STATUS HuCBrcInitReset() override; 1303 MOS_STATUS SetGpuCtxCreatOption() override; 1304 MOS_STATUS SetAndPopulateVEHintParams( 1305 PMOS_COMMAND_BUFFER cmdBuffer); 1306 MOS_STATUS AddCommandsVp9( 1307 uint32_t commandType, 1308 PMOS_COMMAND_BUFFER cmdBuffer); 1309 MOS_STATUS SetDmemHuCVp9Prob() override; 1310 MOS_STATUS InsertConditionalBBEndWithHucErrorStatus(PMOS_COMMAND_BUFFER cmdBuffer); 1311 MOS_STATUS StoreNumPasses( 1312 EncodeStatusBuffer *encodeStatusBuf, 1313 MhwMiInterface *miInterface, 1314 PMOS_COMMAND_BUFFER cmdBuffer, 1315 uint32_t currPass); 1316 1317 }; 1318 #endif // __CODECHAL_VDENC_VP9_G12_H__ 1319