1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 /** 4 * @file post_codes.h 5 */ 6 7 /* 8 * This aims to be a central point for POST codes used throughout coreboot. 9 * All POST codes should be declared here as macros, and post_code() should 10 * be used with the macros instead of hardcoded values. This allows us to 11 * quickly reference POST codes when nothing is working 12 * 13 * The format for a POST code macro is 14 * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED 15 * Lets's keep it at POST_* instead of POST_CODE_* 16 * 17 * This file is also included by early assembly files. Only use #define s; 18 * no function prototypes allowed here 19 * 20 * DOCUMENTATION: 21 * Please document any and all post codes using Doxygen style comments. We 22 * want to be able to generate a verbose enough documentation that is useful 23 * during debugging. 24 * 25 */ 26 27 #ifndef POST_CODES_H 28 #define POST_CODES_H 29 30 /** 31 * \brief Not an actual post-code - used to clear port80h 32 * 33 */ 34 #define POSTCODE_CODE_CLEAR 0x00 35 36 /** 37 * \brief Entry into 'crt0.s'. reset code jumps to here 38 * 39 * First instruction that gets executed after the reset vector jumps. 40 * This indicates that the reset vector points to the correct code segment. 41 */ 42 #define POSTCODE_RESET_VECTOR_CORRECT 0x01 43 44 /** 45 * \brief Entry into protected mode 46 * 47 * Preparing to enter protected mode. This is POSTed right before changing to 48 * protected mode. 49 */ 50 #define POSTCODE_ENTER_PROTECTED_MODE 0x10 51 52 /** 53 * \brief Start copying coreboot to RAM with decompression if compressed 54 * 55 * POSTed before ramstage is about to be loaded into memory 56 */ 57 #define POSTCODE_PREPARE_RAMSTAGE 0x11 58 59 /** 60 * \brief Copy/decompression finished; jumping to RAM 61 * 62 * This is called after ramstage is loaded in memory, and before 63 * the code jumps there. This represents the end of romstage. 64 */ 65 #define POSTCODE_RAMSTAGE_IS_PREPARED 0x12 66 67 /** 68 * \brief Entry into c_start 69 * 70 * c_start.S is the first code executing in ramstage. 71 */ 72 #define POSTCODE_ENTRY_C_START 0x13 73 74 /** 75 * \brief Entry into bootblock cache-as-RAM code 76 * 77 */ 78 #define POSTCODE_BOOTBLOCK_CAR 0x21 79 80 /** 81 * \brief Entry into pci_scan_bus 82 * 83 * Entered pci_scan_bus() 84 */ 85 #define POSTCODE_ENTER_PCI_SCAN_BUS 0x24 86 87 /** 88 * \brief Exit out of pci_scan_bus 89 * 90 * Exited pci_scan_bus() 91 */ 92 #define POSTCODE_EXIT_PCI_SCAN_BUS 0x25 93 94 /** 95 * \brief Pre-memory init preparation start 96 * 97 * Post code emitted in romstage before making callbacks to allow SoC/mainboard 98 * to prepare params for FSP memory init. 99 */ 100 #define POSTCODE_MEM_PREINIT_PREP_START 0x34 101 102 /** 103 * \brief Pre-memory init preparation end 104 * 105 * Post code emitted in romstage after returning from SoC/mainboard callbacks 106 * to prepare params for FSP memory init. 107 */ 108 #define POSTCODE_MEM_PREINIT_PREP_END 0x36 109 110 /** 111 * \brief Console is initialized 112 * 113 * The console is initialized and is ready for usage 114 */ 115 #define POSTCODE_CONSOLE_READY 0x39 116 117 /** 118 * \brief Console boot message succeeded 119 * 120 * First console message has been successfully sent through the console backend 121 * driver. 122 */ 123 #define POSTCODE_CONSOLE_BOOT_MSG 0x40 124 125 /** 126 * \brief Before enabling the cache 127 * 128 * Going to enable the cache 129 */ 130 #define POSTCODE_ENABLING_CACHE 0x60 131 132 /** 133 * \brief Pre call to RAM stage main() 134 * 135 * POSTed right before RAM stage main() is called from c_start.S 136 */ 137 #define POSTCODE_PRE_HARDWAREMAIN 0x6e 138 139 /** 140 * \brief Entry into coreboot in RAM stage main() 141 * 142 * This is the first call in hardwaremain.c. If this code is POSTed, then 143 * ramstage has successfully loaded and started executing. 144 */ 145 #define POSTCODE_ENTRY_HARDWAREMAIN 0x6f 146 147 /** 148 * \brief Before Device Probe 149 * 150 * Boot State Machine: bs_pre_device() 151 */ 152 #define POSTCODE_BS_PRE_DEVICE 0x70 153 154 /** 155 * \brief Initializing Chips 156 * 157 * Boot State Machine: bs_dev_init_chips() 158 */ 159 #define POSTCODE_BS_DEV_INIT_CHIPS 0x71 160 161 /** 162 * \brief Starting Device Enumeration 163 * 164 * Boot State Machine: bs_dev_enumerate() 165 */ 166 #define POSTCODE_BS_DEV_ENUMERATE 0x72 167 168 /** 169 * \brief Device Resource Allocation 170 * 171 * Boot State Machine: bs_dev_resources() 172 */ 173 #define POSTCODE_BS_DEV_RESOURCES 0x73 174 175 /** 176 * \brief Device Enable 177 * 178 * Boot State Machine: bs_dev_enable() 179 */ 180 #define POSTCODE_BS_DEV_ENABLE 0x74 181 182 /** 183 * \brief Device Initialization 184 * 185 * Boot State Machine: bs_dev_init() 186 */ 187 #define POSTCODE_BS_DEV_INIT 0x75 188 189 /** 190 * \brief After Device Probe 191 * 192 * Boot State Machine: bs_post_device() 193 */ 194 #define POSTCODE_BS_POST_DEVICE 0x76 195 196 /** 197 * \brief OS Resume Check 198 * 199 * Boot State Machine: bs_os_resume_check() 200 */ 201 #define POSTCODE_BS_OS_RESUME_CHECK 0x77 202 203 /** 204 * \brief OS Resume 205 * 206 * Boot State Machine: bs_os_resume() 207 */ 208 #define POSTCODE_BS_OS_RESUME 0x78 209 210 /** 211 * \brief Write Tables 212 * 213 * Boot State Machine: bs_write_tables() 214 */ 215 #define POSTCODE_BS_WRITE_TABLES 0x79 216 217 /** 218 * \brief Load Payload 219 * 220 * Boot State Machine: bs_payload_load() 221 */ 222 #define POSTCODE_BS_PAYLOAD_LOAD 0x7a 223 224 /** 225 * \brief Boot Payload 226 * 227 * Boot State Machine: bs_payload_boot() 228 */ 229 #define POSTCODE_BS_PAYLOAD_BOOT 0x7b 230 231 /** 232 * \brief Before calling FSP Notify (end of firmware) 233 * 234 * Going to call into FSP binary for Notify phase (end of firmware) 235 */ 236 #define POSTCODE_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88 237 238 /** 239 * \brief After calling FSP Notify (end of firmware) 240 * 241 * Going to call into FSP binary for Notify phase (end of firmware) 242 */ 243 #define POSTCODE_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89 244 245 /** 246 * \brief Before calling FSP TempRamInit 247 * 248 * Going to call into FSP binary for TempRamInit phase 249 */ 250 #define POSTCODE_FSP_TEMP_RAM_INIT 0x90 251 252 /** 253 * \brief Before calling FSP TempRamExit 254 * 255 * Going to call into FSP binary for TempRamExit phase 256 */ 257 #define POSTCODE_FSP_TEMP_RAM_EXIT 0x91 258 259 /** 260 * \brief Before calling FSP MemoryInit 261 * 262 * Going to call into FSP binary for MemoryInit phase 263 */ 264 #define POSTCODE_FSP_MEMORY_INIT 0x92 265 266 /** 267 * \brief Before calling FSP SiliconInit 268 * 269 * Going to call into FSP binary for SiliconInit phase 270 */ 271 #define POSTCODE_FSP_SILICON_INIT 0x93 272 273 /** 274 * \brief Before calling FSP Notify (after PCI enumeration) 275 * 276 * Going to call into FSP binary for Notify phase (after PCI enumeration) 277 */ 278 #define POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 279 280 /** 281 * \brief Before calling FSP Notify (ready to boot) 282 * 283 * Going to call into FSP binary for Notify phase (ready to boot) 284 */ 285 #define POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE 0x95 286 287 /** 288 * \brief Indicate OS _PTS entry 289 * 290 * Called from _PTS asl method 291 */ 292 #define POSTCODE_OS_ENTER_PTS 0x96 293 294 /** 295 * \brief Indicate OS _WAK entry 296 * 297 * Called from within _WAK method 298 */ 299 #define POSTCODE_OS_ENTER_WAKE 0x97 300 301 /** 302 * \brief After calling FSP MemoryInit 303 * 304 * FSP binary returned from MemoryInit phase 305 */ 306 #define POSTCODE_FSP_MEMORY_EXIT 0x98 307 308 /** 309 * \brief After calling FSP SiliconInit 310 * 311 * FSP binary returned from SiliconInit phase 312 */ 313 #define POSTCODE_FSP_SILICON_EXIT 0x99 314 315 /** 316 * \brief Entry to write_pirq_table 317 * 318 * coreboot entered write_pirq_table 319 */ 320 #define POSTCODE_X86_WRITE_PIRQ_TABLE 0x9a 321 322 /** 323 * \brief Entry to write_mptable 324 * 325 * coreboot entered write_mptable 326 */ 327 #define POSTCODE_X86_WRITE_MPTABLE 0x9b 328 329 /** 330 * \brief Entry to write_acpi_table 331 * 332 * coreboot entered write_acpi_table 333 */ 334 #define POSTCODE_X86_WRITE_ACPITABLE 0x9c 335 336 /** 337 * \brief Before calling FSP Multiphase SiliconInit 338 * 339 * Going to call into FSP binary for Multiple phase SI Init 340 */ 341 #define POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0 342 343 /** 344 * \brief After calling FSP Multiphase SiliconInit 345 * 346 * FSP binary returned from Multiple phase SI Init 347 */ 348 #define POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 349 350 /** 351 * \brief After calling FSP Notify (after PCI enumeration) 352 * 353 * Going to call into FSP binary for Notify phase (after PCI enumeration) 354 */ 355 #define POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE 0xa2 356 357 /** 358 * \brief After calling FSP Notify (ready to boot) 359 * 360 * Going to call into FSP binary for Notify phase (ready to boot) 361 */ 362 #define POSTCODE_FSP_NOTIFY_AFTER_FINALIZE 0xa3 363 364 /** 365 * \brief Before calling FSP Multiphase MemoryInit 366 * 367 * Going to call into FSP binary for Multiple phase MEM Init 368 */ 369 #define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY 0xa4 370 371 /** 372 * \brief After calling FSP Multiphase MemoryInit 373 * 374 * FSP binary returned from Multiple phase MEM Init 375 */ 376 #define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT 0xa5 377 378 /** 379 * \brief Invalid or corrupt ROM 380 * 381 * Set if firmware failed to find or validate a resource that is stored in ROM. 382 */ 383 #define POSTCODE_INVALID_ROM 0xe0 384 385 /** 386 * \brief Invalid or corrupt CBFS 387 * 388 * Set if firmware failed to find or validate a resource that is stored in CBFS. 389 */ 390 #define POSTCODE_INVALID_CBFS 0xe1 391 392 /** 393 * \brief Vendor binary error 394 * 395 * Set if firmware failed to find or validate a vendor binary, or the binary 396 * generated a fatal error. 397 */ 398 #define POSTCODE_INVALID_VENDOR_BINARY 0xe2 399 400 /** 401 * \brief RAM failure 402 * 403 * Set if RAM could not be initialized. This includes RAM is missing, 404 * unsupported RAM configuration, or RAM failure. 405 */ 406 #define POSTCODE_RAM_FAILURE 0xe3 407 408 /** 409 * \brief Hardware initialization failure 410 * 411 * Set when a required hardware component was not found or is unsupported. 412 */ 413 #define POSTCODE_HW_INIT_FAILURE 0xe4 414 415 /** 416 * \brief Video failure 417 * 418 * Video subsystem failed to initialize. 419 */ 420 #define POSTCODE_VIDEO_FAILURE 0xe5 421 422 /** 423 * \brief TPM failure 424 * 425 * An error with the TPM, either unexpected state or communications failure. 426 */ 427 #define POSTCODE_TPM_FAILURE 0xed 428 429 /** 430 * \brief Not supposed to get here 431 * 432 * A function that should not have returned, returned 433 * 434 * Check the console output for details. 435 */ 436 #define POSTCODE_DEAD_CODE 0xee 437 438 /** 439 * \brief Resume from suspend failed 440 * 441 * This post code is sent when the firmware is expected to resume it is 442 * unable to do so. 443 */ 444 #define POSTCODE_RESUME_FAILURE 0xef 445 446 /** 447 * \brief Jumping to payload 448 * 449 * Called right before jumping to a payload. If the boot sequence stops with 450 * this code, chances are the payload freezes. 451 */ 452 #define POSTCODE_JUMPING_TO_PAYLOAD 0xf3 453 454 /** 455 * \brief Entry into elf boot 456 * 457 * This POST code is called right before invoking jmp_to_elf_entry() 458 * jmp_to_elf_entry() invokes the payload, and should never return 459 */ 460 #define POSTCODE_ENTER_ELF_BOOT 0xf8 461 462 /** 463 * \brief Final code before OS resumes 464 * 465 * Called right before jumping to the OS resume vector. 466 */ 467 #define POSTCODE_OS_RESUME 0xfd 468 469 /** 470 * \brief Final code before OS boots 471 * 472 * This may not be called depending on the payload used. 473 */ 474 #define POSTCODE_OS_BOOT 0xfe 475 476 /** 477 * \brief Elfload fail or die() called 478 * 479 * coreboot was not able to load the payload, no payload was detected 480 * or die() was called. 481 * \n 482 * If this code appears before entering ramstage, then most likely 483 * ramstage is corrupted, and reflashing of the ROM chip is needed. 484 * \n 485 * If this code appears after ramstage, there is a problem with the payload 486 * If the payload was built out-of-tree, check that it was compiled as 487 * a coreboot payload 488 * \n 489 * Check the console output to see exactly where the failure occurred. 490 */ 491 #define POSTCODE_DIE 0xff 492 493 #endif /* POST_CODES_H */ 494