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1# Acer G43T-AM3
2
3The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the
4Acer models Aspire M3800, Aspire M5800 and possibly more.
5
6## Technology
7
8```{eval-rst}
9+------------------+--------------------------------------------------+
10| Northbridge      | Intel G43 (called x4x in coreboot code)          |
11+------------------+--------------------------------------------------+
12| Southbridge      | Intel ICH10R (called i82801jx in coreboot code)  |
13+------------------+--------------------------------------------------+
14| CPU socket       | LGA 775                                          |
15+------------------+--------------------------------------------------+
16| RAM              | 4 x DDR3-1066                                    |
17+------------------+--------------------------------------------------+
18| SuperIO          | ITE IT8720F                                      |
19+------------------+--------------------------------------------------+
20| Audio            | Realtek ALC888S                                  |
21+------------------+--------------------------------------------------+
22| Network          | Intel 82567V-2 Gigabit Ethernet                  |
23+------------------+--------------------------------------------------+
24```
25
26There is no serial port. Serial console output is possible by soldering
27to a point at the corresponding Super I/O pin and patching the
28mainboard-specific code accordingly.
29
30## Status
31
32### Working
33
34Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
35(linux-4.19.50).
36
37+ Intel Core 2 processors at up to FSB 1333
38+ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
39+ Integrated graphics (libgfxinit)
40+ HDMI and VGA ports
41+ Both PCI slots
42+ Both PCI-e slots
43+ USB (8 internal, 4 external)
44+ All six SATA ports
45+ Onboard Ethernet
46+ Onboard sound card with output on the rear stereo connector
47+ PS/2 mouse and keyboard
48    + With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500
49    + With FILO it works without further settings
50+ Temperature readings from the Super I/O (including the CPU temperature
51  via PECI)
52+ Super I/O EC automatic fan control
53+ S3 suspend/resume
54+ Poweroff
55
56### Not working
57
58+ DDR3 memory with 512Mx8 chips (G43 limitation)
59+ 4x4GB of DDR3 memory (works, but showed a single bit error within one
60  pass of Memtest86+ 5.01)
61+ Super I/O voltage reading conversions
62
63### Untested
64
65+ Other audio jacks or the front panel header
66+ S/PDIF output
67+ On-board Firewire
68+ Wake-on-LAN
69
70## Flashing coreboot
71
72```{eval-rst}
73+-------------------+---------------------+
74| Type              | Value               |
75+===================+=====================+
76| Socketed flash    | No                  |
77+-------------------+---------------------+
78| Model             | Macronix MX25L1605D |
79+-------------------+---------------------+
80| Size              | 2 MiB               |
81+-------------------+---------------------+
82| Package           | 8-Pin SOP           |
83+-------------------+---------------------+
84| Write protection  | No                  |
85+-------------------+---------------------+
86| Dual BIOS feature | No                  |
87+-------------------+---------------------+
88| Internal flashing | Yes                 |
89+-------------------+---------------------+
90```
91
92The flash is divided into the following regions, as obtained with
93`ifdtool -f rom.layout backup.rom`:
94```
9500000000:00001fff fd
9600100000:001fffff bios
9700006000:000fffff me
9800002000:00005fff gbe
99```
100
101In general, flashing is possible internally and from an external header. It
102might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E`
103is the correct one, not `MX25L1605`.
104
105### Internal flashing
106
107Internal access to the flash chip is unrestricted. When installing coreboot,
108only the BIOS region should be updated by passing the `--ifd` and `-i bios`
109parameters to flashrom. A full backup is advisable.
110
111Here is an example:
112
113```
114$ sudo flashrom \
115  -p internal \
116  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
117  -r backup.rom
118$ sudo flashrom \
119  -p internal \
120  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
121  --ifd -i bios \
122  -w coreboot.rom
123```
124
125```{eval-rst}
126In addition to the information here, please see the
127:doc:`../../tutorial/flashing_firmware/index`.
128```
129
130### External flashing
131
132The SPI flash chip on this board can be flashed externally through the
133SPI_ROM1 header while the board is off and disconnected from power. There
134seems to be a diode that prevents the external programmer from powering the
135whole board.
136
137The signal assignment on the header is identical to the pinout of the flash
138chip. The pinout diagram below is valid when the PCI slots are on the left
139and the CPU is on the right. Note that HOLD# and WP# must be pulled high
140(to VCC) to be able to flash the chip.
141
142                +---+---+
143     SPI_CSn <- | x | x | -> VCC
144                +---+---+
145    SPI_MISO <- | x | x | -> HOLDn
146                +---+---+
147         WPn <- | x | x | -> SPI_CLK
148                +---+---+
149         GND <- | x | x | -> SPI_MOSI
150                +---+---+
151
152## Intel Management Engine
153
154The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE
155jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash
156Descriptor Security Override Strap" to be set. This disables the ME and also
157disables any read/write restrictions to the flash chip that may be set in the
158Intel Flash Descriptor (IFD) (none on this board). Note that changing this
159jumper only comes into effect when starting the board from a shutdown or
160suspend state, not during normal operation.
161
162To completely remove the ME blob from the flash image and to decrease the size
163of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can
164be used with the `-t`, `-r` and `-S` options.
165
166## Fan control
167
168There are two fan connectors that can be controlled individually. CPU_FAN
169can only control a fan by a PWM signal and SYS_FAN only by voltage. See
170the mainboard's `devicetree.cb` file for how coreboot configures the Super
171I/O to control the fans.
172
173## Variants
174
175Various similar mainboards exist, like the Acer Q45T-AM. During a discussion
176in #coreboot on IRC, ECS was suspected to be the original designer of this
177series of mainboards. They have similar models such as the ECS G43T-WM.
178