1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <cpu/intel/post_codes.h> 4#include <cpu/x86/mtrr.h> 5#include <cpu/x86/cache.h> 6#include <cpu/x86/post_code.h> 7 8.section .init 9.global bootblock_pre_c_entry 10 11.code32 12_cache_as_ram_setup: 13 14bootblock_pre_c_entry: 15 16cache_as_ram: 17 post_code(POSTCODE_BOOTBLOCK_CAR) 18 19 /* Clear/disable fixed MTRRs */ 20 mov $fixed_mtrr_list_size, %ebx 21 xor %eax, %eax 22 xor %edx, %edx 23 24clear_fixed_mtrr: 25 add $-2, %ebx 26 movzwl fixed_mtrr_list(%ebx), %ecx 27 wrmsr 28 jnz clear_fixed_mtrr 29 30 /* Figure out how many MTRRs we have, and clear them out */ 31 mov $MTRR_CAP_MSR, %ecx 32 rdmsr 33 movzb %al, %ebx /* Number of variable MTRRs */ 34 mov $MTRR_PHYS_BASE(0), %ecx 35 xor %eax, %eax 36 xor %edx, %edx 37 38clear_var_mtrr: 39 wrmsr 40 inc %ecx 41 wrmsr 42 inc %ecx 43 dec %ebx 44 jnz clear_var_mtrr 45 post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE) 46 47 /* Configure the default memory type to uncacheable. */ 48 movl $MTRR_DEF_TYPE_MSR, %ecx 49 rdmsr 50 andl $(~0x00000cff), %eax 51 wrmsr 52 53 post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS) 54 55 /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ 56 movl $1, %eax 57 cpuid 58 andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ 59 jz addrsize_set_high 60 movl $0x0f, %edx 61 62 /* Preload high word of address mask (in %edx) for Variable 63 MTRRs 0 and 1. */ 64addrsize_set_high: 65 xorl %eax, %eax 66 movl $MTRR_PHYS_MASK(0), %ecx 67 wrmsr 68 movl $MTRR_PHYS_MASK(1), %ecx 69 wrmsr 70 71 post_code(POSTCODE_SOC_SET_CAR_BASE) 72 73 /* Set Cache-as-RAM base address. */ 74 movl $(MTRR_PHYS_BASE(0)), %ecx 75 movl $_car_mtrr_start, %eax 76 orl $MTRR_TYPE_WRBACK, %eax 77 xorl %edx, %edx 78 wrmsr 79 80 /* Set Cache-as-RAM mask. */ 81 movl $(MTRR_PHYS_MASK(0)), %ecx 82 rdmsr 83 movl $_car_mtrr_mask, %eax 84 orl $MTRR_PHYS_MASK_VALID, %eax 85 wrmsr 86 87 post_code(POSTCODE_SOC_ENABLE_MTRRS) 88 89 /* Enable MTRR. */ 90 movl $MTRR_DEF_TYPE_MSR, %ecx 91 rdmsr 92 orl $MTRR_DEF_TYPE_EN, %eax 93 wrmsr 94 95 post_code(POSTCODE_SOC_ENABLE_CACHE) 96 97 /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ 98 movl %cr0, %eax 99 andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax 100 invd 101 movl %eax, %cr0 102 103 /* Read then clear the CAR region. This will also fill up the cache. 104 * IMPORTANT: The read is mandatory. 105 */ 106 cld 107 movl $_car_mtrr_start, %edi 108 movl $_car_mtrr_size, %ecx 109 shr $2, %ecx 110 movl %ecx, %ebx 111 movl %edi, %esi 112 rep lodsl 113 movl %ebx, %ecx 114 xorl %eax, %eax 115 rep stosl 116 117 post_code(POSTCODE_SOC_DISABLE_CACHE) 118 /* Enable Cache-as-RAM mode by disabling cache. */ 119 movl %cr0, %eax 120 orl $CR0_CacheDisable, %eax 121 movl %eax, %cr0 122 123 /* Enable cache for our code in Flash because we do XIP here */ 124 movl $MTRR_PHYS_BASE(1), %ecx 125 xorl %edx, %edx 126 movl $_program, %eax 127 andl $_xip_mtrr_mask, %eax 128 orl $MTRR_TYPE_WRPROT, %eax 129 wrmsr 130 movl $MTRR_PHYS_MASK(1), %ecx 131 rdmsr 132 movl $_xip_mtrr_mask, %eax 133 orl $MTRR_PHYS_MASK_VALID, %eax 134 wrmsr 135 136 post_code(POSTCODE_SOC_FILL_CACHE) 137 /* Enable cache. */ 138 movl %cr0, %eax 139 andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax 140 movl %eax, %cr0 141 142 /* Setup the stack. */ 143 mov $_ecar_stack, %esp 144 145 /* Need to align stack to 16 bytes at call instruction. Account for 146 the pushes below. */ 147 andl $0xfffffff0, %esp 148 subl $4, %esp 149 150 /* push TSC and BIST to stack */ 151 movd %mm0, %eax 152 pushl %eax /* BIST */ 153 movd %mm2, %eax 154 pushl %eax /* tsc[63:32] */ 155 movd %mm1, %eax 156 pushl %eax /* tsc[31:0] */ 157 158 /* Copy .data section content to Cache-As-Ram */ 159#include <cpu/x86/copy_data_section.inc> 160 161before_c_entry: 162 post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) 163 call bootblock_c_entry_bist 164 165 /* Should never see this postcode */ 166 post_code(POSTCODE_DEAD_CODE) 167 168.Lhlt: 169 hlt 170 jmp .Lhlt 171 172fixed_mtrr_list: 173 .word MTRR_FIX_64K_00000 174 .word MTRR_FIX_16K_80000 175 .word MTRR_FIX_16K_A0000 176 .word MTRR_FIX_4K_C0000 177 .word MTRR_FIX_4K_C8000 178 .word MTRR_FIX_4K_D0000 179 .word MTRR_FIX_4K_D8000 180 .word MTRR_FIX_4K_E0000 181 .word MTRR_FIX_4K_E8000 182 .word MTRR_FIX_4K_F0000 183 .word MTRR_FIX_4K_F8000 184fixed_mtrr_list_size = . - fixed_mtrr_list 185 186_cache_as_ram_setup_end: 187