1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _PCH_GPIO_H 4 #define _PCH_GPIO_H 5 6 #include <soc/gpe.h> 7 #include <soc/gpio.h> 8 9 /* Pad configuration in ramstage */ 10 static const struct pad_config gpio_table[] = { 11 /* ------- GPIO Group GPP_A ------- */ 12 /* GPP_A0 - RCIN# */ 13 PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), 14 /* GPP_A1 - LAD0 */ 15 PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), 16 /* GPP_A2 - LAD1 */ 17 PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), 18 /* GPP_A3 - LAD2 */ 19 PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), 20 /* GPP_A4 - LAD3 */ 21 PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), 22 /* GPP_A5 - LFRAME# */ 23 PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), 24 /* GPP_A6 - SERIRQ */ 25 PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), 26 /* GPP_A7 - GPIO */ 27 PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), 28 /* GPP_A8 - CLKRUN# */ 29 PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), 30 /* GPP_A9 - CLKOUT_LPC0 */ 31 PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), 32 /* GPP_A10 - CLKOUT_LPC1 */ 33 PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), 34 /* GPP_A11 - GPIO */ 35 PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), 36 /* GPP_A12 - GPIO */ 37 PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF), 38 /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ 39 PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), 40 /* GPP_A14 - SUS_STAT# */ 41 PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), 42 /* GPP_A15 - SUS_ACK# */ 43 PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), 44 /* GPP_A16 - GPIO */ 45 PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), 46 /* GPP_A17 - GPIO */ 47 PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), 48 /* GPP_A18 - GPIO */ 49 PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), 50 /* GPP_A19 - GPIO */ 51 PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), 52 /* GPP_A20 - GPIO */ 53 PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, OFF), 54 /* GPP_A21 - GPIO */ 55 PAD_CFG_GPI_INT(GPP_A21, NONE, PLTRST, OFF), 56 /* GPP_A22 - GPIO */ 57 PAD_CFG_GPI_INT(GPP_A22, NONE, PLTRST, OFF), 58 /* GPP_A23 - GPIO */ 59 PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), 60 61 /* ------- GPIO Group GPP_B ------- */ 62 /* GPP_B0 - GPIO */ 63 PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), 64 /* GPP_B1 - GPIO */ 65 PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), 66 /* GPP_B2 - GPIO */ 67 PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), 68 /* GPP_B3 - GPIO */ 69 PAD_CFG_GPO(GPP_B3, 1, DEEP), 70 /* GPP_B4 - CPU_GP3 */ 71 PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), 72 /* GPP_B5 - GPIO */ 73 PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF), 74 /* GPP_B6 - GPIO */ 75 PAD_CFG_GPI_INT(GPP_B6, NONE, PLTRST, OFF), 76 /* GPP_B7 - NC */ 77 PAD_NC(GPP_B7, NONE), 78 /* GPP_B8 - GPIO */ 79 PAD_CFG_GPI_INT(GPP_B8, UP_5K, PLTRST, OFF), 80 /* GPP_B9 - GPIO */ 81 PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF), 82 /* GPP_B10 - GPIO */ 83 PAD_CFG_GPI_INT(GPP_B10, NONE, PLTRST, OFF), 84 /* GPP_B11 - GPIO */ 85 _PAD_CFG_STRUCT(GPP_B11, 86 PAD_FUNC(GPIO) | PAD_RESET(PWROK) | 87 PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | 88 PAD_BUF(NO_DISABLE), 89 PAD_PULL(NONE)), 90 /* GPP_B12 - SLP_S0# */ 91 PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), 92 /* GPP_B13 - PLTRST# */ 93 PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), 94 /* GPP_B14 - SPKR */ 95 PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), 96 /* GPP_B15 - GPIO */ 97 PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), 98 /* GPP_B16 - GPIO */ 99 PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), 100 /* GPP_B17 - GPIO */ 101 PAD_CFG_GPO(GPP_B17, 1, DEEP), 102 /* GPP_B18 - GPIO */ 103 PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), 104 /* GPP_B19 - GPIO */ 105 PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), 106 /* GPP_B20 - GPIO */ 107 PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), 108 /* GPP_B21 - GPIO */ 109 PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), 110 /* GPP_B22 - GPIO */ 111 PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), 112 /* GPP_B23 - PCHHOT# */ 113 PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2), 114 115 /* ------- GPIO Group GPP_C ------- */ 116 /* GPP_C0 - SMBCLK */ 117 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), 118 /* GPP_C1 - SMBDATA */ 119 PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), 120 /* GPP_C2 - GPIO */ 121 PAD_CFG_GPO(GPP_C2, 1, DEEP), 122 /* GPP_C3 - SML0CLK */ 123 PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), 124 /* GPP_C4 - SML0DATA */ 125 PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), 126 /* GPP_C5 - GPIO */ 127 PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), 128 /* GPP_C6 - RESERVED */ 129 /* GPP_C7 - RESERVED */ 130 /* GPP_C8 - UART0_RXD */ 131 PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), 132 /* GPP_C9 - UART0_TXD */ 133 PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), 134 /* GPP_C10 - UART0_RTS# */ 135 PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), 136 /* GPP_C11 - UART0_CTS# */ 137 PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), 138 /* GPP_C12 - GPIO */ 139 PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF), 140 /* GPP_C13 - GPIO */ 141 PAD_CFG_GPI_INT(GPP_C13, NONE, PLTRST, OFF), 142 /* GPP_C14 - GPIO */ 143 PAD_CFG_GPI_INT(GPP_C14, NONE, PLTRST, OFF), 144 /* GPP_C15 - GPIO */ 145 PAD_CFG_GPI_INT(GPP_C15, NONE, PLTRST, OFF), 146 /* GPP_C16 - GPIO */ 147 PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), 148 /* GPP_C17 - GPIO */ 149 PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), 150 /* GPP_C18 - GPIO */ 151 PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), 152 /* GPP_C19 - GPIO */ 153 PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), 154 /* GPP_C20 - UART2_RXD */ 155 PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), 156 /* GPP_C21 - UART2_TXD */ 157 PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), 158 /* GPP_C22 - UART2_RTS# */ 159 PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), 160 /* GPP_C23 - GPIO */ 161 PAD_CFG_GPI_SCI_LOW(GPP_C23, NONE, DEEP, LEVEL), 162 163 /* ------- GPIO Group GPP_D ------- */ 164 /* GPP_D0 - GPIO */ 165 PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, OFF), 166 /* GPP_D1 - GPIO */ 167 PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, OFF), 168 /* GPP_D2 - GPIO */ 169 PAD_CFG_GPI_INT(GPP_D2, NONE, PLTRST, OFF), 170 /* GPP_D3 - GPIO */ 171 PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, OFF), 172 /* GPP_D4 - GPIO */ 173 PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), 174 /* GPP_D5 - I2S_SFRM */ 175 PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), 176 /* GPP_D6 - I2S_TXD */ 177 PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), 178 /* GPP_D7 - I2S_RXD */ 179 PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), 180 /* GPP_D8 - I2S_SCLK */ 181 PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), 182 /* GPP_D9 - GPIO */ 183 PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF), 184 /* GPP_D10 - GPIO */ 185 PAD_CFG_GPI_INT(GPP_D10, NONE, PLTRST, OFF), 186 /* GPP_D11 - GPIO */ 187 PAD_CFG_GPI_INT(GPP_D11, NONE, PLTRST, OFF), 188 /* GPP_D12 - GPIO */ 189 PAD_CFG_GPI_INT(GPP_D12, NONE, PLTRST, OFF), 190 /* GPP_D13 - GPIO */ 191 PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), 192 /* GPP_D14 - GPIO */ 193 PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), 194 /* GPP_D15 - GPIO */ 195 PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), 196 /* GPP_D16 - GPIO */ 197 PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), 198 /* GPP_D17 - GPIO */ 199 PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, OFF), 200 /* GPP_D18 - GPIO */ 201 PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), 202 /* GPP_D19 - DMIC_CLK0 */ 203 PAD_CFG_NF(GPP_D19, UP_20K, PLTRST, NF1), 204 /* GPP_D20 - DMIC_DATA0 */ 205 PAD_CFG_NF(GPP_D20, UP_20K, PLTRST, NF1), 206 /* GPP_D21 - GPIO */ 207 PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), 208 /* GPP_D22 - GPIO */ 209 PAD_CFG_GPI_INT(GPP_D22, NONE, PLTRST, OFF), 210 /* GPP_D23 - GPIO */ 211 PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), 212 213 /* ------- GPIO Group GPP_E ------- */ 214 /* GPP_E0 - SATAXPCIE0 */ 215 PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), 216 /* GPP_E1 - SATAXPCIE1 */ 217 PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), 218 /* GPP_E2 - SATAXPCIE2 */ 219 PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), 220 /* GPP_E3 - CPU_GP0 */ 221 PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), 222 /* GPP_E4 - SATA_DEVSLP0 */ 223 PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), 224 /* GPP_E5 - SATA_DEVSLP1 */ 225 PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), 226 /* GPP_E6 - SATA_DEVSLP2 */ 227 PAD_CFG_NF(GPP_E6, NONE, PLTRST, NF1), 228 /* GPP_E7 - GPIO */ 229 PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF), 230 /* GPP_E8 - SATA_LED# */ 231 PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), 232 /* GPP_E9 - USB_OC0# */ 233 PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), 234 /* GPP_E10 - USB_OC1# */ 235 PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), 236 /* GPP_E11 - USB_OC2# */ 237 PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), 238 /* GPP_E12 - USB_OC3# */ 239 PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), 240 241 /* ------- GPIO Group GPP_F ------- */ 242 /* GPP_F0 - GPIO */ 243 PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), 244 /* GPP_F1 - SATAXPCIE4 */ 245 PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), 246 /* GPP_F2 - GPIO */ 247 PAD_NC(GPP_F2, NONE), 248 /* GPP_F3 - GPIO */ 249 PAD_CFG_GPI_INT(GPP_F3, NONE, PLTRST, OFF), 250 /* GPP_F4 - GPIO */ 251 PAD_CFG_GPI_INT(GPP_F4, NONE, PLTRST, OFF), 252 /* GPP_F5 - GPIO */ 253 PAD_CFG_GPI_INT(GPP_F5, NONE, PLTRST, OFF), 254 /* GPP_F6 - GPIO */ 255 PAD_CFG_GPI_INT(GPP_F6, NONE, PLTRST, OFF), 256 /* GPP_F7 - GPIO */ 257 PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), 258 /* GPP_F8 - GPIO */ 259 PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), 260 /* GPP_F9 - GPIO */ 261 PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), 262 /* GPP_F10 - GPIO */ 263 PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), 264 /* GPP_F11 - GPIO */ 265 PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), 266 /* GPP_F12 - GPIO */ 267 PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), 268 /* GPP_F13 - GPIO */ 269 PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), 270 /* GPP_F14 - GPIO */ 271 PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), 272 /* GPP_F15 - USB_OC4# */ 273 PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), 274 /* GPP_F16 - USB_OC5# */ 275 PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), 276 /* GPP_F17 - USB_OC6# */ 277 PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), 278 /* GPP_F18 - GPIO */ 279 PAD_CFG_GPO(GPP_F18, 1, PLTRST), 280 /* GPP_F19 - GPIO */ 281 PAD_CFG_GPI_INT(GPP_F19, NONE, PLTRST, OFF), 282 /* GPP_F20 - GPIO */ 283 PAD_CFG_GPI_INT(GPP_F20, NONE, PLTRST, OFF), 284 /* GPP_F21 - GPIO */ 285 PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, OFF), 286 /* GPP_F22 - GPIO */ 287 PAD_CFG_GPI_INT(GPP_F22, NONE, PLTRST, OFF), 288 /* GPP_F23 - GPIO */ 289 PAD_CFG_GPI_INT(GPP_F23, NONE, PLTRST, OFF), 290 291 /* ------- GPIO Group GPP_G ------- */ 292 /* GPP_G0 - GPIO */ 293 PAD_CFG_GPI_INT(GPP_G0, NONE, PWROK, OFF), 294 /* GPP_G1 - GPIO */ 295 PAD_CFG_GPI_INT(GPP_G1, NONE, PWROK, OFF), 296 /* GPP_G2 - GPIO */ 297 PAD_CFG_GPI_INT(GPP_G2, NONE, PWROK, OFF), 298 /* GPP_G3 - GPIO */ 299 PAD_CFG_GPI_INT(GPP_G3, NONE, PWROK, OFF), 300 /* GPP_G4 - GPIO */ 301 PAD_CFG_GPO(GPP_G4, 0, DEEP), 302 /* GPP_G5 - GPIO */ 303 PAD_CFG_GPI_INT(GPP_G5, NONE, PWROK, OFF), 304 /* GPP_G6 - GPIO */ 305 _PAD_CFG_STRUCT(GPP_G6, 306 PAD_FUNC(GPIO) | PAD_RESET(PWROK) | 307 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | 308 PAD_BUF(TX_DISABLE), 309 PAD_PULL(NONE)), 310 /* GPP_G7 - GPIO */ 311 PAD_CFG_GPI_INT(GPP_G7, NONE, PWROK, OFF), 312 /* GPP_G8 - GPIO */ 313 PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), 314 /* GPP_G9 - GPIO */ 315 PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), 316 /* GPP_G10 - GPIO */ 317 PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), 318 /* GPP_G11 - GPIO */ 319 PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), 320 /* GPP_G12 - GPIO */ 321 _PAD_CFG_STRUCT(GPP_G12, 322 PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | 323 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | 324 PAD_BUF(TX_DISABLE), 325 PAD_PULL(NONE)), 326 /* GPP_G13 - GPIO */ 327 PAD_CFG_GPO(GPP_G13, 1, PLTRST), 328 /* GPP_G14 - GPIO */ 329 _PAD_CFG_STRUCT(GPP_G14, 330 PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | 331 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | 332 PAD_BUF(TX_DISABLE), 333 PAD_PULL(NONE)), 334 /* GPP_G15 - GPIO */ 335 PAD_CFG_GPO(GPP_G15, 0, PLTRST), 336 /* GPP_G16 - GPIO */ 337 PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), 338 /* GPP_G17 - GPIO */ 339 PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), 340 /* GPP_G18 - GPIO */ 341 PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), 342 /* GPP_G19 - SMI# */ 343 PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), 344 /* GPP_G20 - GPIO */ 345 PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF), 346 /* GPP_G21 - GPIO */ 347 PAD_CFG_GPI_INT(GPP_G21, NONE, PLTRST, OFF), 348 /* GPP_G22 - GPIO */ 349 PAD_CFG_GPI_INT(GPP_G22, NONE, PLTRST, OFF), 350 /* GPP_G23 - GPIO */ 351 PAD_CFG_GPI_INT(GPP_G23, NONE, PLTRST, OFF), 352 353 /* ------- GPIO Group GPP_H ------- */ 354 /* GPP_H0 - GPIO */ 355 PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, OFF), 356 /* GPP_H1 - GPIO */ 357 PAD_NC(GPP_H1, NONE), 358 /* GPP_H2 - GPIO */ 359 PAD_CFG_GPI_INT(GPP_H2, NONE, PLTRST, OFF), 360 /* GPP_H3 - GPIO */ 361 PAD_CFG_GPI_INT(GPP_H3, NONE, PLTRST, OFF), 362 /* GPP_H4 - GPIO */ 363 PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), 364 /* GPP_H5 - GPIO */ 365 PAD_CFG_GPI_INT(GPP_H5, NONE, PLTRST, OFF), 366 /* GPP_H6 - GPIO */ 367 PAD_CFG_GPI_INT(GPP_H6, NONE, PLTRST, OFF), 368 /* GPP_H7 - GPIO */ 369 PAD_CFG_GPI_INT(GPP_H7, NONE, PLTRST, OFF), 370 /* GPP_H8 - GPIO */ 371 PAD_CFG_GPI_INT(GPP_H8, NONE, PLTRST, OFF), 372 /* GPP_H9 - GPIO */ 373 PAD_CFG_GPI_INT(GPP_H9, NONE, PLTRST, OFF), 374 /* GPP_H10 - GPIO */ 375 PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), 376 /* GPP_H11 - GPIO */ 377 PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), 378 /* GPP_H12 - GPIO */ 379 PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), 380 /* GPP_H13 - GPIO */ 381 PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), 382 /* GPP_H14 - GPIO */ 383 PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), 384 /* GPP_H15 - GPIO */ 385 PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), 386 /* GPP_H16 - GPIO */ 387 PAD_CFG_GPI(GPP_H16, NONE, PLTRST), 388 /* GPP_H17 - GPIO */ 389 PAD_CFG_GPO(GPP_H17, 1, PLTRST), 390 /* GPP_H18 - GPIO */ 391 PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), 392 /* GPP_H19 - GPIO */ 393 PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), 394 /* GPP_H20 - GPIO */ 395 PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), 396 /* GPP_H21 - GPIO */ 397 PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), 398 /* GPP_H22 - GPIO */ 399 PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), 400 /* GPP_H23 - GPIO */ 401 PAD_CFG_GPI_INT(GPP_H23, NONE, PWROK, OFF), 402 403 /* -------- GPIO Group GPD -------- */ 404 /* GPD0 - GPIO */ 405 PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), 406 /* GPD1 - GPIO */ 407 PAD_CFG_GPO(GPD1, 0, PWROK), 408 /* GPD2 - LAN_WAKE# */ 409 PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), 410 /* GPD3 - PWRBTN# */ 411 PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), 412 /* GPD4 - SLP_S3# */ 413 PAD_CFG_NF(GPD4, NONE, PWROK, NF1), 414 /* GPD5 - SLP_S4# */ 415 PAD_CFG_NF(GPD5, NONE, PWROK, NF1), 416 /* GPD6 - GPIO */ 417 PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF), 418 /* GPD7 - GPIO */ 419 _PAD_CFG_STRUCT(GPD7, 420 PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | 421 PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | 422 PAD_BUF(TX_DISABLE) | 1, 423 PAD_PULL(NONE)), 424 /* GPD8 - SUSCLK */ 425 PAD_CFG_NF(GPD8, NONE, PWROK, NF1), 426 /* GPD9 - SLP_WLAN# */ 427 PAD_CFG_NF(GPD9, NONE, PWROK, NF1), 428 /* GPD10 - SLP_S5# */ 429 PAD_CFG_NF(GPD10, NONE, PWROK, NF1), 430 /* GPD11 - GPIO */ 431 PAD_CFG_GPO(GPD11, 0, PWROK), 432 433 /* ------- GPIO Group GPP_I ------- */ 434 /* GPP_I0 - DDPB_HPD0 */ 435 PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), 436 /* GPP_I1 - DDPC_HPD1 */ 437 PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), 438 /* GPP_I2 - DDPD_HPD2 */ 439 PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), 440 /* GPP_I3 - DDPE_HPD3 */ 441 PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), 442 /* GPP_I4 - GPIO */ 443 PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF), 444 /* GPP_I5 - DDPB_CTRLCLK */ 445 PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), 446 /* GPP_I6 - DDPB_CTRLDATA */ 447 PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), 448 /* GPP_I7 - DDPC_CTRLCLK */ 449 PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), 450 /* GPP_I8 - DDPC_CTRLDATA */ 451 PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), 452 /* GPP_I9 - DDPD_CTRLCLK */ 453 PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), 454 /* GPP_I10 - DDPD_CTRLDATA */ 455 PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), 456 }; 457 458 /* Early pad configuration in bootblock */ 459 static const struct pad_config early_gpio_table[] = { 460 /* ------- GPIO Group GPP_A ------- */ 461 /* GPP_A0 - RCIN# */ 462 PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), 463 /* GPP_A1 - LAD0 */ 464 PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), 465 /* GPP_A2 - LAD1 */ 466 PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), 467 /* GPP_A3 - LAD2 */ 468 PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), 469 /* GPP_A4 - LAD3 */ 470 PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), 471 /* GPP_A5 - LFRAME# */ 472 PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), 473 /* GPP_A6 - SERIRQ */ 474 PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), 475 476 /* GPP_A8 - CLKRUN# */ 477 PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), 478 /* GPP_A9 - CLKOUT_LPC0 */ 479 PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), 480 /* GPP_A10 - CLKOUT_LPC1 */ 481 PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), 482 483 /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ 484 PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), 485 /* GPP_A14 - SUS_STAT# */ 486 PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), 487 /* GPP_A15 - SUS_ACK# */ 488 PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), 489 }; 490 491 #endif 492