1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 /* 4 * Memory map for QEMU virt machine since 5 * a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019): 6 * 7 * 0..128MiB (0x0000_0000..0x0080_0000) is the space for a flash device. 8 * 128MiB..256MiB (0x0080_0000..0x0100_0000) is used for miscellaneous device I/O. 9 * 256MiB..1GiB (0x0100_0000..0x4000_0000) is reserved for possible future PCI support. 10 * 1GiB.. (0x4000_0000) is RAM and the size depends on initial RAM and device memory settings 11 * 12 * 0x0000_0000..0x0080_0000: Flash memory 13 * 0x0900_0000..0x0900_1000: UART (PL011) 14 * 0x0901_0000..0x0901_1000: RTC (PL031) 15 * 0x0903_0000..0x0903_1000: GPIO (PL061) 16 * 0x0904_0000..0x0904_1000: Secure UART (PL011) 17 * 0x0905_0000..0x0907_0000: SMMU (smmu-v3) 18 * 0x0a00_0000..0x0a00_0200: MMIO (virtio) 19 * 0x0c00_0000..0x0e00_0000: Platform bus 20 * 0x0e00_0000..0x0eff_ffff: Secure SRAM 21 * 0x4000_0000..: RAM 22 */ 23 #define VIRT_UART_BASE 0x09000000 24 #define VIRT_RTC_BASE 0x09010000 25 #define VIRT_GPIO_BASE 0x09030000 26 #define VIRT_SECURE_UART_BASE 0x09040000 27 #define VIRT_SMMU_BASE 0x09050000 28 #define VIRT_MMIO_BASE 0x0a000000 29 #define VIRT_PLATFORM_BUS_BASE 0x0c000000 30 #define VIRT_SECRAM_BASE 0xe000000 31 #define VIRT_PCIE_LOW_MMIO_BASE 0x10000000 32 #define VIRT_PCIE_LOW_MMIO_LIMIT 0x3efeffff 33 /* 34 * From hw/arm/virt.c: 35 * Highmem IO Regions: This memory map is floating, located after the RAM. 36 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 37 * top of the RAM, so that its base get the same alignment as the size, 38 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 39 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 40 * Note the extended_memmap is sized so that it eventually also includes the 41 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 42 * index of base_memmap). 43 */ 44 #define VIRT_PCIE_ECAM_BASE 0x4010000000 /* The one in lower memory does not seem to work */ 45 #define VIRT_PCIE_ECAM_SIZE (256 * MiB) 46 #define VIRT_PCIE_HIGH_MMIO_BASE 0x8000000000ULL 47 #define VIRT_PCIE_HIGH_MMIO_LIMIT 0xffffffffffULL 48